1 /* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
2 * pci.c: UltraSparc PCI controller support.
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/sched.h>
14 #include <linux/capability.h>
15 #include <linux/errno.h>
16 #include <linux/smp_lock.h>
17 #include <linux/init.h>
19 #include <asm/uaccess.h>
21 #include <asm/pgtable.h>
26 unsigned long pci_memspace_mask = 0xffffffffUL;
29 /* A "nop" PCI implementation. */
30 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
31 unsigned long off, unsigned long len,
36 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
37 unsigned long off, unsigned long len,
44 /* List of all PCI controllers found in the system. */
45 struct pci_controller_info *pci_controller_root = NULL;
47 /* Each PCI controller found gets a unique index. */
48 int pci_num_controllers = 0;
50 volatile int pci_poke_in_progress;
51 volatile int pci_poke_cpu = -1;
52 volatile int pci_poke_faulted;
54 static DEFINE_SPINLOCK(pci_poke_lock);
56 void pci_config_read8(u8 *addr, u8 *ret)
61 spin_lock_irqsave(&pci_poke_lock, flags);
62 pci_poke_cpu = smp_processor_id();
63 pci_poke_in_progress = 1;
65 __asm__ __volatile__("membar #Sync\n\t"
66 "lduba [%1] %2, %0\n\t"
69 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
71 pci_poke_in_progress = 0;
73 if (!pci_poke_faulted)
75 spin_unlock_irqrestore(&pci_poke_lock, flags);
78 void pci_config_read16(u16 *addr, u16 *ret)
83 spin_lock_irqsave(&pci_poke_lock, flags);
84 pci_poke_cpu = smp_processor_id();
85 pci_poke_in_progress = 1;
87 __asm__ __volatile__("membar #Sync\n\t"
88 "lduha [%1] %2, %0\n\t"
91 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
93 pci_poke_in_progress = 0;
95 if (!pci_poke_faulted)
97 spin_unlock_irqrestore(&pci_poke_lock, flags);
100 void pci_config_read32(u32 *addr, u32 *ret)
105 spin_lock_irqsave(&pci_poke_lock, flags);
106 pci_poke_cpu = smp_processor_id();
107 pci_poke_in_progress = 1;
108 pci_poke_faulted = 0;
109 __asm__ __volatile__("membar #Sync\n\t"
110 "lduwa [%1] %2, %0\n\t"
113 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
115 pci_poke_in_progress = 0;
117 if (!pci_poke_faulted)
119 spin_unlock_irqrestore(&pci_poke_lock, flags);
122 void pci_config_write8(u8 *addr, u8 val)
126 spin_lock_irqsave(&pci_poke_lock, flags);
127 pci_poke_cpu = smp_processor_id();
128 pci_poke_in_progress = 1;
129 pci_poke_faulted = 0;
130 __asm__ __volatile__("membar #Sync\n\t"
131 "stba %0, [%1] %2\n\t"
134 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
136 pci_poke_in_progress = 0;
138 spin_unlock_irqrestore(&pci_poke_lock, flags);
141 void pci_config_write16(u16 *addr, u16 val)
145 spin_lock_irqsave(&pci_poke_lock, flags);
146 pci_poke_cpu = smp_processor_id();
147 pci_poke_in_progress = 1;
148 pci_poke_faulted = 0;
149 __asm__ __volatile__("membar #Sync\n\t"
150 "stha %0, [%1] %2\n\t"
153 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
155 pci_poke_in_progress = 0;
157 spin_unlock_irqrestore(&pci_poke_lock, flags);
160 void pci_config_write32(u32 *addr, u32 val)
164 spin_lock_irqsave(&pci_poke_lock, flags);
165 pci_poke_cpu = smp_processor_id();
166 pci_poke_in_progress = 1;
167 pci_poke_faulted = 0;
168 __asm__ __volatile__("membar #Sync\n\t"
169 "stwa %0, [%1] %2\n\t"
172 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
174 pci_poke_in_progress = 0;
176 spin_unlock_irqrestore(&pci_poke_lock, flags);
179 /* Probe for all PCI controllers in the system. */
180 extern void sabre_init(int, char *);
181 extern void psycho_init(int, char *);
182 extern void schizo_init(int, char *);
183 extern void schizo_plus_init(int, char *);
184 extern void tomatillo_init(int, char *);
185 extern void sun4v_pci_init(int, char *);
189 void (*init)(int, char *);
190 } pci_controller_table[] __initdata = {
191 { "SUNW,sabre", sabre_init },
192 { "pci108e,a000", sabre_init },
193 { "pci108e,a001", sabre_init },
194 { "SUNW,psycho", psycho_init },
195 { "pci108e,8000", psycho_init },
196 { "SUNW,schizo", schizo_init },
197 { "pci108e,8001", schizo_init },
198 { "SUNW,schizo+", schizo_plus_init },
199 { "pci108e,8002", schizo_plus_init },
200 { "SUNW,tomatillo", tomatillo_init },
201 { "pci108e,a801", tomatillo_init },
202 { "SUNW,sun4v-pci", sun4v_pci_init },
204 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
205 sizeof(pci_controller_table[0]))
207 static int __init pci_controller_init(char *model_name, int namelen, int node)
211 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
212 if (!strncmp(model_name,
213 pci_controller_table[i].model_name,
215 pci_controller_table[i].init(node, model_name);
219 printk("PCI: Warning unknown controller, model name [%s]\n",
221 printk("PCI: Ignoring controller...\n");
226 static int __init pci_is_controller(char *model_name, int namelen, int node)
230 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
231 if (!strncmp(model_name,
232 pci_controller_table[i].model_name,
240 static int __init pci_controller_scan(int (*handler)(char *, int, int))
246 node = prom_getchild(prom_root_node);
247 while ((node = prom_searchsiblings(node, "pci")) != 0) {
250 if ((len = prom_getproperty(node, "model", namebuf, sizeof(namebuf))) > 0 ||
251 (len = prom_getproperty(node, "compatible", namebuf, sizeof(namebuf))) > 0) {
254 /* Our value may be a multi-valued string in the
255 * case of some compatible properties. For sanity,
256 * only try the first one. */
258 while (namebuf[item_len] && len) {
263 if (handler(namebuf, item_len, node))
267 node = prom_getsibling(node);
276 /* Is there some PCI controller in the system? */
277 int __init pcic_present(void)
279 return pci_controller_scan(pci_is_controller);
282 struct pci_iommu_ops *pci_iommu_ops;
283 EXPORT_SYMBOL(pci_iommu_ops);
285 extern struct pci_iommu_ops pci_sun4u_iommu_ops,
288 /* Find each controller in the system, attach and initialize
289 * software state structure for each and link into the
290 * pci_controller_root. Setup the controller enough such
291 * that bus scanning can be done.
293 static void __init pci_controller_probe(void)
295 if (tlb_type == hypervisor)
296 pci_iommu_ops = &pci_sun4v_iommu_ops;
298 pci_iommu_ops = &pci_sun4u_iommu_ops;
300 printk("PCI: Probing for controllers.\n");
302 pci_controller_scan(pci_controller_init);
305 static void __init pci_scan_each_controller_bus(void)
307 struct pci_controller_info *p;
309 for (p = pci_controller_root; p; p = p->next)
313 extern void clock_probe(void);
314 extern void power_init(void);
316 static int __init pcibios_init(void)
318 pci_controller_probe();
319 if (pci_controller_root == NULL)
322 pci_scan_each_controller_bus();
332 subsys_initcall(pcibios_init);
334 void pcibios_fixup_bus(struct pci_bus *pbus)
336 struct pci_pbm_info *pbm = pbus->sysdata;
338 /* Generic PCI bus probing sets these to point at
339 * &io{port,mem}_resouce which is wrong for us.
341 pbus->resource[0] = &pbm->io_space;
342 pbus->resource[1] = &pbm->mem_space;
345 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
347 struct pci_pbm_info *pbm = pdev->bus->sysdata;
348 struct resource *root = NULL;
350 if (r->flags & IORESOURCE_IO)
351 root = &pbm->io_space;
352 if (r->flags & IORESOURCE_MEM)
353 root = &pbm->mem_space;
358 void pcibios_update_irq(struct pci_dev *pdev, int irq)
362 void pcibios_align_resource(void *data, struct resource *res,
363 unsigned long size, unsigned long align)
367 int pcibios_enable_device(struct pci_dev *pdev, int mask)
372 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
373 struct resource *res)
375 struct pci_pbm_info *pbm = pdev->bus->sysdata;
376 struct resource zero_res, *root;
380 zero_res.flags = res->flags;
382 if (res->flags & IORESOURCE_IO)
383 root = &pbm->io_space;
385 root = &pbm->mem_space;
387 pbm->parent->resource_adjust(pdev, &zero_res, root);
389 region->start = res->start - zero_res.start;
390 region->end = res->end - zero_res.start;
392 EXPORT_SYMBOL(pcibios_resource_to_bus);
394 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
395 struct pci_bus_region *region)
397 struct pci_pbm_info *pbm = pdev->bus->sysdata;
398 struct resource *root;
400 res->start = region->start;
401 res->end = region->end;
403 if (res->flags & IORESOURCE_IO)
404 root = &pbm->io_space;
406 root = &pbm->mem_space;
408 pbm->parent->resource_adjust(pdev, res, root);
410 EXPORT_SYMBOL(pcibios_bus_to_resource);
412 char * __init pcibios_setup(char *str)
417 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
419 /* If the user uses a host-bridge as the PCI device, he may use
420 * this to perform a raw mmap() of the I/O or MEM space behind
423 * This can be useful for execution of x86 PCI bios initialization code
424 * on a PCI card, like the xfree86 int10 stuff does.
426 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
427 enum pci_mmap_state mmap_state)
429 struct pcidev_cookie *pcp = pdev->sysdata;
430 struct pci_pbm_info *pbm;
431 struct pci_controller_info *p;
432 unsigned long space_size, user_offset, user_size;
441 if (p->pbms_same_domain) {
442 unsigned long lowest, highest;
444 lowest = ~0UL; highest = 0UL;
445 if (mmap_state == pci_mmap_io) {
446 if (p->pbm_A.io_space.flags) {
447 lowest = p->pbm_A.io_space.start;
448 highest = p->pbm_A.io_space.end + 1;
450 if (p->pbm_B.io_space.flags) {
451 if (lowest > p->pbm_B.io_space.start)
452 lowest = p->pbm_B.io_space.start;
453 if (highest < p->pbm_B.io_space.end + 1)
454 highest = p->pbm_B.io_space.end + 1;
456 space_size = highest - lowest;
458 if (p->pbm_A.mem_space.flags) {
459 lowest = p->pbm_A.mem_space.start;
460 highest = p->pbm_A.mem_space.end + 1;
462 if (p->pbm_B.mem_space.flags) {
463 if (lowest > p->pbm_B.mem_space.start)
464 lowest = p->pbm_B.mem_space.start;
465 if (highest < p->pbm_B.mem_space.end + 1)
466 highest = p->pbm_B.mem_space.end + 1;
468 space_size = highest - lowest;
471 if (mmap_state == pci_mmap_io) {
472 space_size = (pbm->io_space.end -
473 pbm->io_space.start) + 1;
475 space_size = (pbm->mem_space.end -
476 pbm->mem_space.start) + 1;
480 /* Make sure the request is in range. */
481 user_offset = vma->vm_pgoff << PAGE_SHIFT;
482 user_size = vma->vm_end - vma->vm_start;
484 if (user_offset >= space_size ||
485 (user_offset + user_size) > space_size)
488 if (p->pbms_same_domain) {
489 unsigned long lowest = ~0UL;
491 if (mmap_state == pci_mmap_io) {
492 if (p->pbm_A.io_space.flags)
493 lowest = p->pbm_A.io_space.start;
494 if (p->pbm_B.io_space.flags &&
495 lowest > p->pbm_B.io_space.start)
496 lowest = p->pbm_B.io_space.start;
498 if (p->pbm_A.mem_space.flags)
499 lowest = p->pbm_A.mem_space.start;
500 if (p->pbm_B.mem_space.flags &&
501 lowest > p->pbm_B.mem_space.start)
502 lowest = p->pbm_B.mem_space.start;
504 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
506 if (mmap_state == pci_mmap_io) {
507 vma->vm_pgoff = (pbm->io_space.start +
508 user_offset) >> PAGE_SHIFT;
510 vma->vm_pgoff = (pbm->mem_space.start +
511 user_offset) >> PAGE_SHIFT;
518 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
519 * to the 32-bit pci bus offset for DEV requested by the user.
521 * Basically, the user finds the base address for his device which he wishes
522 * to mmap. They read the 32-bit value from the config space base register,
523 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
524 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
526 * Returns negative error code on failure, zero on success.
528 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
529 enum pci_mmap_state mmap_state)
531 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
532 unsigned long user32 = user_offset & pci_memspace_mask;
533 unsigned long largest_base, this_base, addr32;
536 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
537 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
539 /* Figure out which base address this is for. */
541 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
542 struct resource *rp = &dev->resource[i];
549 if (i == PCI_ROM_RESOURCE) {
550 if (mmap_state != pci_mmap_mem)
553 if ((mmap_state == pci_mmap_io &&
554 (rp->flags & IORESOURCE_IO) == 0) ||
555 (mmap_state == pci_mmap_mem &&
556 (rp->flags & IORESOURCE_MEM) == 0))
560 this_base = rp->start;
562 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
564 if (mmap_state == pci_mmap_io)
567 if (addr32 <= user32 && this_base > largest_base)
568 largest_base = this_base;
571 if (largest_base == 0UL)
574 /* Now construct the final physical address. */
575 if (mmap_state == pci_mmap_io)
576 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
578 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
583 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
586 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
587 enum pci_mmap_state mmap_state)
589 vma->vm_flags |= (VM_IO | VM_RESERVED);
592 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
595 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
596 enum pci_mmap_state mmap_state)
598 /* Our io_remap_pfn_range takes care of this, do nothing. */
601 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
602 * for this architecture. The region in the process to map is described by vm_start
603 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
604 * The pci device structure is provided so that architectures may make mapping
605 * decisions on a per-device or per-bus basis.
607 * Returns a negative error code on failure, zero on success.
609 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
610 enum pci_mmap_state mmap_state,
615 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
619 __pci_mmap_set_flags(dev, vma, mmap_state);
620 __pci_mmap_set_pgprot(dev, vma, mmap_state);
622 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
623 ret = io_remap_pfn_range(vma, vma->vm_start,
625 vma->vm_end - vma->vm_start,
633 /* Return the domain nuber for this pci bus */
635 int pci_domain_nr(struct pci_bus *pbus)
637 struct pci_pbm_info *pbm = pbus->sysdata;
640 if (pbm == NULL || pbm->parent == NULL) {
643 struct pci_controller_info *p = pbm->parent;
646 if (p->pbms_same_domain == 0)
648 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
653 EXPORT_SYMBOL(pci_domain_nr);
655 int pcibios_prep_mwi(struct pci_dev *dev)
657 /* We set correct PCI_CACHE_LINE_SIZE register values for every
658 * device probed on this platform. So there is nothing to check
659 * and this always succeeds.
664 #endif /* !(CONFIG_PCI) */