1 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/of_device.h>
16 #include <asm/iommu.h>
18 #include <asm/starfire.h>
23 #include "iommu_common.h"
24 #include "psycho_common.h"
26 #define DRIVER_NAME "psycho"
27 #define PFX DRIVER_NAME ": "
29 /* Misc. PSYCHO PCI controller register offsets and definitions. */
30 #define PSYCHO_CONTROL 0x0010UL
31 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
32 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
33 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
34 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
35 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
36 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
37 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
38 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
39 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
40 #define PSYCHO_PCIA_CTRL 0x2000UL
41 #define PSYCHO_PCIB_CTRL 0x4000UL
42 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
43 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
44 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
45 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
46 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
47 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
48 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
49 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
50 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
51 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
52 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
53 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
55 /* U2P Programmer's Manual, page 13-55, configuration space
58 * 32 24 23 16 15 11 10 8 7 2 1 0
59 * ---------------------------------------------------------
60 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
61 * ---------------------------------------------------------
63 #define PSYCHO_CONFIG_BASE(PBM) \
64 ((PBM)->config_space | (1UL << 24))
65 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
66 (((unsigned long)(BUS) << 16) | \
67 ((unsigned long)(DEVFN) << 8) | \
68 ((unsigned long)(REG)))
70 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
78 (PSYCHO_CONFIG_BASE(pbm) |
79 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
82 /* PSYCHO error handling support. */
84 /* Helper function of IOMMU error checking, which checks out
85 * the state of the streaming buffers. The IOMMU lock is
86 * held when this is called.
88 * For the PCI error case we know which PBM (and thus which
89 * streaming buffer) caused the error, but for the uncorrectable
90 * error case we do not. So we always check both streaming caches.
92 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
93 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
94 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
95 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
96 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
97 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
98 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
99 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
100 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
101 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
102 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
103 #define PSYCHO_STC_DATA_A 0xb000UL
104 #define PSYCHO_STC_DATA_B 0xc000UL
105 #define PSYCHO_STC_ERR_A 0xb400UL
106 #define PSYCHO_STC_ERR_B 0xc400UL
107 #define PSYCHO_STC_TAG_A 0xb800UL
108 #define PSYCHO_STC_TAG_B 0xc800UL
109 #define PSYCHO_STC_LINE_A 0xb900UL
110 #define PSYCHO_STC_LINE_B 0xc900UL
112 /* When an Uncorrectable Error or a PCI Error happens, we
113 * interrogate the IOMMU state to see if it is the cause.
115 #define PSYCHO_IOMMU_CONTROL 0x0200UL
116 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
117 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
118 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
119 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
120 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
121 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
122 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
123 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
124 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
125 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
126 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
127 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
128 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
129 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
130 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
131 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
132 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
133 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
134 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
135 #define PSYCHO_IOMMU_FLUSH 0x0210UL
136 #define PSYCHO_IOMMU_TAG 0xa580UL
137 #define PSYCHO_IOMMU_DATA 0xa600UL
139 /* Uncorrectable Errors. Cause of the error and the address are
140 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
141 * relating to UPA interface transactions.
143 #define PSYCHO_UE_AFSR 0x0030UL
144 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
145 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
146 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
147 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
148 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
149 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
150 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
151 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
152 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
153 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
154 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
155 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
156 #define PSYCHO_UE_AFAR 0x0038UL
158 static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
160 struct pci_pbm_info *pbm = dev_id;
161 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
162 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
163 unsigned long afsr, afar, error_bits;
166 /* Latch uncorrectable error status. */
167 afar = upa_readq(afar_reg);
168 afsr = upa_readq(afsr_reg);
170 /* Clear the primary/secondary error status bits. */
172 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
173 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
176 upa_writeq(error_bits, afsr_reg);
179 printk("%s: Uncorrectable Error, primary error type[%s]\n",
181 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
183 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
185 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
186 "DMA Write" : "???")))));
187 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
189 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
190 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
191 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
192 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
193 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
194 printk("%s: UE Secondary errors [", pbm->name);
196 if (afsr & PSYCHO_UEAFSR_SPIO) {
200 if (afsr & PSYCHO_UEAFSR_SDRD) {
202 printk("(DMA Read)");
204 if (afsr & PSYCHO_UEAFSR_SDWR) {
206 printk("(DMA Write)");
212 /* Interrogate both IOMMUs for error status. */
213 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
215 psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR);
220 /* Correctable Errors. */
221 #define PSYCHO_CE_AFSR 0x0040UL
222 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
223 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
224 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
225 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
226 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
227 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
228 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
229 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
230 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
231 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
232 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
233 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
234 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
235 #define PSYCHO_CE_AFAR 0x0040UL
237 static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
239 struct pci_pbm_info *pbm = dev_id;
240 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
241 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
242 unsigned long afsr, afar, error_bits;
245 /* Latch error status. */
246 afar = upa_readq(afar_reg);
247 afsr = upa_readq(afsr_reg);
249 /* Clear primary/secondary error status bits. */
251 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
252 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
255 upa_writeq(error_bits, afsr_reg);
258 printk("%s: Correctable Error, primary error type[%s]\n",
260 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
262 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
264 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
265 "DMA Write" : "???")))));
267 /* XXX Use syndrome and afar to print out module string just like
268 * XXX UDB CE trap handler does... -DaveM
270 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
271 "UPA_MID[%02lx] was_block(%d)\n",
273 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
274 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
275 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
276 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
277 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
278 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
279 printk("%s: CE Secondary errors [", pbm->name);
281 if (afsr & PSYCHO_CEAFSR_SPIO) {
285 if (afsr & PSYCHO_CEAFSR_SDRD) {
287 printk("(DMA Read)");
289 if (afsr & PSYCHO_CEAFSR_SDWR) {
291 printk("(DMA Write)");
300 /* PCI Errors. They are signalled by the PCI bus module since they
301 * are associated with a specific bus segment.
303 #define PSYCHO_PCI_AFSR_A 0x2010UL
304 #define PSYCHO_PCI_AFSR_B 0x4010UL
305 #define PSYCHO_PCI_AFAR_A 0x2018UL
306 #define PSYCHO_PCI_AFAR_B 0x4018UL
308 /* XXX What about PowerFail/PowerManagement??? -DaveM */
309 #define PSYCHO_ECC_CTRL 0x0020
310 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
311 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
312 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
313 static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
315 struct of_device *op = of_find_device_by_node(pbm->op->node);
316 unsigned long base = pbm->controller_regs;
323 /* Psycho interrupt property order is:
324 * 0: PCIERR INO for this PBM
329 * 5: POWER MANAGEMENT
332 if (op->num_irqs < 6)
335 /* We really mean to ignore the return result here. Two
336 * PCI controller share the same interrupt numbers and
337 * drive the same front-end hardware. Whichever of the
338 * two get in here first will register the IRQ handler
339 * the second will just error out since we do not pass in
342 err = request_irq(op->irqs[1], psycho_ue_intr, 0,
344 err = request_irq(op->irqs[2], psycho_ce_intr, 0,
347 /* This one, however, ought not to fail. We can just warn
348 * about it since the system can still operate properly even
351 err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
352 "PSYCHO_PCIERR", pbm);
354 printk(KERN_WARNING "%s: Could not register PCIERR, "
355 "err=%d\n", pbm->name, err);
357 /* Enable UE and CE interrupts for controller. */
358 upa_writeq((PSYCHO_ECCCTRL_EE |
360 PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL);
362 /* Enable PCI Error interrupts and clear error
365 tmp = upa_readq(base + PSYCHO_PCIA_CTRL);
366 tmp |= (PSYCHO_PCICTRL_SERR |
367 PSYCHO_PCICTRL_SBH_ERR |
369 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
370 upa_writeq(tmp, base + PSYCHO_PCIA_CTRL);
372 tmp = upa_readq(base + PSYCHO_PCIB_CTRL);
373 tmp |= (PSYCHO_PCICTRL_SERR |
374 PSYCHO_PCICTRL_SBH_ERR |
376 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
377 upa_writeq(tmp, base + PSYCHO_PCIB_CTRL);
380 /* PSYCHO boot time probing and initialization. */
381 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
385 /* Set cache-line size to 64 bytes, this is actually
386 * a nop but I do it for completeness.
388 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
389 0, PCI_CACHE_LINE_SIZE);
390 pci_config_write8(addr, 64 / sizeof(u32));
392 /* Set PBM latency timer to 64 PCI clocks. */
393 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
394 0, PCI_LATENCY_TIMER);
395 pci_config_write8(addr, 64);
398 static void __init psycho_scan_bus(struct pci_pbm_info *pbm,
399 struct device *parent)
401 pbm_config_busmastering(pbm);
402 pbm->is_66mhz_capable = 0;
403 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
405 /* After the PCI bus scan is complete, we can register
406 * the error interrupt handlers.
408 psycho_register_error_handlers(pbm);
411 #define PSYCHO_IRQ_RETRY 0x1a00UL
412 #define PSYCHO_PCIA_DIAG 0x2020UL
413 #define PSYCHO_PCIB_DIAG 0x4020UL
414 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
415 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
416 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
417 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
418 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
419 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
420 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
421 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
423 static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
427 upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY);
429 /* Enable arbiter for all PCI slots. */
430 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL);
431 tmp |= PSYCHO_PCICTRL_AEN;
432 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL);
434 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL);
435 tmp |= PSYCHO_PCICTRL_AEN;
436 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL);
438 /* Disable DMA write / PIO read synchronization on
439 * both PCI bus segments.
440 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
442 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG);
443 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
444 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG);
446 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG);
447 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
448 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG);
451 static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
454 unsigned long base = pbm->controller_regs;
458 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
459 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
460 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
461 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A;
462 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A;
463 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A;
465 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
466 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
467 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
468 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B;
469 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B;
470 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B;
472 /* PSYCHO's streaming buffer lacks ctx flushing. */
473 pbm->stc.strbuf_ctxflush = 0;
474 pbm->stc.strbuf_ctxmatch_base = 0;
476 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
477 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
480 pbm->stc.strbuf_flushflag_pa = (unsigned long)
481 __pa(pbm->stc.strbuf_flushflag);
483 /* Enable the streaming buffer. We have to be careful
484 * just in case OBP left it with LRU locking enabled.
486 * It is possible to control if PBM will be rerun on
487 * line misses. Currently I just retain whatever setting
488 * OBP left us with. All checks so far show it having
491 #undef PSYCHO_STRBUF_RERUN_ENABLE
492 #undef PSYCHO_STRBUF_RERUN_DISABLE
493 control = upa_readq(pbm->stc.strbuf_control);
494 control |= PSYCHO_STRBUF_CTRL_ENAB;
495 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
496 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
497 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
499 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
500 control |= PSYCHO_STRBUF_CTRL_RRDIS;
503 upa_writeq(control, pbm->stc.strbuf_control);
505 pbm->stc.strbuf_enabled = 1;
508 #define PSYCHO_IOSPACE_A 0x002000000UL
509 #define PSYCHO_IOSPACE_B 0x002010000UL
510 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
511 #define PSYCHO_MEMSPACE_A 0x100000000UL
512 #define PSYCHO_MEMSPACE_B 0x180000000UL
513 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
515 static void __init psycho_pbm_init(struct pci_pbm_info *pbm,
516 struct of_device *op, int is_pbm_a)
518 psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO);
519 psycho_pbm_strbuf_init(pbm, is_pbm_a);
520 psycho_scan_bus(pbm, &op->dev);
523 static struct pci_pbm_info * __devinit psycho_find_sibling(u32 upa_portid)
525 struct pci_pbm_info *pbm;
527 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
528 if (pbm->portid == upa_portid)
534 #define PSYCHO_CONFIGSPACE 0x001000000UL
536 static int __devinit psycho_probe(struct of_device *op,
537 const struct of_device_id *match)
539 const struct linux_prom64_registers *pr_regs;
540 struct device_node *dp = op->node;
541 struct pci_pbm_info *pbm;
546 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
549 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
551 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
555 pbm->sibling = psycho_find_sibling(upa_portid);
557 iommu = pbm->sibling->iommu;
559 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
561 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
562 goto out_free_controller;
567 pbm->portid = upa_portid;
569 pr_regs = of_get_property(dp, "reg", NULL);
572 printk(KERN_ERR PFX "No reg property.\n");
576 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
578 pbm->controller_regs = pr_regs[2].phys_addr;
579 pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
582 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A;
583 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A;
584 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL;
586 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B;
587 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B;
588 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL;
591 psycho_controller_hwinit(pbm);
593 err = psycho_iommu_init(pbm, 128, 0xc0000000,
594 0xffffffff, PSYCHO_CONTROL);
598 /* If necessary, hook us up for starfire IRQ translations. */
599 if (this_is_starfire)
600 starfire_hookup(pbm->portid);
603 psycho_pbm_init(pbm, op, is_pbm_a);
605 pbm->next = pci_pbm_root;
609 pbm->sibling->sibling = pbm;
611 dev_set_drvdata(&op->dev, pbm);
626 static struct of_device_id __initdata psycho_match[] = {
629 .compatible = "pci108e,8000",
634 static struct of_platform_driver psycho_driver = {
636 .match_table = psycho_match,
637 .probe = psycho_probe,
640 static int __init psycho_init(void)
642 return of_register_driver(&psycho_driver, &of_bus_type);
645 subsys_initcall(psycho_init);