arch/sparc64/kernel/pci_sabre.c

   1 /* pci_sabre.c: Sabre specific PCI controller support.
   2  *
   3  * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   5  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/types.h>
  10 #include <linux/pci.h>
  11 #include <linux/init.h>
  12 #include <linux/slab.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/of_device.h>
  15
  16 #include <asm/apb.h>
  17 #include <asm/iommu.h>
  18 #include <asm/irq.h>
  19 #include <asm/prom.h>
  20
  21 #include "pci_impl.h"
  22 #include "iommu_common.h"
  23 #include "psycho_common.h"
  24
  25 #define DRIVER_NAME     "sabre"
  26 #define PFX             DRIVER_NAME ": "
  27
  28 /* All SABRE registers are 64-bits.  The following accessor
  29  * routines are how they are accessed.  The REG parameter
  30  * is a physical address.
  31  */
  32 #define sabre_read(__reg) \
  33 ({      u64 __ret; \
  34         __asm__ __volatile__("ldxa [%1] %2, %0" \
  35                              : "=r" (__ret) \
  36                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  37                              : "memory"); \
  38         __ret; \
  39 })
  40 #define sabre_write(__reg, __val) \
  41         __asm__ __volatile__("stxa %0, [%1] %2" \
  42                              : /* no outputs */ \
  43                              : "r" (__val), "r" (__reg), \
  44                                "i" (ASI_PHYS_BYPASS_EC_E) \
  45                              : "memory")
  46
  47 /* SABRE PCI controller register offsets and definitions. */
  48 #define SABRE_UE_AFSR           0x0030UL
  49 #define  SABRE_UEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  50 #define  SABRE_UEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  51 #define  SABRE_UEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  52 #define  SABRE_UEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  53 #define  SABRE_UEAFSR_SDTE       0x0200000000000000UL   /* Secondary DMA Translation Error */
  54 #define  SABRE_UEAFSR_PDTE       0x0100000000000000UL   /* Primary DMA Translation Error */
  55 #define  SABRE_UEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  56 #define  SABRE_UEAFSR_OFF        0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
  57 #define  SABRE_UEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  58 #define SABRE_UECE_AFAR         0x0038UL
  59 #define SABRE_CE_AFSR           0x0040UL
  60 #define  SABRE_CEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  61 #define  SABRE_CEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  62 #define  SABRE_CEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  63 #define  SABRE_CEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  64 #define  SABRE_CEAFSR_ESYND      0x00ff000000000000UL   /* ECC Syndrome */
  65 #define  SABRE_CEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  66 #define  SABRE_CEAFSR_OFF        0x00000000e0000000UL   /* Offset */
  67 #define  SABRE_CEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  68 #define SABRE_UECE_AFAR_ALIAS   0x0048UL        /* Aliases to 0x0038 */
  69 #define SABRE_IOMMU_CONTROL     0x0200UL
  70 #define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
  71 #define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
  72 #define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
  73 #define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
  74 #define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
  75 #define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
  76 #define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
  77 #define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
  78 #define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
  79 #define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
  80 #define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
  81 #define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
  82 #define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
  83 #define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
  84 #define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
  85 #define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
  86 #define SABRE_IOMMU_TSBBASE     0x0208UL
  87 #define SABRE_IOMMU_FLUSH       0x0210UL
  88 #define SABRE_IMAP_A_SLOT0      0x0c00UL
  89 #define SABRE_IMAP_B_SLOT0      0x0c20UL
  90 #define SABRE_IMAP_SCSI         0x1000UL
  91 #define SABRE_IMAP_ETH          0x1008UL
  92 #define SABRE_IMAP_BPP          0x1010UL
  93 #define SABRE_IMAP_AU_REC       0x1018UL
  94 #define SABRE_IMAP_AU_PLAY      0x1020UL
  95 #define SABRE_IMAP_PFAIL        0x1028UL
  96 #define SABRE_IMAP_KMS          0x1030UL
  97 #define SABRE_IMAP_FLPY         0x1038UL
  98 #define SABRE_IMAP_SHW          0x1040UL
  99 #define SABRE_IMAP_KBD          0x1048UL
 100 #define SABRE_IMAP_MS           0x1050UL
 101 #define SABRE_IMAP_SER          0x1058UL
 102 #define SABRE_IMAP_UE           0x1070UL
 103 #define SABRE_IMAP_CE           0x1078UL
 104 #define SABRE_IMAP_PCIERR       0x1080UL
 105 #define SABRE_IMAP_GFX          0x1098UL
 106 #define SABRE_IMAP_EUPA         0x10a0UL
 107 #define SABRE_ICLR_A_SLOT0      0x1400UL
 108 #define SABRE_ICLR_B_SLOT0      0x1480UL
 109 #define SABRE_ICLR_SCSI         0x1800UL
 110 #define SABRE_ICLR_ETH          0x1808UL
 111 #define SABRE_ICLR_BPP          0x1810UL
 112 #define SABRE_ICLR_AU_REC       0x1818UL
 113 #define SABRE_ICLR_AU_PLAY      0x1820UL
 114 #define SABRE_ICLR_PFAIL        0x1828UL
 115 #define SABRE_ICLR_KMS          0x1830UL
 116 #define SABRE_ICLR_FLPY         0x1838UL
 117 #define SABRE_ICLR_SHW          0x1840UL
 118 #define SABRE_ICLR_KBD          0x1848UL
 119 #define SABRE_ICLR_MS           0x1850UL
 120 #define SABRE_ICLR_SER          0x1858UL
 121 #define SABRE_ICLR_UE           0x1870UL
 122 #define SABRE_ICLR_CE           0x1878UL
 123 #define SABRE_ICLR_PCIERR       0x1880UL
 124 #define SABRE_WRSYNC            0x1c20UL
 125 #define SABRE_PCICTRL           0x2000UL
 126 #define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
 127 #define  SABRE_PCICTRL_SERR      0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
 128 #define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
 129 #define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
 130 #define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
 131 #define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
 132 #define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
 133 #define  SABRE_PCICTRL_AEN       0x000000000000000fUL   /* Slot PCI arbitration enables */
 134 #define SABRE_PIOAFSR           0x2010UL
 135 #define  SABRE_PIOAFSR_PMA       0x8000000000000000UL   /* Primary Master Abort */
 136 #define  SABRE_PIOAFSR_PTA       0x4000000000000000UL   /* Primary Target Abort */
 137 #define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
 138 #define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
 139 #define  SABRE_PIOAFSR_SMA       0x0800000000000000UL   /* Secondary Master Abort */
 140 #define  SABRE_PIOAFSR_STA       0x0400000000000000UL   /* Secondary Target Abort */
 141 #define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
 142 #define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
 143 #define  SABRE_PIOAFSR_BMSK      0x0000ffff00000000UL   /* Byte Mask */
 144 #define  SABRE_PIOAFSR_BLK       0x0000000080000000UL   /* Was Block Operation */
 145 #define SABRE_PIOAFAR           0x2018UL
 146 #define SABRE_PCIDIAG           0x2020UL
 147 #define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
 148 #define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
 149 #define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
 150 #define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
 151 #define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
 152 #define SABRE_PCITASR           0x2028UL
 153 #define  SABRE_PCITASR_EF        0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
 154 #define  SABRE_PCITASR_CD        0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
 155 #define  SABRE_PCITASR_AB        0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
 156 #define  SABRE_PCITASR_89        0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
 157 #define  SABRE_PCITASR_67        0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
 158 #define  SABRE_PCITASR_45        0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
 159 #define  SABRE_PCITASR_23        0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
 160 #define  SABRE_PCITASR_01        0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
 161 #define SABRE_PIOBUF_DIAG       0x5000UL
 162 #define SABRE_DMABUF_DIAGLO     0x5100UL
 163 #define SABRE_DMABUF_DIAGHI     0x51c0UL
 164 #define SABRE_IMAP_GFX_ALIAS    0x6000UL        /* Aliases to 0x1098 */
 165 #define SABRE_IMAP_EUPA_ALIAS   0x8000UL        /* Aliases to 0x10a0 */
 166 #define SABRE_IOMMU_VADIAG      0xa400UL
 167 #define SABRE_IOMMU_TCDIAG      0xa408UL
 168 #define SABRE_IOMMU_TAG         0xa580UL
 169 #define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
 170 #define  SABRE_IOMMUTAG_ERR      0x0000000000400000UL   /* Error present */
 171 #define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
 172 #define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
 173 #define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
 174 #define  SABRE_IOMMUTAG_VPN      0x000000000007ffffUL   /* Virtual Page Number [31:13] */
 175 #define SABRE_IOMMU_DATA        0xa600UL
 176 #define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
 177 #define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
 178 #define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
 179 #define SABRE_IOMMUDATA_PPN      0x00000000001fffffUL   /* Physical Page Number [33:13] */
 180 #define SABRE_PCI_IRQSTATE      0xa800UL
 181 #define SABRE_OBIO_IRQSTATE     0xa808UL
 182 #define SABRE_FFBCFG            0xf000UL
 183 #define  SABRE_FFBCFG_SPRQS      0x000000000f000000     /* Slave P_RQST queue size */
 184 #define  SABRE_FFBCFG_ONEREAD    0x0000000000004000     /* Slave supports one outstanding read */
 185 #define SABRE_MCCTRL0           0xf010UL
 186 #define  SABRE_MCCTRL0_RENAB     0x0000000080000000     /* Refresh Enable */
 187 #define  SABRE_MCCTRL0_EENAB     0x0000000010000000     /* Enable all ECC functions */
 188 #define  SABRE_MCCTRL0_11BIT     0x0000000000001000     /* Enable 11-bit column addressing */
 189 #define  SABRE_MCCTRL0_DPP       0x0000000000000f00     /* DIMM Pair Present Bits */
 190 #define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff     /* Refresh Interval */
 191 #define SABRE_MCCTRL1           0xf018UL
 192 #define  SABRE_MCCTRL1_AMDC      0x0000000038000000     /* Advance Memdata Clock */
 193 #define  SABRE_MCCTRL1_ARDC      0x0000000007000000     /* Advance DRAM Read Data Clock */
 194 #define  SABRE_MCCTRL1_CSR       0x0000000000e00000     /* CAS to RAS delay for CBR refresh */
 195 #define  SABRE_MCCTRL1_CASRW     0x00000000001c0000     /* CAS length for read/write */
 196 #define  SABRE_MCCTRL1_RCD       0x0000000000038000     /* RAS to CAS delay */
 197 #define  SABRE_MCCTRL1_CP        0x0000000000007000     /* CAS Precharge */
 198 #define  SABRE_MCCTRL1_RP        0x0000000000000e00     /* RAS Precharge */
 199 #define  SABRE_MCCTRL1_RAS       0x00000000000001c0     /* Length of RAS for refresh */
 200 #define  SABRE_MCCTRL1_CASRW2    0x0000000000000038     /* Must be same as CASRW */
 201 #define  SABRE_MCCTRL1_RSC       0x0000000000000007     /* RAS after CAS hold time */
 202 #define SABRE_RESETCTRL         0xf020UL
 203
 204 #define SABRE_CONFIGSPACE       0x001000000UL
 205 #define SABRE_IOSPACE           0x002000000UL
 206 #define SABRE_IOSPACE_SIZE      0x000ffffffUL
 207 #define SABRE_MEMSPACE          0x100000000UL
 208 #define SABRE_MEMSPACE_SIZE     0x07fffffffUL
 209
 210 static int hummingbird_p;
 211 static struct pci_bus *sabre_root_bus;
 212
 213 /* SABRE error handling support. */
 214 static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
 215                                     unsigned long afsr,
 216                                     unsigned long afar)
 217 {
 218         struct iommu *iommu = pbm->iommu;
 219         unsigned long iommu_tag[16];
 220         unsigned long iommu_data[16];
 221         unsigned long flags;
 222         u64 control;
 223         int i;
 224
 225         spin_lock_irqsave(&iommu->lock, flags);
 226         control = sabre_read(iommu->iommu_control);
 227         if (control & SABRE_IOMMUCTRL_ERR) {
 228                 char *type_string;
 229
 230                 /* Clear the error encountered bit.
 231                  * NOTE: On Sabre this is write 1 to clear,
 232                  *       which is different from Psycho.
 233                  */
 234                 sabre_write(iommu->iommu_control, control);
 235                 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
 236                 case 1:
 237                         type_string = "Invalid Error";
 238                         break;
 239                 case 3:
 240                         type_string = "ECC Error";
 241                         break;
 242                 default:
 243                         type_string = "Unknown";
 244                         break;
 245                 };
 246                 printk("%s: IOMMU Error, type[%s]\n",
 247                        pbm->name, type_string);
 248
 249                 /* Enter diagnostic mode and probe for error'd
 250                  * entries in the IOTLB.
 251                  */
 252                 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
 253                 sabre_write(iommu->iommu_control,
 254                             (control | SABRE_IOMMUCTRL_DENAB));
 255                 for (i = 0; i < 16; i++) {
 256                         unsigned long base = pbm->controller_regs;
 257
 258                         iommu_tag[i] =
 259                                 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
 260                         iommu_data[i] =
 261                                 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
 262                         sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
 263                         sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
 264                 }
 265                 sabre_write(iommu->iommu_control, control);
 266
 267                 for (i = 0; i < 16; i++) {
 268                         unsigned long tag, data;
 269
 270                         tag = iommu_tag[i];
 271                         if (!(tag & SABRE_IOMMUTAG_ERR))
 272                                 continue;
 273
 274                         data = iommu_data[i];
 275                         switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
 276                         case 1:
 277                                 type_string = "Invalid Error";
 278                                 break;
 279                         case 3:
 280                                 type_string = "ECC Error";
 281                                 break;
 282                         default:
 283                                 type_string = "Unknown";
 284                                 break;
 285                         };
 286                         printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
 287                                pbm->name, i, tag, type_string,
 288                                ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
 289                                ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
 290                                ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
 291                         printk("%s: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
 292                                pbm->name, i, data,
 293                                ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
 294                                ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
 295                                ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
 296                                ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
 297                 }
 298         }
 299         spin_unlock_irqrestore(&iommu->lock, flags);
 300 }
 301
 302 static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
 303 {
 304         struct pci_pbm_info *pbm = dev_id;
 305         unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
 306         unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
 307         unsigned long afsr, afar, error_bits;
 308         int reported;
 309
 310         /* Latch uncorrectable error status. */
 311         afar = sabre_read(afar_reg);
 312         afsr = sabre_read(afsr_reg);
 313
 314         /* Clear the primary/secondary error status bits. */
 315         error_bits = afsr &
 316                 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 317                  SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 318                  SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
 319         if (!error_bits)
 320                 return IRQ_NONE;
 321         sabre_write(afsr_reg, error_bits);
 322
 323         /* Log the error. */
 324         printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
 325                pbm->name,
 326                ((error_bits & SABRE_UEAFSR_PDRD) ?
 327                 "DMA Read" :
 328                 ((error_bits & SABRE_UEAFSR_PDWR) ?
 329                  "DMA Write" : "???")),
 330                ((error_bits & SABRE_UEAFSR_PDTE) ?
 331                 ":Translation Error" : ""));
 332         printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
 333                pbm->name,
 334                (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
 335                (afsr & SABRE_UEAFSR_OFF) >> 29UL,
 336                ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
 337         printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
 338         printk("%s: UE Secondary errors [", pbm->name);
 339         reported = 0;
 340         if (afsr & SABRE_UEAFSR_SDRD) {
 341                 reported++;
 342                 printk("(DMA Read)");
 343         }
 344         if (afsr & SABRE_UEAFSR_SDWR) {
 345                 reported++;
 346                 printk("(DMA Write)");
 347         }
 348         if (afsr & SABRE_UEAFSR_SDTE) {
 349                 reported++;
 350                 printk("(Translation Error)");
 351         }
 352         if (!reported)
 353                 printk("(none)");
 354         printk("]\n");
 355
 356         /* Interrogate IOMMU for error status. */
 357         sabre_check_iommu_error(pbm, afsr, afar);
 358
 359         return IRQ_HANDLED;
 360 }
 361
 362 static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
 363 {
 364         struct pci_pbm_info *pbm = dev_id;
 365         unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
 366         unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
 367         unsigned long afsr, afar, error_bits;
 368         int reported;
 369
 370         /* Latch error status. */
 371         afar = sabre_read(afar_reg);
 372         afsr = sabre_read(afsr_reg);
 373
 374         /* Clear primary/secondary error status bits. */
 375         error_bits = afsr &
 376                 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 377                  SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
 378         if (!error_bits)
 379                 return IRQ_NONE;
 380         sabre_write(afsr_reg, error_bits);
 381
 382         /* Log the error. */
 383         printk("%s: Correctable Error, primary error type[%s]\n",
 384                pbm->name,
 385                ((error_bits & SABRE_CEAFSR_PDRD) ?
 386                 "DMA Read" :
 387                 ((error_bits & SABRE_CEAFSR_PDWR) ?
 388                  "DMA Write" : "???")));
 389
 390         /* XXX Use syndrome and afar to print out module string just like
 391          * XXX UDB CE trap handler does... -DaveM
 392          */
 393         printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
 394                "was_block(%d)\n",
 395                pbm->name,
 396                (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
 397                (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
 398                (afsr & SABRE_CEAFSR_OFF) >> 29UL,
 399                ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
 400         printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
 401         printk("%s: CE Secondary errors [", pbm->name);
 402         reported = 0;
 403         if (afsr & SABRE_CEAFSR_SDRD) {
 404                 reported++;
 405                 printk("(DMA Read)");
 406         }
 407         if (afsr & SABRE_CEAFSR_SDWR) {
 408                 reported++;
 409                 printk("(DMA Write)");
 410         }
 411         if (!reported)
 412                 printk("(none)");
 413         printk("]\n");
 414
 415         return IRQ_HANDLED;
 416 }
 417
 418 static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm)
 419 {
 420         unsigned long csr_reg, csr, csr_error_bits;
 421         irqreturn_t ret = IRQ_NONE;
 422         u16 stat;
 423
 424         csr_reg = pbm->controller_regs + SABRE_PCICTRL;
 425         csr = sabre_read(csr_reg);
 426         csr_error_bits =
 427                 csr & SABRE_PCICTRL_SERR;
 428         if (csr_error_bits) {
 429                 /* Clear the errors.  */
 430                 sabre_write(csr_reg, csr);
 431
 432                 /* Log 'em.  */
 433                 if (csr_error_bits & SABRE_PCICTRL_SERR)
 434                         printk("%s: PCI SERR signal asserted.\n",
 435                                pbm->name);
 436                 ret = IRQ_HANDLED;
 437         }
 438         pci_bus_read_config_word(sabre_root_bus, 0,
 439                                  PCI_STATUS, &stat);
 440         if (stat & (PCI_STATUS_PARITY |
 441                     PCI_STATUS_SIG_TARGET_ABORT |
 442                     PCI_STATUS_REC_TARGET_ABORT |
 443                     PCI_STATUS_REC_MASTER_ABORT |
 444                     PCI_STATUS_SIG_SYSTEM_ERROR)) {
 445                 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
 446                        pbm->name, stat);
 447                 pci_bus_write_config_word(sabre_root_bus, 0,
 448                                           PCI_STATUS, 0xffff);
 449                 ret = IRQ_HANDLED;
 450         }
 451         return ret;
 452 }
 453
 454 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
 455 {
 456         struct pci_pbm_info *pbm = dev_id;
 457         unsigned long afsr_reg, afar_reg;
 458         unsigned long afsr, afar, error_bits;
 459         int reported;
 460
 461         afsr_reg = pbm->controller_regs + SABRE_PIOAFSR;
 462         afar_reg = pbm->controller_regs + SABRE_PIOAFAR;
 463
 464         /* Latch error status. */
 465         afar = sabre_read(afar_reg);
 466         afsr = sabre_read(afsr_reg);
 467
 468         /* Clear primary/secondary error status bits. */
 469         error_bits = afsr &
 470                 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
 471                  SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
 472                  SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
 473                  SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
 474         if (!error_bits)
 475                 return sabre_pcierr_intr_other(pbm);
 476         sabre_write(afsr_reg, error_bits);
 477
 478         /* Log the error. */
 479         printk("%s: PCI Error, primary error type[%s]\n",
 480                pbm->name,
 481                (((error_bits & SABRE_PIOAFSR_PMA) ?
 482                  "Master Abort" :
 483                  ((error_bits & SABRE_PIOAFSR_PTA) ?
 484                   "Target Abort" :
 485                   ((error_bits & SABRE_PIOAFSR_PRTRY) ?
 486                    "Excessive Retries" :
 487                    ((error_bits & SABRE_PIOAFSR_PPERR) ?
 488                     "Parity Error" : "???"))))));
 489         printk("%s: bytemask[%04lx] was_block(%d)\n",
 490                pbm->name,
 491                (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
 492                (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
 493         printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
 494         printk("%s: PCI Secondary errors [", pbm->name);
 495         reported = 0;
 496         if (afsr & SABRE_PIOAFSR_SMA) {
 497                 reported++;
 498                 printk("(Master Abort)");
 499         }
 500         if (afsr & SABRE_PIOAFSR_STA) {
 501                 reported++;
 502                 printk("(Target Abort)");
 503         }
 504         if (afsr & SABRE_PIOAFSR_SRTRY) {
 505                 reported++;
 506                 printk("(Excessive Retries)");
 507         }
 508         if (afsr & SABRE_PIOAFSR_SPERR) {
 509                 reported++;
 510                 printk("(Parity Error)");
 511         }
 512         if (!reported)
 513                 printk("(none)");
 514         printk("]\n");
 515
 516         /* For the error types shown, scan both PCI buses for devices
 517          * which have logged that error type.
 518          */
 519
 520         /* If we see a Target Abort, this could be the result of an
 521          * IOMMU translation error of some sort.  It is extremely
 522          * useful to log this information as usually it indicates
 523          * a bug in the IOMMU support code or a PCI device driver.
 524          */
 525         if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
 526                 sabre_check_iommu_error(pbm, afsr, afar);
 527                 pci_scan_for_target_abort(pbm, pbm->pci_bus);
 528         }
 529         if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
 530                 pci_scan_for_master_abort(pbm, pbm->pci_bus);
 531
 532         /* For excessive retries, SABRE/PBM will abort the device
 533          * and there is no way to specifically check for excessive
 534          * retries in the config space status registers.  So what
 535          * we hope is that we'll catch it via the master/target
 536          * abort events.
 537          */
 538
 539         if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
 540                 pci_scan_for_parity_error(pbm, pbm->pci_bus);
 541
 542         return IRQ_HANDLED;
 543 }
 544
 545 static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
 546 {
 547         struct device_node *dp = pbm->op->node;
 548         struct of_device *op;
 549         unsigned long base = pbm->controller_regs;
 550         u64 tmp;
 551         int err;
 552
 553         if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
 554                 dp = dp->parent;
 555
 556         op = of_find_device_by_node(dp);
 557         if (!op)
 558                 return;
 559
 560         /* Sabre/Hummingbird IRQ property layout is:
 561          * 0: PCI ERR
 562          * 1: UE ERR
 563          * 2: CE ERR
 564          * 3: POWER FAIL
 565          */
 566         if (op->num_irqs < 4)
 567                 return;
 568
 569         /* We clear the error bits in the appropriate AFSR before
 570          * registering the handler so that we don't get spurious
 571          * interrupts.
 572          */
 573         sabre_write(base + SABRE_UE_AFSR,
 574                     (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 575                      SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 576                      SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
 577
 578         err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
 579         if (err)
 580                 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
 581                        pbm->name, err);
 582
 583         sabre_write(base + SABRE_CE_AFSR,
 584                     (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 585                      SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
 586
 587         err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
 588         if (err)
 589                 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
 590                        pbm->name, err);
 591         err = request_irq(op->irqs[0], sabre_pcierr_intr, 0,
 592                           "SABRE_PCIERR", pbm);
 593         if (err)
 594                 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
 595                        pbm->name, err);
 596
 597         tmp = sabre_read(base + SABRE_PCICTRL);
 598         tmp |= SABRE_PCICTRL_ERREN;
 599         sabre_write(base + SABRE_PCICTRL, tmp);
 600 }
 601
 602 static void apb_init(struct pci_bus *sabre_bus)
 603 {
 604         struct pci_dev *pdev;
 605
 606         list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
 607                 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
 608                     pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
 609                         u16 word16;
 610
 611                         pci_read_config_word(pdev, PCI_COMMAND, &word16);
 612                         word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 613                                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
 614                                 PCI_COMMAND_IO;
 615                         pci_write_config_word(pdev, PCI_COMMAND, word16);
 616
 617                         /* Status register bits are "write 1 to clear". */
 618                         pci_write_config_word(pdev, PCI_STATUS, 0xffff);
 619                         pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
 620
 621                         /* Use a primary/seconday latency timer value
 622                          * of 64.
 623                          */
 624                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
 625                         pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
 626
 627                         /* Enable reporting/forwarding of master aborts,
 628                          * parity, and SERR.
 629                          */
 630                         pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
 631                                               (PCI_BRIDGE_CTL_PARITY |
 632                                                PCI_BRIDGE_CTL_SERR |
 633                                                PCI_BRIDGE_CTL_MASTER_ABORT));
 634                 }
 635         }
 636 }
 637
 638 static void __init sabre_scan_bus(struct pci_pbm_info *pbm,
 639                                   struct device *parent)
 640 {
 641         static int once;
 642
 643         /* The APB bridge speaks to the Sabre host PCI bridge
 644          * at 66Mhz, but the front side of APB runs at 33Mhz
 645          * for both segments.
 646          *
 647          * Hummingbird systems do not use APB, so they run
 648          * at 66MHZ.
 649          */
 650         if (hummingbird_p)
 651                 pbm->is_66mhz_capable = 1;
 652         else
 653                 pbm->is_66mhz_capable = 0;
 654
 655         /* This driver has not been verified to handle
 656          * multiple SABREs yet, so trap this.
 657          *
 658          * Also note that the SABRE host bridge is hardwired
 659          * to live at bus 0.
 660          */
 661         if (once != 0) {
 662                 printk(KERN_ERR PFX "Multiple controllers unsupported.\n");
 663                 return;
 664         }
 665         once++;
 666
 667         pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
 668         if (!pbm->pci_bus)
 669                 return;
 670
 671         sabre_root_bus = pbm->pci_bus;
 672
 673         apb_init(pbm->pci_bus);
 674
 675         sabre_register_error_handlers(pbm);
 676 }
 677
 678 static void __init sabre_pbm_init(struct pci_pbm_info *pbm,
 679                                   struct of_device *op)
 680 {
 681         struct device_node *dp = op->node;
 682
 683         pbm->name = dp->full_name;
 684         printk("%s: SABRE PCI Bus Module\n", pbm->name);
 685
 686         pbm->numa_node = -1;
 687
 688         pbm->pci_ops = &sun4u_pci_ops;
 689         pbm->config_space_reg_bits = 8;
 690
 691         pbm->index = pci_num_pbms++;
 692
 693         pbm->chip_type = PBM_CHIP_TYPE_SABRE;
 694         pbm->op = op;
 695         pci_get_pbm_props(pbm);
 696
 697         pci_determine_mem_io_space(pbm);
 698
 699         sabre_scan_bus(pbm, &op->dev);
 700 }
 701
 702 static int __devinit sabre_probe(struct of_device *op,
 703                                  const struct of_device_id *match)
 704 {
 705         const struct linux_prom64_registers *pr_regs;
 706         struct device_node *dp = op->node;
 707         struct pci_pbm_info *pbm;
 708         u32 upa_portid, dma_mask;
 709         struct iommu *iommu;
 710         int tsbsize, err;
 711         const u32 *vdma;
 712         u64 clear_irq;
 713
 714         hummingbird_p = (match->data != NULL);
 715         if (!hummingbird_p) {
 716                 struct device_node *cpu_dp;
 717
 718                 /* Of course, Sun has to encode things a thousand
 719                  * different ways, inconsistently.
 720                  */
 721                 for_each_node_by_type(cpu_dp, "cpu") {
 722                         if (!strcmp(cpu_dp->name, "SUNW,UltraSPARC-IIe"))
 723                                 hummingbird_p = 1;
 724                 }
 725         }
 726
 727         err = -ENOMEM;
 728         pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
 729         if (!pbm) {
 730                 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
 731                 goto out_err;
 732         }
 733
 734         iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
 735         if (!iommu) {
 736                 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
 737                 goto out_free_controller;
 738         }
 739
 740         pbm->iommu = iommu;
 741
 742         upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
 743
 744         pbm->portid = upa_portid;
 745
 746         /*
 747          * Map in SABRE register set and report the presence of this SABRE.
 748          */
 749
 750         pr_regs = of_get_property(dp, "reg", NULL);
 751         err = -ENODEV;
 752         if (!pr_regs) {
 753                 printk(KERN_ERR PFX "No reg property\n");
 754                 goto out_free_iommu;
 755         }
 756
 757         /*
 758          * First REG in property is base of entire SABRE register space.
 759          */
 760         pbm->controller_regs = pr_regs[0].phys_addr;
 761
 762         /* Clear interrupts */
 763
 764         /* PCI first */
 765         for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
 766                 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
 767
 768         /* Then OBIO */
 769         for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
 770                 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
 771
 772         /* Error interrupts are enabled later after the bus scan. */
 773         sabre_write(pbm->controller_regs + SABRE_PCICTRL,
 774                     (SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
 775                      SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
 776
 777         /* Now map in PCI config space for entire SABRE. */
 778         pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;
 779
 780         vdma = of_get_property(dp, "virtual-dma", NULL);
 781         if (!vdma) {
 782                 printk(KERN_ERR PFX "No virtual-dma property\n");
 783                 goto out_free_iommu;
 784         }
 785
 786         dma_mask = vdma[0];
 787         switch(vdma[1]) {
 788                 case 0x20000000:
 789                         dma_mask |= 0x1fffffff;
 790                         tsbsize = 64;
 791                         break;
 792                 case 0x40000000:
 793                         dma_mask |= 0x3fffffff;
 794                         tsbsize = 128;
 795                         break;
 796
 797                 case 0x80000000:
 798                         dma_mask |= 0x7fffffff;
 799                         tsbsize = 128;
 800                         break;
 801                 default:
 802                         printk(KERN_ERR PFX "Strange virtual-dma size.\n");
 803                         goto out_free_iommu;
 804         }
 805
 806         err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC);
 807         if (err)
 808                 goto out_free_iommu;
 809
 810         /*
 811          * Look for APB underneath.
 812          */
 813         sabre_pbm_init(pbm, op);
 814
 815         pbm->next = pci_pbm_root;
 816         pci_pbm_root = pbm;
 817
 818         dev_set_drvdata(&op->dev, pbm);
 819
 820         return 0;
 821
 822 out_free_iommu:
 823         kfree(pbm->iommu);
 824
 825 out_free_controller:
 826         kfree(pbm);
 827
 828 out_err:
 829         return err;
 830 }
 831
 832 static struct of_device_id __initdata sabre_match[] = {
 833         {
 834                 .name = "pci",
 835                 .compatible = "pci108e,a001",
 836                 .data = (void *) 1,
 837         },
 838         {
 839                 .name = "pci",
 840                 .compatible = "pci108e,a000",
 841         },
 842         {},
 843 };
 844
 845 static struct of_platform_driver sabre_driver = {
 846         .name           = DRIVER_NAME,
 847         .match_table    = sabre_match,
 848         .probe          = sabre_probe,
 849 };
 850
 851 static int __init sabre_init(void)
 852 {
 853         return of_register_driver(&sabre_driver, &of_bus_type);
 854 }
 855
 856 subsys_initcall(sabre_init);