1 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
3 * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/kernel.h>
7 #include <linux/types.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/of_device.h>
14 #include <asm/iommu.h>
16 #include <asm/pstate.h>
20 #include "iommu_common.h"
22 #define DRIVER_NAME "schizo"
23 #define PFX DRIVER_NAME ": "
25 /* All SCHIZO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
29 #define schizo_read(__reg) \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
37 #define schizo_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
44 /* This is a convention that at least Excalibur and Merlin
45 * follow. I suppose the SCHIZO used in Starcat and friends
48 * The only way I could see this changing is if the newlink
49 * block requires more space in Schizo's address space than
50 * they predicted, thus requiring an address space reorg when
51 * the newer Schizo is taped out.
54 /* Streaming buffer control register. */
55 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
56 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
57 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
58 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
59 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
61 /* IOMMU control register. */
62 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
63 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
64 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
65 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
66 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
67 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
68 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
69 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
70 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
71 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
72 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
73 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
74 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
75 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
76 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
77 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
78 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
79 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
81 /* Schizo config space address format is nearly identical to
84 * 32 24 23 16 15 11 10 8 7 2 1 0
85 * ---------------------------------------------------------
86 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
87 * ---------------------------------------------------------
89 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
90 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
91 (((unsigned long)(BUS) << 16) | \
92 ((unsigned long)(DEVFN) << 8) | \
93 ((unsigned long)(REG)))
95 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
102 bus -= pbm->pci_first_busno;
104 (SCHIZO_CONFIG_BASE(pbm) |
105 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
108 /* SCHIZO error handling support. */
109 enum schizo_error_type {
110 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
113 static DEFINE_SPINLOCK(stc_buf_lock);
114 static unsigned long stc_error_buf[128];
115 static unsigned long stc_tag_buf[16];
116 static unsigned long stc_line_buf[16];
118 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
119 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
120 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
121 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
122 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
124 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
125 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
126 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
128 #define SCHIZO_STCERR_WRITE 0x2UL
129 #define SCHIZO_STCERR_READ 0x1UL
131 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
132 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
133 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
134 #define SCHIZO_STCTAG_READ 0x4000000000000000UL
136 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
137 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
138 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
139 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
140 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
141 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
143 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
144 enum schizo_error_type type)
146 struct strbuf *strbuf = &pbm->stc;
147 unsigned long regbase = pbm->pbm_regs;
148 unsigned long err_base, tag_base, line_base;
152 err_base = regbase + SCHIZO_STC_ERR;
153 tag_base = regbase + SCHIZO_STC_TAG;
154 line_base = regbase + SCHIZO_STC_LINE;
156 spin_lock(&stc_buf_lock);
158 /* This is __REALLY__ dangerous. When we put the
159 * streaming buffer into diagnostic mode to probe
160 * it's tags and error status, we _must_ clear all
161 * of the line tag valid bits before re-enabling
162 * the streaming buffer. If any dirty data lives
163 * in the STC when we do this, we will end up
164 * invalidating it before it has a chance to reach
167 control = schizo_read(strbuf->strbuf_control);
168 schizo_write(strbuf->strbuf_control,
169 (control | SCHIZO_STRBUF_CTRL_DENAB));
170 for (i = 0; i < 128; i++) {
173 val = schizo_read(err_base + (i * 8UL));
174 schizo_write(err_base + (i * 8UL), 0UL);
175 stc_error_buf[i] = val;
177 for (i = 0; i < 16; i++) {
178 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
179 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
180 schizo_write(tag_base + (i * 8UL), 0UL);
181 schizo_write(line_base + (i * 8UL), 0UL);
184 /* OK, state is logged, exit diagnostic mode. */
185 schizo_write(strbuf->strbuf_control, control);
187 for (i = 0; i < 16; i++) {
188 int j, saw_error, first, last;
193 for (j = first; j < last; j++) {
194 unsigned long errval = stc_error_buf[j];
197 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
200 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
201 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
204 if (saw_error != 0) {
205 unsigned long tagval = stc_tag_buf[i];
206 unsigned long lineval = stc_line_buf[i];
207 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
210 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
211 (tagval & SCHIZO_STCTAG_VPN),
212 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
213 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
215 /* XXX Should spit out per-bank error information... -DaveM */
216 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
220 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
221 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
222 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
223 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
224 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
225 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
229 spin_unlock(&stc_buf_lock);
232 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
233 * controller level errors.
236 #define SCHIZO_IOMMU_TAG 0xa580UL
237 #define SCHIZO_IOMMU_DATA 0xa600UL
239 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
240 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
241 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
242 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
243 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
244 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
245 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
247 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
248 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
249 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
251 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
252 enum schizo_error_type type)
254 struct iommu *iommu = pbm->iommu;
255 unsigned long iommu_tag[16];
256 unsigned long iommu_data[16];
261 spin_lock_irqsave(&iommu->lock, flags);
262 control = schizo_read(iommu->iommu_control);
263 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
267 /* Clear the error encountered bit. */
268 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
269 schizo_write(iommu->iommu_control, control);
271 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
273 type_string = "Protection Error";
276 type_string = "Invalid Error";
279 type_string = "TimeOut Error";
283 type_string = "ECC Error";
286 printk("%s: IOMMU Error, type[%s]\n",
287 pbm->name, type_string);
289 /* Put the IOMMU into diagnostic mode and probe
290 * it's TLB for entries with error status.
292 * It is very possible for another DVMA to occur
293 * while we do this probe, and corrupt the system
294 * further. But we are so screwed at this point
295 * that we are likely to crash hard anyways, so
296 * get as much diagnostic information to the
299 schizo_write(iommu->iommu_control,
300 control | SCHIZO_IOMMU_CTRL_DENAB);
302 base = pbm->pbm_regs;
304 for (i = 0; i < 16; i++) {
306 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
308 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
310 /* Now clear out the entry. */
311 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
312 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
315 /* Leave diagnostic mode. */
316 schizo_write(iommu->iommu_control, control);
318 for (i = 0; i < 16; i++) {
319 unsigned long tag, data;
322 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
325 data = iommu_data[i];
326 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
328 type_string = "Protection Error";
331 type_string = "Invalid Error";
334 type_string = "TimeOut Error";
338 type_string = "ECC Error";
341 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
342 "sz(%dK) vpg(%08lx)]\n",
343 pbm->name, i, type_string,
344 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
345 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
346 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
347 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
348 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
349 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
351 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
352 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
353 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
356 if (pbm->stc.strbuf_enabled)
357 __schizo_check_stc_error_pbm(pbm, type);
358 spin_unlock_irqrestore(&iommu->lock, flags);
361 static void schizo_check_iommu_error(struct pci_controller_info *p,
362 enum schizo_error_type type)
364 schizo_check_iommu_error_pbm(&p->pbm_A, type);
365 schizo_check_iommu_error_pbm(&p->pbm_B, type);
368 /* Uncorrectable ECC error status gathering. */
369 #define SCHIZO_UE_AFSR 0x10030UL
370 #define SCHIZO_UE_AFAR 0x10038UL
372 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
373 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
374 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
375 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
376 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
377 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
378 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
379 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
380 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
381 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
382 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
383 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
384 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
385 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
387 static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
389 struct pci_pbm_info *pbm = dev_id;
390 struct pci_controller_info *p = pbm->parent;
391 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
392 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
393 unsigned long afsr, afar, error_bits;
396 /* Latch uncorrectable error status. */
397 afar = schizo_read(afar_reg);
399 /* If either of the error pending bits are set in the
400 * AFSR, the error status is being actively updated by
401 * the hardware and we must re-read to get a clean value.
405 afsr = schizo_read(afsr_reg);
406 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
408 /* Clear the primary/secondary error status bits. */
410 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
411 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
414 schizo_write(afsr_reg, error_bits);
417 printk("%s: Uncorrectable Error, primary error type[%s]\n",
419 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
421 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
423 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
424 "DMA Write" : "???")))));
425 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
427 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
428 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
429 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
430 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
432 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
433 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
434 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
435 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
436 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
437 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
438 printk("%s: UE Secondary errors [", pbm->name);
440 if (afsr & SCHIZO_UEAFSR_SPIO) {
444 if (afsr & SCHIZO_UEAFSR_SDMA) {
452 /* Interrogate IOMMU for error status. */
453 schizo_check_iommu_error(p, UE_ERR);
458 #define SCHIZO_CE_AFSR 0x10040UL
459 #define SCHIZO_CE_AFAR 0x10048UL
461 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
462 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
463 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
464 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
465 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
466 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
467 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
468 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
469 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
470 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
471 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
472 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
473 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
474 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
476 static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
478 struct pci_pbm_info *pbm = dev_id;
479 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
480 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
481 unsigned long afsr, afar, error_bits;
484 /* Latch error status. */
485 afar = schizo_read(afar_reg);
487 /* If either of the error pending bits are set in the
488 * AFSR, the error status is being actively updated by
489 * the hardware and we must re-read to get a clean value.
493 afsr = schizo_read(afsr_reg);
494 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
496 /* Clear primary/secondary error status bits. */
498 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
499 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
502 schizo_write(afsr_reg, error_bits);
505 printk("%s: Correctable Error, primary error type[%s]\n",
507 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
509 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
511 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
512 "DMA Write" : "???")))));
514 /* XXX Use syndrome and afar to print out module string just like
515 * XXX UDB CE trap handler does... -DaveM
517 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
519 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
520 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
521 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
522 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
524 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
525 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
526 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
527 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
528 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
529 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
530 printk("%s: CE Secondary errors [", pbm->name);
532 if (afsr & SCHIZO_CEAFSR_SPIO) {
536 if (afsr & SCHIZO_CEAFSR_SDMA) {
547 #define SCHIZO_PCI_AFSR 0x2010UL
548 #define SCHIZO_PCI_AFAR 0x2018UL
550 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
551 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
552 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
553 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
554 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
555 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
556 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
557 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
558 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
559 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
560 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
561 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
562 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
563 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
564 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
565 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
566 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
568 #define SCHIZO_PCI_CTRL (0x2000UL)
569 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
570 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
571 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
572 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
573 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
574 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
575 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
576 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
577 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
578 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
579 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
580 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
581 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
582 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
583 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
584 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
585 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
586 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
587 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
588 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
589 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
590 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
591 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
592 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
593 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
594 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
595 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
597 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
599 unsigned long csr_reg, csr, csr_error_bits;
600 irqreturn_t ret = IRQ_NONE;
603 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
604 csr = schizo_read(csr_reg);
606 csr & (SCHIZO_PCICTRL_BUS_UNUS |
607 SCHIZO_PCICTRL_TTO_ERR |
608 SCHIZO_PCICTRL_RTRY_ERR |
609 SCHIZO_PCICTRL_DTO_ERR |
610 SCHIZO_PCICTRL_SBH_ERR |
611 SCHIZO_PCICTRL_SERR);
612 if (csr_error_bits) {
613 /* Clear the errors. */
614 schizo_write(csr_reg, csr);
617 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
618 printk("%s: Bus unusable error asserted.\n",
620 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
621 printk("%s: PCI TRDY# timeout error asserted.\n",
623 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
624 printk("%s: PCI excessive retry error asserted.\n",
626 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
627 printk("%s: PCI discard timeout error asserted.\n",
629 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
630 printk("%s: PCI streaming byte hole error asserted.\n",
632 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
633 printk("%s: PCI SERR signal asserted.\n",
637 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
638 if (stat & (PCI_STATUS_PARITY |
639 PCI_STATUS_SIG_TARGET_ABORT |
640 PCI_STATUS_REC_TARGET_ABORT |
641 PCI_STATUS_REC_MASTER_ABORT |
642 PCI_STATUS_SIG_SYSTEM_ERROR)) {
643 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
645 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
651 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
653 struct pci_pbm_info *pbm = dev_id;
654 struct pci_controller_info *p = pbm->parent;
655 unsigned long afsr_reg, afar_reg, base;
656 unsigned long afsr, afar, error_bits;
659 base = pbm->pbm_regs;
661 afsr_reg = base + SCHIZO_PCI_AFSR;
662 afar_reg = base + SCHIZO_PCI_AFAR;
664 /* Latch error status. */
665 afar = schizo_read(afar_reg);
666 afsr = schizo_read(afsr_reg);
668 /* Clear primary/secondary error status bits. */
670 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
671 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
672 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
673 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
674 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
675 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
677 return schizo_pcierr_intr_other(pbm);
678 schizo_write(afsr_reg, error_bits);
681 printk("%s: PCI Error, primary error type[%s]\n",
683 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
685 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
687 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
688 "Excessive Retries" :
689 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
691 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
693 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
694 "Bus Unusable" : "???"))))))));
695 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
697 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
698 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
699 ((afsr & SCHIZO_PCIAFSR_CFG) ?
701 ((afsr & SCHIZO_PCIAFSR_MEM) ?
703 ((afsr & SCHIZO_PCIAFSR_IO) ?
705 printk("%s: PCI AFAR [%016lx]\n",
707 printk("%s: PCI Secondary errors [",
710 if (afsr & SCHIZO_PCIAFSR_SMA) {
712 printk("(Master Abort)");
714 if (afsr & SCHIZO_PCIAFSR_STA) {
716 printk("(Target Abort)");
718 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
720 printk("(Excessive Retries)");
722 if (afsr & SCHIZO_PCIAFSR_SPERR) {
724 printk("(Parity Error)");
726 if (afsr & SCHIZO_PCIAFSR_STTO) {
730 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
732 printk("(Bus Unusable)");
738 /* For the error types shown, scan PBM's PCI bus for devices
739 * which have logged that error type.
742 /* If we see a Target Abort, this could be the result of an
743 * IOMMU translation error of some sort. It is extremely
744 * useful to log this information as usually it indicates
745 * a bug in the IOMMU support code or a PCI device driver.
747 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
748 schizo_check_iommu_error(p, PCI_ERR);
749 pci_scan_for_target_abort(pbm, pbm->pci_bus);
751 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
752 pci_scan_for_master_abort(pbm, pbm->pci_bus);
754 /* For excessive retries, PSYCHO/PBM will abort the device
755 * and there is no way to specifically check for excessive
756 * retries in the config space status registers. So what
757 * we hope is that we'll catch it via the master/target
761 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
762 pci_scan_for_parity_error(pbm, pbm->pci_bus);
767 #define SCHIZO_SAFARI_ERRLOG 0x10018UL
769 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
771 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
772 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
773 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
774 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
775 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
776 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
777 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
778 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
779 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
780 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
781 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
782 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
783 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
784 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
785 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
786 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
787 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
788 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
789 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
790 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
791 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
792 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
793 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
794 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
795 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
796 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
797 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
798 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
799 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
800 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
801 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
803 /* We only expect UNMAP errors here. The rest of the Safari errors
804 * are marked fatal and thus cause a system reset.
806 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
808 struct pci_pbm_info *pbm = dev_id;
809 struct pci_controller_info *p = pbm->parent;
812 errlog = schizo_read(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
813 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG,
814 errlog & ~(SAFARI_ERRLOG_ERROUT));
816 if (!(errlog & BUS_ERROR_UNMAP)) {
817 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
823 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
825 schizo_check_iommu_error(p, SAFARI_ERR);
830 /* Nearly identical to PSYCHO equivalents... */
831 #define SCHIZO_ECC_CTRL 0x10020UL
832 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
833 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
834 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
836 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
837 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
838 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
839 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
841 static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
845 if (pbm->ino_bitmap & (1UL << ino))
851 /* How the Tomatillo IRQs are routed around is pure guesswork here.
853 * All the Tomatillo devices I see in prtconf dumps seem to have only
854 * a single PCI bus unit attached to it. It would seem they are separate
855 * devices because their PortID (ie. JBUS ID) values are all different
856 * and thus the registers are mapped to totally different locations.
858 * However, two Tomatillo's look "similar" in that the only difference
859 * in their PortID is the lowest bit.
861 * So if we were to ignore this lower bit, it certainly looks like two
862 * PCI bus units of the same Tomatillo. I still have not really
863 * figured this out...
865 static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
867 struct of_device *op = of_find_device_by_node(pbm->prom_node);
868 u64 tmp, err_mask, err_no_mask;
871 /* Tomatillo IRQ property layout is:
879 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
880 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
881 "TOMATILLO_UE", pbm);
883 printk(KERN_WARNING "%s: Could not register UE, "
884 "err=%d\n", pbm->name, err);
886 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
887 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
888 "TOMATILLO_CE", pbm);
890 printk(KERN_WARNING "%s: Could not register CE, "
891 "err=%d\n", pbm->name, err);
894 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
895 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
896 "TOMATILLO_PCIERR", pbm);
897 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
898 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
899 "TOMATILLO_PCIERR", pbm);
902 printk(KERN_WARNING "%s: Could not register PCIERR, "
903 "err=%d\n", pbm->name, err);
905 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
906 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
907 "TOMATILLO_SERR", pbm);
909 printk(KERN_WARNING "%s: Could not register SERR, "
910 "err=%d\n", pbm->name, err);
913 /* Enable UE and CE interrupts for controller. */
914 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
919 /* Enable PCI Error interrupts and clear error
922 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
923 SCHIZO_PCICTRL_TTO_ERR |
924 SCHIZO_PCICTRL_RTRY_ERR |
925 SCHIZO_PCICTRL_SERR |
928 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
930 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
933 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
935 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
936 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
937 SCHIZO_PCIAFSR_PTTO |
938 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
939 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
940 SCHIZO_PCIAFSR_STTO);
942 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, err_mask);
944 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
945 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
946 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
947 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
948 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
949 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
950 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
951 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
952 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
954 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
955 (SCHIZO_SAFERRCTRL_EN | err_mask));
957 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL,
958 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
961 static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
963 struct of_device *op = of_find_device_by_node(pbm->prom_node);
964 u64 tmp, err_mask, err_no_mask;
967 /* Schizo IRQ property layout is:
975 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
976 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
979 printk(KERN_WARNING "%s: Could not register UE, "
980 "err=%d\n", pbm->name, err);
982 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
983 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
986 printk(KERN_WARNING "%s: Could not register CE, "
987 "err=%d\n", pbm->name, err);
990 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
991 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
992 "SCHIZO_PCIERR", pbm);
993 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
994 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
995 "SCHIZO_PCIERR", pbm);
998 printk(KERN_WARNING "%s: Could not register PCIERR, "
999 "err=%d\n", pbm->name, err);
1001 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
1002 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1003 "SCHIZO_SERR", pbm);
1005 printk(KERN_WARNING "%s: Could not register SERR, "
1006 "err=%d\n", pbm->name, err);
1009 /* Enable UE and CE interrupts for controller. */
1010 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1011 (SCHIZO_ECCCTRL_EE |
1013 SCHIZO_ECCCTRL_CE));
1015 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1016 SCHIZO_PCICTRL_ESLCK |
1017 SCHIZO_PCICTRL_TTO_ERR |
1018 SCHIZO_PCICTRL_RTRY_ERR |
1019 SCHIZO_PCICTRL_SBH_ERR |
1020 SCHIZO_PCICTRL_SERR |
1021 SCHIZO_PCICTRL_EEN);
1023 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1024 SCHIZO_PCICTRL_SBH_INT);
1026 /* Enable PCI Error interrupts and clear error
1027 * bits for each PBM.
1029 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1031 tmp &= ~err_no_mask;
1032 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1034 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR,
1035 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1036 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1037 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1038 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1039 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1040 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1042 /* Make all Safari error conditions fatal except unmapped
1043 * errors which we make generate interrupts.
1045 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1046 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1048 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1049 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1051 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1052 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1053 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1056 /* XXX Something wrong with some Excalibur systems
1057 * XXX Sun is shipping. The behavior on a 2-cpu
1058 * XXX machine is that both CPU1 parity error bits
1059 * XXX are set and are immediately set again when
1060 * XXX their error status bits are cleared. Just
1061 * XXX ignore them for now. -DaveM
1063 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1064 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1067 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1068 (SCHIZO_SAFERRCTRL_EN | err_mask));
1071 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1075 /* Set cache-line size to 64 bytes, this is actually
1076 * a nop but I do it for completeness.
1078 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1079 0, PCI_CACHE_LINE_SIZE);
1080 pci_config_write8(addr, 64 / sizeof(u32));
1082 /* Set PBM latency timer to 64 PCI clocks. */
1083 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1084 0, PCI_LATENCY_TIMER);
1085 pci_config_write8(addr, 64);
1088 static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm,
1089 struct device *parent)
1091 pbm_config_busmastering(pbm);
1092 pbm->is_66mhz_capable =
1093 (of_find_property(pbm->prom_node, "66mhz-capable", NULL)
1096 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
1098 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1099 tomatillo_register_error_handlers(pbm);
1101 schizo_register_error_handlers(pbm);
1104 #define SCHIZO_STRBUF_CONTROL (0x02800UL)
1105 #define SCHIZO_STRBUF_FLUSH (0x02808UL)
1106 #define SCHIZO_STRBUF_FSYNC (0x02810UL)
1107 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1108 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1110 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1112 unsigned long base = pbm->pbm_regs;
1115 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1116 /* TOMATILLO lacks streaming cache. */
1120 /* SCHIZO has context flushing. */
1121 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1122 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1123 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1124 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1125 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1127 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1128 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1131 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1132 __pa(pbm->stc.strbuf_flushflag);
1134 /* Turn off LRU locking and diag mode, enable the
1135 * streaming buffer and leave the rerun-disable
1136 * setting however OBP set it.
1138 control = schizo_read(pbm->stc.strbuf_control);
1139 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1140 SCHIZO_STRBUF_CTRL_LENAB |
1141 SCHIZO_STRBUF_CTRL_DENAB);
1142 control |= SCHIZO_STRBUF_CTRL_ENAB;
1143 schizo_write(pbm->stc.strbuf_control, control);
1145 pbm->stc.strbuf_enabled = 1;
1148 #define SCHIZO_IOMMU_CONTROL (0x00200UL)
1149 #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1150 #define SCHIZO_IOMMU_FLUSH (0x00210UL)
1151 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1153 static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1155 static const u32 vdma_default[] = { 0xc0000000, 0x40000000 };
1156 unsigned long i, tagbase, database;
1157 struct iommu *iommu = pbm->iommu;
1163 vdma = of_get_property(pbm->prom_node, "virtual-dma", NULL);
1165 vdma = vdma_default;
1170 dma_mask |= 0x1fffffff;
1175 dma_mask |= 0x3fffffff;
1180 dma_mask |= 0x7fffffff;
1185 printk(KERN_ERR PFX "Strange virtual-dma size.\n");
1189 /* Register addresses, SCHIZO has iommu ctx flushing. */
1190 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1191 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1192 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1193 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
1194 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1196 /* We use the main control/status register of SCHIZO as the write
1197 * completion register.
1199 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1202 * Invalidate TLB Entries.
1204 control = schizo_read(iommu->iommu_control);
1205 control |= SCHIZO_IOMMU_CTRL_DENAB;
1206 schizo_write(iommu->iommu_control, control);
1208 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1210 for (i = 0; i < 16; i++) {
1211 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1212 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1215 /* Leave diag mode enabled for full-flushing done
1218 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
1221 printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
1225 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
1227 control = schizo_read(iommu->iommu_control);
1228 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1231 control |= SCHIZO_IOMMU_TSBSZ_64K;
1234 control |= SCHIZO_IOMMU_TSBSZ_128K;
1238 control |= SCHIZO_IOMMU_CTRL_ENAB;
1239 schizo_write(iommu->iommu_control, control);
1244 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1245 #define SCHIZO_IRQ_RETRY_INF 0xffUL
1247 #define SCHIZO_PCI_DIAG (0x2020UL)
1248 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1249 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1250 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1251 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1252 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1253 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1254 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1255 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1256 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1258 #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1259 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1260 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1261 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1262 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1263 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1264 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1265 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1266 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1267 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1268 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1269 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1270 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1271 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1272 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1273 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1275 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1276 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1278 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1282 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5);
1284 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1286 /* Enable arbiter for all PCI slots. */
1289 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1290 pbm->chip_version >= 0x2)
1291 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1293 if (!of_find_property(pbm->prom_node, "no-bus-parking", NULL))
1294 tmp |= SCHIZO_PCICTRL_PARK;
1296 tmp &= ~SCHIZO_PCICTRL_PARK;
1298 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1299 pbm->chip_version <= 0x1)
1300 tmp |= SCHIZO_PCICTRL_DTO_INT;
1302 tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1304 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1305 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1306 SCHIZO_PCICTRL_RDO_PREF |
1307 SCHIZO_PCICTRL_RDL_PREF);
1309 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1311 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1312 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1313 SCHIZO_PCIDIAG_D_RETRY |
1314 SCHIZO_PCIDIAG_D_INTSYNC);
1315 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1317 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1318 /* Clear prefetch lengths to workaround a bug in
1321 tmp = (TOMATILLO_IOC_PART_WPENAB |
1322 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1323 TOMATILLO_IOC_RDMULT_CPENAB |
1324 TOMATILLO_IOC_RDONE_CPENAB |
1325 TOMATILLO_IOC_RDLINE_CPENAB);
1327 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1332 static int __devinit schizo_pbm_init(struct pci_controller_info *p,
1333 struct of_device *op, u32 portid,
1336 const struct linux_prom64_registers *regs;
1337 struct device_node *dp = op->node;
1338 struct pci_pbm_info *pbm;
1339 const char *chipset_name;
1342 switch (chip_type) {
1343 case PBM_CHIP_TYPE_TOMATILLO:
1344 chipset_name = "TOMATILLO";
1347 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1348 chipset_name = "SCHIZO+";
1351 case PBM_CHIP_TYPE_SCHIZO:
1353 chipset_name = "SCHIZO";
1357 /* For SCHIZO, three OBP regs:
1358 * 1) PBM controller regs
1359 * 2) Schizo front-end controller regs (same for both PBMs)
1360 * 3) PBM PCI config space
1362 * For TOMATILLO, four OBP regs:
1363 * 1) PBM controller regs
1364 * 2) Tomatillo front-end controller regs
1365 * 3) PBM PCI config space
1368 regs = of_get_property(dp, "reg", NULL);
1370 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000);
1376 pbm->next = pci_pbm_root;
1379 pbm->numa_node = -1;
1381 pbm->pci_ops = &sun4u_pci_ops;
1382 pbm->config_space_reg_bits = 8;
1384 pbm->index = pci_num_pbms++;
1386 pbm->portid = portid;
1388 pbm->prom_node = dp;
1390 pbm->chip_type = chip_type;
1391 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1392 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
1394 pbm->pbm_regs = regs[0].phys_addr;
1395 pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1397 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1398 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
1400 pbm->name = dp->full_name;
1402 printk("%s: %s PCI Bus Module ver[%x:%x]\n",
1403 pbm->name, chipset_name,
1404 pbm->chip_version, pbm->chip_revision);
1406 schizo_pbm_hw_init(pbm);
1408 pci_determine_mem_io_space(pbm);
1410 pci_get_pbm_props(pbm);
1412 err = schizo_pbm_iommu_init(pbm);
1416 schizo_pbm_strbuf_init(pbm);
1418 schizo_scan_bus(pbm, &op->dev);
1423 static inline int portid_compare(u32 x, u32 y, int chip_type)
1425 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1433 static int __devinit __schizo_init(struct of_device *op, unsigned long chip_type)
1435 struct device_node *dp = op->node;
1436 struct pci_controller_info *p;
1437 struct pci_pbm_info *pbm;
1438 struct iommu *iommu;
1442 portid = of_getintprop_default(dp, "portid", 0xff);
1445 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1446 if (portid_compare(pbm->portid, portid, chip_type)) {
1447 if (schizo_pbm_init(pbm->parent, op,
1454 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1456 printk(KERN_ERR PFX "Cannot allocate controller info.\n");
1460 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1462 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
1463 goto out_free_controller;
1466 p->pbm_A.iommu = iommu;
1468 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1470 printk(KERN_ERR PFX "Cannot allocate PBM B iommu.\n");
1471 goto out_free_iommu_A;
1474 p->pbm_B.iommu = iommu;
1476 if (schizo_pbm_init(p, op, portid, chip_type))
1477 goto out_free_iommu_B;
1482 kfree(p->pbm_B.iommu);
1485 kfree(p->pbm_A.iommu);
1487 out_free_controller:
1494 static int __devinit schizo_probe(struct of_device *op,
1495 const struct of_device_id *match)
1497 return __schizo_init(op, (unsigned long) match->data);
1500 /* The ordering of this table is very important. Some Tomatillo
1501 * nodes announce that they are compatible with both pci108e,a801
1502 * and pci108e,8001. So list the chips in reverse chronological
1505 static struct of_device_id __initdata schizo_match[] = {
1508 .compatible = "pci108e,a801",
1509 .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
1513 .compatible = "pci108e,8002",
1514 .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
1518 .compatible = "pci108e,8001",
1519 .data = (void *) PBM_CHIP_TYPE_SCHIZO,
1524 static struct of_platform_driver schizo_driver = {
1525 .name = DRIVER_NAME,
1526 .match_table = schizo_match,
1527 .probe = schizo_probe,
1530 static int __init schizo_init(void)
1532 return of_register_driver(&schizo_driver, &of_bus_type);
1535 subsys_initcall(schizo_init);