arch/sparc64/kernel/smp.c

   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/smp_lock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/cache.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/profile.h>
  24 #include <linux/bootmem.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/ptrace.h>
  28 #include <asm/atomic.h>
  29 #include <asm/tlbflush.h>
  30 #include <asm/mmu_context.h>
  31 #include <asm/cpudata.h>
  32
  33 #include <asm/irq.h>
  34 #include <asm/page.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/oplib.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/timer.h>
  39 #include <asm/starfire.h>
  40 #include <asm/tlb.h>
  41 #include <asm/sections.h>
  42
  43 extern void calibrate_delay(void);
  44
  45 /* Please don't make this stuff initdata!!!  --DaveM */
  46 static unsigned char boot_cpu_id;
  47
  48 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
  49 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
  50 static cpumask_t smp_commenced_mask;
  51 static cpumask_t cpu_callout_map;
  52
  53 void smp_info(struct seq_file *m)
  54 {
  55         int i;
  56
  57         seq_printf(m, "State:\n");
  58         for (i = 0; i < NR_CPUS; i++) {
  59                 if (cpu_online(i))
  60                         seq_printf(m,
  61                                    "CPU%d:\t\tonline\n", i);
  62         }
  63 }
  64
  65 void smp_bogo(struct seq_file *m)
  66 {
  67         int i;
  68
  69         for (i = 0; i < NR_CPUS; i++)
  70                 if (cpu_online(i))
  71                         seq_printf(m,
  72                                    "Cpu%dBogo\t: %lu.%02lu\n"
  73                                    "Cpu%dClkTck\t: %016lx\n",
  74                                    i, cpu_data(i).udelay_val / (500000/HZ),
  75                                    (cpu_data(i).udelay_val / (5000/HZ)) % 100,
  76                                    i, cpu_data(i).clock_tick);
  77 }
  78
  79 void __init smp_store_cpu_info(int id)
  80 {
  81         int cpu_node;
  82
  83         /* multiplier and counter set by
  84            smp_setup_percpu_timer()  */
  85         cpu_data(id).udelay_val                 = loops_per_jiffy;
  86
  87         cpu_find_by_mid(id, &cpu_node);
  88         cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
  89                                                      "clock-frequency", 0);
  90
  91         cpu_data(id).idle_volume                = 1;
  92
  93         cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
  94                                                       16 * 1024);
  95         cpu_data(id).dcache_line_size =
  96                 prom_getintdefault(cpu_node, "dcache-line-size", 32);
  97         cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
  98                                                       16 * 1024);
  99         cpu_data(id).icache_line_size =
 100                 prom_getintdefault(cpu_node, "icache-line-size", 32);
 101         cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
 102                                                       4 * 1024 * 1024);
 103         cpu_data(id).ecache_line_size =
 104                 prom_getintdefault(cpu_node, "ecache-line-size", 64);
 105         printk("CPU[%d]: Caches "
 106                "D[sz(%d):line_sz(%d)] "
 107                "I[sz(%d):line_sz(%d)] "
 108                "E[sz(%d):line_sz(%d)]\n",
 109                id,
 110                cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
 111                cpu_data(id).icache_size, cpu_data(id).icache_line_size,
 112                cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
 113 }
 114
 115 static void smp_setup_percpu_timer(void);
 116
 117 static volatile unsigned long callin_flag = 0;
 118
 119 void __init smp_callin(void)
 120 {
 121         int cpuid = hard_smp_processor_id();
 122
 123         __local_per_cpu_offset = __per_cpu_offset(cpuid);
 124
 125         if (tlb_type == hypervisor)
 126                 sun4v_register_fault_status();
 127
 128         __flush_tlb_all();
 129
 130         smp_setup_percpu_timer();
 131
 132         if (cheetah_pcache_forced_on)
 133                 cheetah_enable_pcache();
 134
 135         local_irq_enable();
 136
 137         calibrate_delay();
 138         smp_store_cpu_info(cpuid);
 139         callin_flag = 1;
 140         __asm__ __volatile__("membar #Sync\n\t"
 141                              "flush  %%g6" : : : "memory");
 142
 143         /* Clear this or we will die instantly when we
 144          * schedule back to this idler...
 145          */
 146         current_thread_info()->new_child = 0;
 147
 148         /* Attach to the address space of init_task. */
 149         atomic_inc(&init_mm.mm_count);
 150         current->active_mm = &init_mm;
 151
 152         while (!cpu_isset(cpuid, smp_commenced_mask))
 153                 rmb();
 154
 155         cpu_set(cpuid, cpu_online_map);
 156
 157         /* idle thread is expected to have preempt disabled */
 158         preempt_disable();
 159 }
 160
 161 void cpu_panic(void)
 162 {
 163         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 164         panic("SMP bolixed\n");
 165 }
 166
 167 static unsigned long current_tick_offset __read_mostly;
 168
 169 /* This tick register synchronization scheme is taken entirely from
 170  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 171  *
 172  * The only change I've made is to rework it so that the master
 173  * initiates the synchonization instead of the slave. -DaveM
 174  */
 175
 176 #define MASTER  0
 177 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 178
 179 #define NUM_ROUNDS      64      /* magic value */
 180 #define NUM_ITERS       5       /* likewise */
 181
 182 static DEFINE_SPINLOCK(itc_sync_lock);
 183 static unsigned long go[SLAVE + 1];
 184
 185 #define DEBUG_TICK_SYNC 0
 186
 187 static inline long get_delta (long *rt, long *master)
 188 {
 189         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 190         unsigned long tcenter, t0, t1, tm;
 191         unsigned long i;
 192
 193         for (i = 0; i < NUM_ITERS; i++) {
 194                 t0 = tick_ops->get_tick();
 195                 go[MASTER] = 1;
 196                 membar_storeload();
 197                 while (!(tm = go[SLAVE]))
 198                         rmb();
 199                 go[SLAVE] = 0;
 200                 wmb();
 201                 t1 = tick_ops->get_tick();
 202
 203                 if (t1 - t0 < best_t1 - best_t0)
 204                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 205         }
 206
 207         *rt = best_t1 - best_t0;
 208         *master = best_tm - best_t0;
 209
 210         /* average best_t0 and best_t1 without overflow: */
 211         tcenter = (best_t0/2 + best_t1/2);
 212         if (best_t0 % 2 + best_t1 % 2 == 2)
 213                 tcenter++;
 214         return tcenter - best_tm;
 215 }
 216
 217 void smp_synchronize_tick_client(void)
 218 {
 219         long i, delta, adj, adjust_latency = 0, done = 0;
 220         unsigned long flags, rt, master_time_stamp, bound;
 221 #if DEBUG_TICK_SYNC
 222         struct {
 223                 long rt;        /* roundtrip time */
 224                 long master;    /* master's timestamp */
 225                 long diff;      /* difference between midpoint and master's timestamp */
 226                 long lat;       /* estimate of itc adjustment latency */
 227         } t[NUM_ROUNDS];
 228 #endif
 229
 230         go[MASTER] = 1;
 231
 232         while (go[MASTER])
 233                 rmb();
 234
 235         local_irq_save(flags);
 236         {
 237                 for (i = 0; i < NUM_ROUNDS; i++) {
 238                         delta = get_delta(&rt, &master_time_stamp);
 239                         if (delta == 0) {
 240                                 done = 1;       /* let's lock on to this... */
 241                                 bound = rt;
 242                         }
 243
 244                         if (!done) {
 245                                 if (i > 0) {
 246                                         adjust_latency += -delta;
 247                                         adj = -delta + adjust_latency/4;
 248                                 } else
 249                                         adj = -delta;
 250
 251                                 tick_ops->add_tick(adj, current_tick_offset);
 252                         }
 253 #if DEBUG_TICK_SYNC
 254                         t[i].rt = rt;
 255                         t[i].master = master_time_stamp;
 256                         t[i].diff = delta;
 257                         t[i].lat = adjust_latency/4;
 258 #endif
 259                 }
 260         }
 261         local_irq_restore(flags);
 262
 263 #if DEBUG_TICK_SYNC
 264         for (i = 0; i < NUM_ROUNDS; i++)
 265                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 266                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 267 #endif
 268
 269         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
 270                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
 271 }
 272
 273 static void smp_start_sync_tick_client(int cpu);
 274
 275 static void smp_synchronize_one_tick(int cpu)
 276 {
 277         unsigned long flags, i;
 278
 279         go[MASTER] = 0;
 280
 281         smp_start_sync_tick_client(cpu);
 282
 283         /* wait for client to be ready */
 284         while (!go[MASTER])
 285                 rmb();
 286
 287         /* now let the client proceed into his loop */
 288         go[MASTER] = 0;
 289         membar_storeload();
 290
 291         spin_lock_irqsave(&itc_sync_lock, flags);
 292         {
 293                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 294                         while (!go[MASTER])
 295                                 rmb();
 296                         go[MASTER] = 0;
 297                         wmb();
 298                         go[SLAVE] = tick_ops->get_tick();
 299                         membar_storeload();
 300                 }
 301         }
 302         spin_unlock_irqrestore(&itc_sync_lock, flags);
 303 }
 304
 305 extern unsigned long sparc64_cpu_startup;
 306
 307 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 308  * 32-bits (I think) so to be safe we have it read the pointer
 309  * contained here so we work on >4GB machines. -DaveM
 310  */
 311 static struct thread_info *cpu_new_thread = NULL;
 312
 313 static int __devinit smp_boot_one_cpu(unsigned int cpu)
 314 {
 315         unsigned long entry =
 316                 (unsigned long)(&sparc64_cpu_startup);
 317         unsigned long cookie =
 318                 (unsigned long)(&cpu_new_thread);
 319         struct task_struct *p;
 320         int timeout, ret, cpu_node;
 321
 322         p = fork_idle(cpu);
 323         callin_flag = 0;
 324         cpu_new_thread = task_thread_info(p);
 325         cpu_set(cpu, cpu_callout_map);
 326
 327         cpu_find_by_mid(cpu, &cpu_node);
 328         prom_startcpu(cpu_node, entry, cookie);
 329
 330         for (timeout = 0; timeout < 5000000; timeout++) {
 331                 if (callin_flag)
 332                         break;
 333                 udelay(100);
 334         }
 335         if (callin_flag) {
 336                 ret = 0;
 337         } else {
 338                 printk("Processor %d is stuck.\n", cpu);
 339                 cpu_clear(cpu, cpu_callout_map);
 340                 ret = -ENODEV;
 341         }
 342         cpu_new_thread = NULL;
 343
 344         return ret;
 345 }
 346
 347 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 348 {
 349         u64 result, target;
 350         int stuck, tmp;
 351
 352         if (this_is_starfire) {
 353                 /* map to real upaid */
 354                 cpu = (((cpu & 0x3c) << 1) |
 355                         ((cpu & 0x40) >> 4) |
 356                         (cpu & 0x3));
 357         }
 358
 359         target = (cpu << 14) | 0x70;
 360 again:
 361         /* Ok, this is the real Spitfire Errata #54.
 362          * One must read back from a UDB internal register
 363          * after writes to the UDB interrupt dispatch, but
 364          * before the membar Sync for that write.
 365          * So we use the high UDB control register (ASI 0x7f,
 366          * ADDR 0x20) for the dummy read. -DaveM
 367          */
 368         tmp = 0x40;
 369         __asm__ __volatile__(
 370         "wrpr   %1, %2, %%pstate\n\t"
 371         "stxa   %4, [%0] %3\n\t"
 372         "stxa   %5, [%0+%8] %3\n\t"
 373         "add    %0, %8, %0\n\t"
 374         "stxa   %6, [%0+%8] %3\n\t"
 375         "membar #Sync\n\t"
 376         "stxa   %%g0, [%7] %3\n\t"
 377         "membar #Sync\n\t"
 378         "mov    0x20, %%g1\n\t"
 379         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 380         "membar #Sync"
 381         : "=r" (tmp)
 382         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 383           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 384           "r" (0x10), "0" (tmp)
 385         : "g1");
 386
 387         /* NOTE: PSTATE_IE is still clear. */
 388         stuck = 100000;
 389         do {
 390                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 391                         : "=r" (result)
 392                         : "i" (ASI_INTR_DISPATCH_STAT));
 393                 if (result == 0) {
 394                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 395                                              : : "r" (pstate));
 396                         return;
 397                 }
 398                 stuck -= 1;
 399                 if (stuck == 0)
 400                         break;
 401         } while (result & 0x1);
 402         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 403                              : : "r" (pstate));
 404         if (stuck == 0) {
 405                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 406                        smp_processor_id(), result);
 407         } else {
 408                 udelay(2);
 409                 goto again;
 410         }
 411 }
 412
 413 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 414 {
 415         u64 pstate;
 416         int i;
 417
 418         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 419         for_each_cpu_mask(i, mask)
 420                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
 421 }
 422
 423 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 424  * packet, but we have no use for that.  However we do take advantage of
 425  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 426  */
 427 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 428 {
 429         u64 pstate, ver;
 430         int nack_busy_id, is_jbus;
 431
 432         if (cpus_empty(mask))
 433                 return;
 434
 435         /* Unfortunately, someone at Sun had the brilliant idea to make the
 436          * busy/nack fields hard-coded by ITID number for this Ultra-III
 437          * derivative processor.
 438          */
 439         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 440         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 441                    (ver >> 32) == __SERRANO_ID);
 442
 443         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 444
 445 retry:
 446         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 447                              : : "r" (pstate), "i" (PSTATE_IE));
 448
 449         /* Setup the dispatch data registers. */
 450         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 451                              "stxa      %1, [%4] %6\n\t"
 452                              "stxa      %2, [%5] %6\n\t"
 453                              "membar    #Sync\n\t"
 454                              : /* no outputs */
 455                              : "r" (data0), "r" (data1), "r" (data2),
 456                                "r" (0x40), "r" (0x50), "r" (0x60),
 457                                "i" (ASI_INTR_W));
 458
 459         nack_busy_id = 0;
 460         {
 461                 int i;
 462
 463                 for_each_cpu_mask(i, mask) {
 464                         u64 target = (i << 14) | 0x70;
 465
 466                         if (!is_jbus)
 467                                 target |= (nack_busy_id << 24);
 468                         __asm__ __volatile__(
 469                                 "stxa   %%g0, [%0] %1\n\t"
 470                                 "membar #Sync\n\t"
 471                                 : /* no outputs */
 472                                 : "r" (target), "i" (ASI_INTR_W));
 473                         nack_busy_id++;
 474                 }
 475         }
 476
 477         /* Now, poll for completion. */
 478         {
 479                 u64 dispatch_stat;
 480                 long stuck;
 481
 482                 stuck = 100000 * nack_busy_id;
 483                 do {
 484                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 485                                              : "=r" (dispatch_stat)
 486                                              : "i" (ASI_INTR_DISPATCH_STAT));
 487                         if (dispatch_stat == 0UL) {
 488                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 489                                                      : : "r" (pstate));
 490                                 return;
 491                         }
 492                         if (!--stuck)
 493                                 break;
 494                 } while (dispatch_stat & 0x5555555555555555UL);
 495
 496                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 497                                      : : "r" (pstate));
 498
 499                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
 500                         /* Busy bits will not clear, continue instead
 501                          * of freezing up on this cpu.
 502                          */
 503                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 504                                smp_processor_id(), dispatch_stat);
 505                 } else {
 506                         int i, this_busy_nack = 0;
 507
 508                         /* Delay some random time with interrupts enabled
 509                          * to prevent deadlock.
 510                          */
 511                         udelay(2 * nack_busy_id);
 512
 513                         /* Clear out the mask bits for cpus which did not
 514                          * NACK us.
 515                          */
 516                         for_each_cpu_mask(i, mask) {
 517                                 u64 check_mask;
 518
 519                                 if (is_jbus)
 520                                         check_mask = (0x2UL << (2*i));
 521                                 else
 522                                         check_mask = (0x2UL <<
 523                                                       this_busy_nack);
 524                                 if ((dispatch_stat & check_mask) == 0)
 525                                         cpu_clear(i, mask);
 526                                 this_busy_nack += 2;
 527                         }
 528
 529                         goto retry;
 530                 }
 531         }
 532 }
 533
 534 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 535 {
 536         /* XXX implement me */
 537 }
 538
 539 /* Send cross call to all processors mentioned in MASK
 540  * except self.
 541  */
 542 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
 543 {
 544         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 545         int this_cpu = get_cpu();
 546
 547         cpus_and(mask, mask, cpu_online_map);
 548         cpu_clear(this_cpu, mask);
 549
 550         if (tlb_type == spitfire)
 551                 spitfire_xcall_deliver(data0, data1, data2, mask);
 552         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 553                 cheetah_xcall_deliver(data0, data1, data2, mask);
 554         else
 555                 hypervisor_xcall_deliver(data0, data1, data2, mask);
 556         /* NOTE: Caller runs local copy on master. */
 557
 558         put_cpu();
 559 }
 560
 561 extern unsigned long xcall_sync_tick;
 562
 563 static void smp_start_sync_tick_client(int cpu)
 564 {
 565         cpumask_t mask = cpumask_of_cpu(cpu);
 566
 567         smp_cross_call_masked(&xcall_sync_tick,
 568                               0, 0, 0, mask);
 569 }
 570
 571 /* Send cross call to all processors except self. */
 572 #define smp_cross_call(func, ctx, data1, data2) \
 573         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
 574
 575 struct call_data_struct {
 576         void (*func) (void *info);
 577         void *info;
 578         atomic_t finished;
 579         int wait;
 580 };
 581
 582 static DEFINE_SPINLOCK(call_lock);
 583 static struct call_data_struct *call_data;
 584
 585 extern unsigned long xcall_call_function;
 586
 587 /*
 588  * You must not call this function with disabled interrupts or from a
 589  * hardware interrupt handler or from a bottom half handler.
 590  */
 591 static int smp_call_function_mask(void (*func)(void *info), void *info,
 592                                   int nonatomic, int wait, cpumask_t mask)
 593 {
 594         struct call_data_struct data;
 595         int cpus = cpus_weight(mask) - 1;
 596         long timeout;
 597
 598         if (!cpus)
 599                 return 0;
 600
 601         /* Can deadlock when called with interrupts disabled */
 602         WARN_ON(irqs_disabled());
 603
 604         data.func = func;
 605         data.info = info;
 606         atomic_set(&data.finished, 0);
 607         data.wait = wait;
 608
 609         spin_lock(&call_lock);
 610
 611         call_data = &data;
 612
 613         smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
 614
 615         /*
 616          * Wait for other cpus to complete function or at
 617          * least snap the call data.
 618          */
 619         timeout = 1000000;
 620         while (atomic_read(&data.finished) != cpus) {
 621                 if (--timeout <= 0)
 622                         goto out_timeout;
 623                 barrier();
 624                 udelay(1);
 625         }
 626
 627         spin_unlock(&call_lock);
 628
 629         return 0;
 630
 631 out_timeout:
 632         spin_unlock(&call_lock);
 633         printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
 634                (long) num_online_cpus() - 1L,
 635                (long) atomic_read(&data.finished));
 636         return 0;
 637 }
 638
 639 int smp_call_function(void (*func)(void *info), void *info,
 640                       int nonatomic, int wait)
 641 {
 642         return smp_call_function_mask(func, info, nonatomic, wait,
 643                                       cpu_online_map);
 644 }
 645
 646 void smp_call_function_client(int irq, struct pt_regs *regs)
 647 {
 648         void (*func) (void *info) = call_data->func;
 649         void *info = call_data->info;
 650
 651         clear_softint(1 << irq);
 652         if (call_data->wait) {
 653                 /* let initiator proceed only after completion */
 654                 func(info);
 655                 atomic_inc(&call_data->finished);
 656         } else {
 657                 /* let initiator proceed after getting data */
 658                 atomic_inc(&call_data->finished);
 659                 func(info);
 660         }
 661 }
 662
 663 static void tsb_sync(void *info)
 664 {
 665         struct mm_struct *mm = info;
 666
 667         if (current->active_mm == mm)
 668                 tsb_context_switch(mm);
 669 }
 670
 671 void smp_tsb_sync(struct mm_struct *mm)
 672 {
 673         smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
 674 }
 675
 676 extern unsigned long xcall_flush_tlb_mm;
 677 extern unsigned long xcall_flush_tlb_pending;
 678 extern unsigned long xcall_flush_tlb_kernel_range;
 679 extern unsigned long xcall_report_regs;
 680 extern unsigned long xcall_receive_signal;
 681
 682 #ifdef DCACHE_ALIASING_POSSIBLE
 683 extern unsigned long xcall_flush_dcache_page_cheetah;
 684 #endif
 685 extern unsigned long xcall_flush_dcache_page_spitfire;
 686
 687 #ifdef CONFIG_DEBUG_DCFLUSH
 688 extern atomic_t dcpage_flushes;
 689 extern atomic_t dcpage_flushes_xcall;
 690 #endif
 691
 692 static __inline__ void __local_flush_dcache_page(struct page *page)
 693 {
 694 #ifdef DCACHE_ALIASING_POSSIBLE
 695         __flush_dcache_page(page_address(page),
 696                             ((tlb_type == spitfire) &&
 697                              page_mapping(page) != NULL));
 698 #else
 699         if (page_mapping(page) != NULL &&
 700             tlb_type == spitfire)
 701                 __flush_icache_page(__pa(page_address(page)));
 702 #endif
 703 }
 704
 705 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 706 {
 707         cpumask_t mask = cpumask_of_cpu(cpu);
 708         int this_cpu;
 709
 710         if (tlb_type == hypervisor)
 711                 return;
 712
 713 #ifdef CONFIG_DEBUG_DCFLUSH
 714         atomic_inc(&dcpage_flushes);
 715 #endif
 716
 717         this_cpu = get_cpu();
 718
 719         if (cpu == this_cpu) {
 720                 __local_flush_dcache_page(page);
 721         } else if (cpu_online(cpu)) {
 722                 void *pg_addr = page_address(page);
 723                 u64 data0;
 724
 725                 if (tlb_type == spitfire) {
 726                         data0 =
 727                                 ((u64)&xcall_flush_dcache_page_spitfire);
 728                         if (page_mapping(page) != NULL)
 729                                 data0 |= ((u64)1 << 32);
 730                         spitfire_xcall_deliver(data0,
 731                                                __pa(pg_addr),
 732                                                (u64) pg_addr,
 733                                                mask);
 734                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 735 #ifdef DCACHE_ALIASING_POSSIBLE
 736                         data0 =
 737                                 ((u64)&xcall_flush_dcache_page_cheetah);
 738                         cheetah_xcall_deliver(data0,
 739                                               __pa(pg_addr),
 740                                               0, mask);
 741 #endif
 742                 }
 743 #ifdef CONFIG_DEBUG_DCFLUSH
 744                 atomic_inc(&dcpage_flushes_xcall);
 745 #endif
 746         }
 747
 748         put_cpu();
 749 }
 750
 751 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 752 {
 753         void *pg_addr = page_address(page);
 754         cpumask_t mask = cpu_online_map;
 755         u64 data0;
 756         int this_cpu;
 757
 758         if (tlb_type == hypervisor)
 759                 return;
 760
 761         this_cpu = get_cpu();
 762
 763         cpu_clear(this_cpu, mask);
 764
 765 #ifdef CONFIG_DEBUG_DCFLUSH
 766         atomic_inc(&dcpage_flushes);
 767 #endif
 768         if (cpus_empty(mask))
 769                 goto flush_self;
 770         if (tlb_type == spitfire) {
 771                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 772                 if (page_mapping(page) != NULL)
 773                         data0 |= ((u64)1 << 32);
 774                 spitfire_xcall_deliver(data0,
 775                                        __pa(pg_addr),
 776                                        (u64) pg_addr,
 777                                        mask);
 778         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 779 #ifdef DCACHE_ALIASING_POSSIBLE
 780                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 781                 cheetah_xcall_deliver(data0,
 782                                       __pa(pg_addr),
 783                                       0, mask);
 784 #endif
 785         }
 786 #ifdef CONFIG_DEBUG_DCFLUSH
 787         atomic_inc(&dcpage_flushes_xcall);
 788 #endif
 789  flush_self:
 790         __local_flush_dcache_page(page);
 791
 792         put_cpu();
 793 }
 794
 795 void smp_receive_signal(int cpu)
 796 {
 797         cpumask_t mask = cpumask_of_cpu(cpu);
 798
 799         if (cpu_online(cpu)) {
 800                 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
 801
 802                 if (tlb_type == spitfire)
 803                         spitfire_xcall_deliver(data0, 0, 0, mask);
 804                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 805                         cheetah_xcall_deliver(data0, 0, 0, mask);
 806                 else if (tlb_type == hypervisor)
 807                         hypervisor_xcall_deliver(data0, 0, 0, mask);
 808         }
 809 }
 810
 811 void smp_receive_signal_client(int irq, struct pt_regs *regs)
 812 {
 813         /* Just return, rtrap takes care of the rest. */
 814         clear_softint(1 << irq);
 815 }
 816
 817 void smp_report_regs(void)
 818 {
 819         smp_cross_call(&xcall_report_regs, 0, 0, 0);
 820 }
 821
 822 /* We know that the window frames of the user have been flushed
 823  * to the stack before we get here because all callers of us
 824  * are flush_tlb_*() routines, and these run after flush_cache_*()
 825  * which performs the flushw.
 826  *
 827  * The SMP TLB coherency scheme we use works as follows:
 828  *
 829  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
 830  *    space has (potentially) executed on, this is the heuristic
 831  *    we use to avoid doing cross calls.
 832  *
 833  *    Also, for flushing from kswapd and also for clones, we
 834  *    use cpu_vm_mask as the list of cpus to make run the TLB.
 835  *
 836  * 2) TLB context numbers are shared globally across all processors
 837  *    in the system, this allows us to play several games to avoid
 838  *    cross calls.
 839  *
 840  *    One invariant is that when a cpu switches to a process, and
 841  *    that processes tsk->active_mm->cpu_vm_mask does not have the
 842  *    current cpu's bit set, that tlb context is flushed locally.
 843  *
 844  *    If the address space is non-shared (ie. mm->count == 1) we avoid
 845  *    cross calls when we want to flush the currently running process's
 846  *    tlb state.  This is done by clearing all cpu bits except the current
 847  *    processor's in current->active_mm->cpu_vm_mask and performing the
 848  *    flush locally only.  This will force any subsequent cpus which run
 849  *    this task to flush the context from the local tlb if the process
 850  *    migrates to another cpu (again).
 851  *
 852  * 3) For shared address spaces (threads) and swapping we bite the
 853  *    bullet for most cases and perform the cross call (but only to
 854  *    the cpus listed in cpu_vm_mask).
 855  *
 856  *    The performance gain from "optimizing" away the cross call for threads is
 857  *    questionable (in theory the big win for threads is the massive sharing of
 858  *    address space state across processors).
 859  */
 860
 861 /* This currently is only used by the hugetlb arch pre-fault
 862  * hook on UltraSPARC-III+ and later when changing the pagesize
 863  * bits of the context register for an address space.
 864  */
 865 void smp_flush_tlb_mm(struct mm_struct *mm)
 866 {
 867         u32 ctx = CTX_HWBITS(mm->context);
 868         int cpu = get_cpu();
 869
 870         if (atomic_read(&mm->mm_users) == 1) {
 871                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
 872                 goto local_flush_and_out;
 873         }
 874
 875         smp_cross_call_masked(&xcall_flush_tlb_mm,
 876                               ctx, 0, 0,
 877                               mm->cpu_vm_mask);
 878
 879 local_flush_and_out:
 880         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
 881
 882         put_cpu();
 883 }
 884
 885 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
 886 {
 887         u32 ctx = CTX_HWBITS(mm->context);
 888         int cpu = get_cpu();
 889
 890         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
 891                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
 892         else
 893                 smp_cross_call_masked(&xcall_flush_tlb_pending,
 894                                       ctx, nr, (unsigned long) vaddrs,
 895                                       mm->cpu_vm_mask);
 896
 897         __flush_tlb_pending(ctx, nr, vaddrs);
 898
 899         put_cpu();
 900 }
 901
 902 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
 903 {
 904         start &= PAGE_MASK;
 905         end    = PAGE_ALIGN(end);
 906         if (start != end) {
 907                 smp_cross_call(&xcall_flush_tlb_kernel_range,
 908                                0, start, end);
 909
 910                 __flush_tlb_kernel_range(start, end);
 911         }
 912 }
 913
 914 /* CPU capture. */
 915 /* #define CAPTURE_DEBUG */
 916 extern unsigned long xcall_capture;
 917
 918 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
 919 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
 920 static unsigned long penguins_are_doing_time;
 921
 922 void smp_capture(void)
 923 {
 924         int result = atomic_add_ret(1, &smp_capture_depth);
 925
 926         if (result == 1) {
 927                 int ncpus = num_online_cpus();
 928
 929 #ifdef CAPTURE_DEBUG
 930                 printk("CPU[%d]: Sending penguins to jail...",
 931                        smp_processor_id());
 932 #endif
 933                 penguins_are_doing_time = 1;
 934                 membar_storestore_loadstore();
 935                 atomic_inc(&smp_capture_registry);
 936                 smp_cross_call(&xcall_capture, 0, 0, 0);
 937                 while (atomic_read(&smp_capture_registry) != ncpus)
 938                         rmb();
 939 #ifdef CAPTURE_DEBUG
 940                 printk("done\n");
 941 #endif
 942         }
 943 }
 944
 945 void smp_release(void)
 946 {
 947         if (atomic_dec_and_test(&smp_capture_depth)) {
 948 #ifdef CAPTURE_DEBUG
 949                 printk("CPU[%d]: Giving pardon to "
 950                        "imprisoned penguins\n",
 951                        smp_processor_id());
 952 #endif
 953                 penguins_are_doing_time = 0;
 954                 membar_storeload_storestore();
 955                 atomic_dec(&smp_capture_registry);
 956         }
 957 }
 958
 959 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
 960  * can service tlb flush xcalls...
 961  */
 962 extern void prom_world(int);
 963
 964 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
 965 {
 966         clear_softint(1 << irq);
 967
 968         preempt_disable();
 969
 970         __asm__ __volatile__("flushw");
 971         prom_world(1);
 972         atomic_inc(&smp_capture_registry);
 973         membar_storeload_storestore();
 974         while (penguins_are_doing_time)
 975                 rmb();
 976         atomic_dec(&smp_capture_registry);
 977         prom_world(0);
 978
 979         preempt_enable();
 980 }
 981
 982 #define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
 983 #define prof_counter(__cpu)             cpu_data(__cpu).counter
 984
 985 void smp_percpu_timer_interrupt(struct pt_regs *regs)
 986 {
 987         unsigned long compare, tick, pstate;
 988         int cpu = smp_processor_id();
 989         int user = user_mode(regs);
 990
 991         /*
 992          * Check for level 14 softint.
 993          */
 994         {
 995                 unsigned long tick_mask = tick_ops->softint_mask;
 996
 997                 if (!(get_softint() & tick_mask)) {
 998                         extern void handler_irq(int, struct pt_regs *);
 999
1000                         handler_irq(14, regs);
1001                         return;
1002                 }
1003                 clear_softint(tick_mask);
1004         }
1005
1006         do {
1007                 profile_tick(CPU_PROFILING, regs);
1008                 if (!--prof_counter(cpu)) {
1009                         irq_enter();
1010
1011                         if (cpu == boot_cpu_id) {
1012                                 kstat_this_cpu.irqs[0]++;
1013                                 timer_tick_interrupt(regs);
1014                         }
1015
1016                         update_process_times(user);
1017
1018                         irq_exit();
1019
1020                         prof_counter(cpu) = prof_multiplier(cpu);
1021                 }
1022
1023                 /* Guarantee that the following sequences execute
1024                  * uninterrupted.
1025                  */
1026                 __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1027                                      "wrpr      %0, %1, %%pstate"
1028                                      : "=r" (pstate)
1029                                      : "i" (PSTATE_IE));
1030
1031                 compare = tick_ops->add_compare(current_tick_offset);
1032                 tick = tick_ops->get_tick();
1033
1034                 /* Restore PSTATE_IE. */
1035                 __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1036                                      : /* no outputs */
1037                                      : "r" (pstate));
1038         } while (time_after_eq(tick, compare));
1039 }
1040
1041 static void __init smp_setup_percpu_timer(void)
1042 {
1043         int cpu = smp_processor_id();
1044         unsigned long pstate;
1045
1046         prof_counter(cpu) = prof_multiplier(cpu) = 1;
1047
1048         /* Guarantee that the following sequences execute
1049          * uninterrupted.
1050          */
1051         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1052                              "wrpr      %0, %1, %%pstate"
1053                              : "=r" (pstate)
1054                              : "i" (PSTATE_IE));
1055
1056         tick_ops->init_tick(current_tick_offset);
1057
1058         /* Restore PSTATE_IE. */
1059         __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1060                              : /* no outputs */
1061                              : "r" (pstate));
1062 }
1063
1064 void __init smp_tick_init(void)
1065 {
1066         boot_cpu_id = hard_smp_processor_id();
1067         current_tick_offset = timer_tick_offset;
1068
1069         cpu_set(boot_cpu_id, cpu_online_map);
1070         prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1071 }
1072
1073 /* /proc/profile writes can call this, don't __init it please. */
1074 static DEFINE_SPINLOCK(prof_setup_lock);
1075
1076 int setup_profiling_timer(unsigned int multiplier)
1077 {
1078         unsigned long flags;
1079         int i;
1080
1081         if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1082                 return -EINVAL;
1083
1084         spin_lock_irqsave(&prof_setup_lock, flags);
1085         for (i = 0; i < NR_CPUS; i++)
1086                 prof_multiplier(i) = multiplier;
1087         current_tick_offset = (timer_tick_offset / multiplier);
1088         spin_unlock_irqrestore(&prof_setup_lock, flags);
1089
1090         return 0;
1091 }
1092
1093 /* Constrain the number of cpus to max_cpus.  */
1094 void __init smp_prepare_cpus(unsigned int max_cpus)
1095 {
1096         if (num_possible_cpus() > max_cpus) {
1097                 int instance, mid;
1098
1099                 instance = 0;
1100                 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1101                         if (mid != boot_cpu_id) {
1102                                 cpu_clear(mid, phys_cpu_present_map);
1103                                 if (num_possible_cpus() <= max_cpus)
1104                                         break;
1105                         }
1106                         instance++;
1107                 }
1108         }
1109
1110         smp_store_cpu_info(boot_cpu_id);
1111 }
1112
1113 /* Set this up early so that things like the scheduler can init
1114  * properly.  We use the same cpu mask for both the present and
1115  * possible cpu map.
1116  */
1117 void __init smp_setup_cpu_possible_map(void)
1118 {
1119         int instance, mid;
1120
1121         instance = 0;
1122         while (!cpu_find_by_instance(instance, NULL, &mid)) {
1123                 if (mid < NR_CPUS)
1124                         cpu_set(mid, phys_cpu_present_map);
1125                 instance++;
1126         }
1127 }
1128
1129 void __devinit smp_prepare_boot_cpu(void)
1130 {
1131         int cpu = hard_smp_processor_id();
1132
1133         if (cpu >= NR_CPUS) {
1134                 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1135                 prom_halt();
1136         }
1137
1138         current_thread_info()->cpu = cpu;
1139         __local_per_cpu_offset = __per_cpu_offset(cpu);
1140
1141         cpu_set(smp_processor_id(), cpu_online_map);
1142         cpu_set(smp_processor_id(), phys_cpu_present_map);
1143 }
1144
1145 int __devinit __cpu_up(unsigned int cpu)
1146 {
1147         int ret = smp_boot_one_cpu(cpu);
1148
1149         if (!ret) {
1150                 cpu_set(cpu, smp_commenced_mask);
1151                 while (!cpu_isset(cpu, cpu_online_map))
1152                         mb();
1153                 if (!cpu_isset(cpu, cpu_online_map)) {
1154                         ret = -ENODEV;
1155                 } else {
1156                         smp_synchronize_one_tick(cpu);
1157                 }
1158         }
1159         return ret;
1160 }
1161
1162 void __init smp_cpus_done(unsigned int max_cpus)
1163 {
1164         unsigned long bogosum = 0;
1165         int i;
1166
1167         for (i = 0; i < NR_CPUS; i++) {
1168                 if (cpu_online(i))
1169                         bogosum += cpu_data(i).udelay_val;
1170         }
1171         printk("Total of %ld processors activated "
1172                "(%lu.%02lu BogoMIPS).\n",
1173                (long) num_online_cpus(),
1174                bogosum/(500000/HZ),
1175                (bogosum/(5000/HZ))%100);
1176 }
1177
1178 void smp_send_reschedule(int cpu)
1179 {
1180         smp_receive_signal(cpu);
1181 }
1182
1183 /* This is a nop because we capture all other cpus
1184  * anyways when making the PROM active.
1185  */
1186 void smp_send_stop(void)
1187 {
1188 }
1189
1190 unsigned long __per_cpu_base __read_mostly;
1191 unsigned long __per_cpu_shift __read_mostly;
1192
1193 EXPORT_SYMBOL(__per_cpu_base);
1194 EXPORT_SYMBOL(__per_cpu_shift);
1195
1196 void __init setup_per_cpu_areas(void)
1197 {
1198         unsigned long goal, size, i;
1199         char *ptr;
1200
1201         /* Copy section for each CPU (we discard the original) */
1202         goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
1203 #ifdef CONFIG_MODULES
1204         if (goal < PERCPU_ENOUGH_ROOM)
1205                 goal = PERCPU_ENOUGH_ROOM;
1206 #endif
1207         __per_cpu_shift = 0;
1208         for (size = 1UL; size < goal; size <<= 1UL)
1209                 __per_cpu_shift++;
1210
1211         ptr = alloc_bootmem(size * NR_CPUS);
1212
1213         __per_cpu_base = ptr - __per_cpu_start;
1214
1215         for (i = 0; i < NR_CPUS; i++, ptr += size)
1216                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1217 }