1 /* tsb.S: Sparc64 TSB table handling.
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
7 #include <asm/hypervisor.h>
12 /* Invoked from TLB miss handler, we are in the
13 * MMU global registers and they are setup like
16 * %g1: TSB entry pointer
17 * %g2: available temporary
18 * %g3: FAULT_CODE_{D,I}TLB
19 * %g4: available temporary
20 * %g5: available temporary
22 * %g7: available temporary, will be loaded by us with
23 * the physical address base of the linux page
24 * tables for the current address space
27 mov TLB_TAG_ACCESS, %g4
28 ba,pt %xcc, tsb_miss_page_table_walk
29 ldxa [%g4] ASI_DMMU, %g4
32 mov TLB_TAG_ACCESS, %g4
33 ba,pt %xcc, tsb_miss_page_table_walk
34 ldxa [%g4] ASI_IMMU, %g4
36 /* At this point we have:
37 * %g4 -- missing virtual address
38 * %g1 -- TSB entry address
39 * %g6 -- TAG TARGET ((vaddr >> 22) | (ctx << 48))
41 tsb_miss_page_table_walk:
42 TRAP_LOAD_PGD_PHYS(%g7, %g5)
44 /* And now we have the PGD base physical address in %g7. */
45 tsb_miss_page_table_walk_sun4v_fastpath:
46 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
49 TSB_LOCK_TAG(%g1, %g2, %g7)
51 /* Load and check PTE. */
52 ldxa [%g5] ASI_PHYS_USE_EC, %g5
53 brgez,a,pn %g5, tsb_do_fault
56 /* If it is larger than the base page size, don't
57 * bother putting it into the TSB.
60 sethi %hi(_PAGE_ALL_SZ_BITS >> 32), %g7
62 sethi %hi(_PAGE_SZBITS >> 32), %g7
64 bne,a,pn %xcc, tsb_tlb_reload
67 TSB_WRITE(%g1, %g5, %g6)
69 /* Finally, load TLB and return from trap. */
71 cmp %g3, FAULT_CODE_DTLB
72 bne,pn %xcc, tsb_itlb_load
77 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
79 .section .sun4v_2insn_patch, "ax"
85 /* For sun4v the ASI_DTLB_DATA_IN store and the retry
86 * instruction get nop'd out and we get here to branch
87 * to the sun4v tlb load code. The registers are setup
94 * The sun4v TLB load wants the PTE in %g3 so we fix that
97 ba,pt %xcc, sun4v_dtlb_load
102 661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
104 .section .sun4v_2insn_patch, "ax"
110 /* For sun4v the ASI_ITLB_DATA_IN store and the retry
111 * instruction get nop'd out and we get here to branch
112 * to the sun4v tlb load code. The registers are setup
119 * The sun4v TLB load wants the PTE in %g3 so we fix that
122 ba,pt %xcc, sun4v_itlb_load
125 /* No valid entry in the page tables, do full fault
131 cmp %g3, FAULT_CODE_DTLB
133 661: rdpr %pstate, %g5
134 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
135 .section .sun4v_2insn_patch, "ax"
141 bne,pn %xcc, tsb_do_itlb_fault
148 661: mov TLB_TAG_ACCESS, %g4
149 ldxa [%g4] ASI_DMMU, %g5
150 .section .sun4v_2insn_patch, "ax"
156 be,pt %xcc, sparc64_realfault_common
157 mov FAULT_CODE_DTLB, %g4
158 ba,pt %xcc, winfix_trampoline
163 ba,pt %xcc, sparc64_realfault_common
164 mov FAULT_CODE_ITLB, %g4
166 .globl sparc64_realfault_common
167 sparc64_realfault_common:
168 /* fault code in %g4, fault address in %g5, etrap will
169 * preserve these two values in %l4 and %l5 respectively
171 ba,pt %xcc, etrap ! Save trap state
173 stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
174 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
175 call do_sparc64_fault ! Call fault handler
176 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
177 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
178 nop ! Delay slot (fill me)
181 rdpr %tpc, %g3 ! Prepare winfixup TNPC
182 or %g3, 0x7c, %g3 ! Compute branch offset
183 wrpr %g3, %tnpc ! Write it into TNPC
186 /* Insert an entry into the TSB.
188 * %o0: TSB entry pointer (virt or phys address)
196 wrpr %o5, PSTATE_IE, %pstate
197 TSB_LOCK_TAG(%o0, %g2, %g3)
198 TSB_WRITE(%o0, %o2, %o1)
203 /* Flush the given TSB entry if it has the matching
206 * %o0: TSB entry pointer (virt or phys address)
212 sethi %hi(TSB_TAG_LOCK_HIGH), %g2
213 1: TSB_LOAD_TAG(%o0, %g1)
221 TSB_CAS_TAG(%o0, %g1, %o3)
228 /* Reload MMU related context switch state at
231 * %o0: page table physical address
232 * %o1: TSB register value
233 * %o2: TSB virtual address
234 * %o3: TSB mapping locked PTE
235 * %o4: Hypervisor TSB descriptor physical address
237 * We have to run this whole thing with interrupts
238 * disabled so that the current cpu doesn't change
242 .globl __tsb_context_switch
243 __tsb_context_switch:
245 wrpr %o5, PSTATE_IE, %pstate
247 ldub [%g6 + TI_CPU], %g1
248 sethi %hi(trap_block), %g2
249 sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1
250 or %g2, %lo(trap_block), %g2
252 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
254 sethi %hi(tlb_type), %g1
255 lduw [%g1 + %lo(tlb_type)], %g1
260 /* Hypervisor TSB switch. */
261 mov SCRATCHPAD_UTSBREG1, %g1
262 stxa %o1, [%g1] ASI_SCRATCHPAD
264 mov SCRATCHPAD_UTSBREG2, %g1
265 stxa %g2, [%g1] ASI_SCRATCHPAD
267 mov HV_FAST_MMU_TSB_CTXNON0, %o5
275 /* SUN4U TSB switch. */
277 stxa %o1, [%g1] ASI_DMMU
279 stxa %o1, [%g1] ASI_IMMU
285 sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
286 mov TLB_TAG_ACCESS, %g1
287 lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
288 stxa %o2, [%g1] ASI_DMMU
291 stxa %o3, [%g2] ASI_DTLB_DATA_ACCESS