arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/system.h>
  28 #include <asm/page.h>
  29 #include <asm/pgalloc.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/oplib.h>
  32 #include <asm/iommu.h>
  33 #include <asm/io.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/tlbflush.h>
  37 #include <asm/dma.h>
  38 #include <asm/starfire.h>
  39 #include <asm/tlb.h>
  40 #include <asm/spitfire.h>
  41 #include <asm/sections.h>
  42 #include <asm/tsb.h>
  43 #include <asm/hypervisor.h>
  44
  45 extern void device_scan(void);
  46
  47 #define MAX_BANKS       32
  48
  49 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
  50 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
  51 static int pavail_ents __initdata;
  52 static int pavail_rescan_ents __initdata;
  53
  54 static int cmp_p64(const void *a, const void *b)
  55 {
  56         const struct linux_prom64_registers *x = a, *y = b;
  57
  58         if (x->phys_addr > y->phys_addr)
  59                 return 1;
  60         if (x->phys_addr < y->phys_addr)
  61                 return -1;
  62         return 0;
  63 }
  64
  65 static void __init read_obp_memory(const char *property,
  66                                    struct linux_prom64_registers *regs,
  67                                    int *num_ents)
  68 {
  69         int node = prom_finddevice("/memory");
  70         int prop_size = prom_getproplen(node, property);
  71         int ents, ret, i;
  72
  73         ents = prop_size / sizeof(struct linux_prom64_registers);
  74         if (ents > MAX_BANKS) {
  75                 prom_printf("The machine has more %s property entries than "
  76                             "this kernel can support (%d).\n",
  77                             property, MAX_BANKS);
  78                 prom_halt();
  79         }
  80
  81         ret = prom_getproperty(node, property, (char *) regs, prop_size);
  82         if (ret == -1) {
  83                 prom_printf("Couldn't get %s property from /memory.\n");
  84                 prom_halt();
  85         }
  86
  87         *num_ents = ents;
  88
  89         /* Sanitize what we got from the firmware, by page aligning
  90          * everything.
  91          */
  92         for (i = 0; i < ents; i++) {
  93                 unsigned long base, size;
  94
  95                 base = regs[i].phys_addr;
  96                 size = regs[i].reg_size;
  97
  98                 size &= PAGE_MASK;
  99                 if (base & ~PAGE_MASK) {
 100                         unsigned long new_base = PAGE_ALIGN(base);
 101
 102                         size -= new_base - base;
 103                         if ((long) size < 0L)
 104                                 size = 0UL;
 105                         base = new_base;
 106                 }
 107                 regs[i].phys_addr = base;
 108                 regs[i].reg_size = size;
 109         }
 110         sort(regs, ents, sizeof(struct linux_prom64_registers),
 111              cmp_p64, NULL);
 112 }
 113
 114 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
 115
 116 /* Ugly, but necessary... -DaveM */
 117 unsigned long phys_base __read_mostly;
 118 unsigned long kern_base __read_mostly;
 119 unsigned long kern_size __read_mostly;
 120 unsigned long pfn_base __read_mostly;
 121
 122 /* get_new_mmu_context() uses "cache + 1".  */
 123 DEFINE_SPINLOCK(ctx_alloc_lock);
 124 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 125 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
 126 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
 127
 128 /* References to special section boundaries */
 129 extern char  _start[], _end[];
 130
 131 /* Initial ramdisk setup */
 132 extern unsigned long sparc_ramdisk_image64;
 133 extern unsigned int sparc_ramdisk_image;
 134 extern unsigned int sparc_ramdisk_size;
 135
 136 struct page *mem_map_zero __read_mostly;
 137
 138 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 139
 140 unsigned long sparc64_kern_pri_context __read_mostly;
 141 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 142 unsigned long sparc64_kern_sec_context __read_mostly;
 143
 144 int bigkernel = 0;
 145
 146 kmem_cache_t *pgtable_cache __read_mostly;
 147
 148 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
 149 {
 150         clear_page(addr);
 151 }
 152
 153 void pgtable_cache_init(void)
 154 {
 155         pgtable_cache = kmem_cache_create("pgtable_cache",
 156                                           PAGE_SIZE, PAGE_SIZE,
 157                                           SLAB_HWCACHE_ALIGN |
 158                                           SLAB_MUST_HWCACHE_ALIGN,
 159                                           zero_ctor,
 160                                           NULL);
 161         if (!pgtable_cache) {
 162                 prom_printf("pgtable_cache_init(): Could not create!\n");
 163                 prom_halt();
 164         }
 165 }
 166
 167 #ifdef CONFIG_DEBUG_DCFLUSH
 168 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 169 #ifdef CONFIG_SMP
 170 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 171 #endif
 172 #endif
 173
 174 __inline__ void flush_dcache_page_impl(struct page *page)
 175 {
 176 #ifdef CONFIG_DEBUG_DCFLUSH
 177         atomic_inc(&dcpage_flushes);
 178 #endif
 179
 180 #ifdef DCACHE_ALIASING_POSSIBLE
 181         __flush_dcache_page(page_address(page),
 182                             ((tlb_type == spitfire) &&
 183                              page_mapping(page) != NULL));
 184 #else
 185         if (page_mapping(page) != NULL &&
 186             tlb_type == spitfire)
 187                 __flush_icache_page(__pa(page_address(page)));
 188 #endif
 189 }
 190
 191 #define PG_dcache_dirty         PG_arch_1
 192 #define PG_dcache_cpu_shift     24
 193 #define PG_dcache_cpu_mask      (256 - 1)
 194
 195 #if NR_CPUS > 256
 196 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
 197 #endif
 198
 199 #define dcache_dirty_cpu(page) \
 200         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 201
 202 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 203 {
 204         unsigned long mask = this_cpu;
 205         unsigned long non_cpu_bits;
 206
 207         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 208         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 209
 210         __asm__ __volatile__("1:\n\t"
 211                              "ldx       [%2], %%g7\n\t"
 212                              "and       %%g7, %1, %%g1\n\t"
 213                              "or        %%g1, %0, %%g1\n\t"
 214                              "casx      [%2], %%g7, %%g1\n\t"
 215                              "cmp       %%g7, %%g1\n\t"
 216                              "membar    #StoreLoad | #StoreStore\n\t"
 217                              "bne,pn    %%xcc, 1b\n\t"
 218                              " nop"
 219                              : /* no outputs */
 220                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 221                              : "g1", "g7");
 222 }
 223
 224 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 225 {
 226         unsigned long mask = (1UL << PG_dcache_dirty);
 227
 228         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 229                              "1:\n\t"
 230                              "ldx       [%2], %%g7\n\t"
 231                              "srlx      %%g7, %4, %%g1\n\t"
 232                              "and       %%g1, %3, %%g1\n\t"
 233                              "cmp       %%g1, %0\n\t"
 234                              "bne,pn    %%icc, 2f\n\t"
 235                              " andn     %%g7, %1, %%g1\n\t"
 236                              "casx      [%2], %%g7, %%g1\n\t"
 237                              "cmp       %%g7, %%g1\n\t"
 238                              "membar    #StoreLoad | #StoreStore\n\t"
 239                              "bne,pn    %%xcc, 1b\n\t"
 240                              " nop\n"
 241                              "2:"
 242                              : /* no outputs */
 243                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 244                                "i" (PG_dcache_cpu_mask),
 245                                "i" (PG_dcache_cpu_shift)
 246                              : "g1", "g7");
 247 }
 248
 249 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 250 {
 251         unsigned long tsb_addr = (unsigned long) ent;
 252
 253         if (tlb_type == cheetah_plus)
 254                 tsb_addr = __pa(tsb_addr);
 255
 256         __tsb_insert(tsb_addr, tag, pte);
 257 }
 258
 259 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 260 {
 261         struct mm_struct *mm;
 262         struct page *page;
 263         unsigned long pfn;
 264         unsigned long pg_flags;
 265
 266         pfn = pte_pfn(pte);
 267         if (pfn_valid(pfn) &&
 268             (page = pfn_to_page(pfn), page_mapping(page)) &&
 269             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 270                 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 271                            PG_dcache_cpu_mask);
 272                 int this_cpu = get_cpu();
 273
 274                 /* This is just to optimize away some function calls
 275                  * in the SMP case.
 276                  */
 277                 if (cpu == this_cpu)
 278                         flush_dcache_page_impl(page);
 279                 else
 280                         smp_flush_dcache_page_impl(page, cpu);
 281
 282                 clear_dcache_dirty_cpu(page, cpu);
 283
 284                 put_cpu();
 285         }
 286
 287         mm = vma->vm_mm;
 288         if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
 289                 struct tsb *tsb;
 290                 unsigned long tag;
 291
 292                 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
 293                                        (mm->context.tsb_nentries - 1UL)];
 294                 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
 295                 tsb_insert(tsb, tag, pte_val(pte));
 296         }
 297 }
 298
 299 void flush_dcache_page(struct page *page)
 300 {
 301         struct address_space *mapping;
 302         int this_cpu;
 303
 304         /* Do not bother with the expensive D-cache flush if it
 305          * is merely the zero page.  The 'bigcore' testcase in GDB
 306          * causes this case to run millions of times.
 307          */
 308         if (page == ZERO_PAGE(0))
 309                 return;
 310
 311         this_cpu = get_cpu();
 312
 313         mapping = page_mapping(page);
 314         if (mapping && !mapping_mapped(mapping)) {
 315                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 316                 if (dirty) {
 317                         int dirty_cpu = dcache_dirty_cpu(page);
 318
 319                         if (dirty_cpu == this_cpu)
 320                                 goto out;
 321                         smp_flush_dcache_page_impl(page, dirty_cpu);
 322                 }
 323                 set_dcache_dirty(page, this_cpu);
 324         } else {
 325                 /* We could delay the flush for the !page_mapping
 326                  * case too.  But that case is for exec env/arg
 327                  * pages and those are %99 certainly going to get
 328                  * faulted into the tlb (and thus flushed) anyways.
 329                  */
 330                 flush_dcache_page_impl(page);
 331         }
 332
 333 out:
 334         put_cpu();
 335 }
 336
 337 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 338 {
 339         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 340         if (tlb_type == spitfire) {
 341                 unsigned long kaddr;
 342
 343                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 344                         __flush_icache_page(__get_phys(kaddr));
 345         }
 346 }
 347
 348 unsigned long page_to_pfn(struct page *page)
 349 {
 350         return (unsigned long) ((page - mem_map) + pfn_base);
 351 }
 352
 353 struct page *pfn_to_page(unsigned long pfn)
 354 {
 355         return (mem_map + (pfn - pfn_base));
 356 }
 357
 358 void show_mem(void)
 359 {
 360         printk("Mem-info:\n");
 361         show_free_areas();
 362         printk("Free swap:       %6ldkB\n",
 363                nr_swap_pages << (PAGE_SHIFT-10));
 364         printk("%ld pages of RAM\n", num_physpages);
 365         printk("%d free pages\n", nr_free_pages());
 366 }
 367
 368 void mmu_info(struct seq_file *m)
 369 {
 370         if (tlb_type == cheetah)
 371                 seq_printf(m, "MMU Type\t: Cheetah\n");
 372         else if (tlb_type == cheetah_plus)
 373                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 374         else if (tlb_type == spitfire)
 375                 seq_printf(m, "MMU Type\t: Spitfire\n");
 376         else if (tlb_type == hypervisor)
 377                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 378         else
 379                 seq_printf(m, "MMU Type\t: ???\n");
 380
 381 #ifdef CONFIG_DEBUG_DCFLUSH
 382         seq_printf(m, "DCPageFlushes\t: %d\n",
 383                    atomic_read(&dcpage_flushes));
 384 #ifdef CONFIG_SMP
 385         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 386                    atomic_read(&dcpage_flushes_xcall));
 387 #endif /* CONFIG_SMP */
 388 #endif /* CONFIG_DEBUG_DCFLUSH */
 389 }
 390
 391 struct linux_prom_translation {
 392         unsigned long virt;
 393         unsigned long size;
 394         unsigned long data;
 395 };
 396
 397 /* Exported for kernel TLB miss handling in ktlb.S */
 398 struct linux_prom_translation prom_trans[512] __read_mostly;
 399 unsigned int prom_trans_ents __read_mostly;
 400
 401 extern unsigned long prom_boot_page;
 402 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 403 extern int prom_get_mmu_ihandle(void);
 404 extern void register_prom_callbacks(void);
 405
 406 /* Exported for SMP bootup purposes. */
 407 unsigned long kern_locked_tte_data;
 408
 409 /*
 410  * Translate PROM's mapping we capture at boot time into physical address.
 411  * The second parameter is only set from prom_callback() invocations.
 412  */
 413 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 414 {
 415         int i;
 416
 417         for (i = 0; i < prom_trans_ents; i++) {
 418                 struct linux_prom_translation *p = &prom_trans[i];
 419
 420                 if (promva >= p->virt &&
 421                     promva < (p->virt + p->size)) {
 422                         unsigned long base = p->data & _PAGE_PADDR;
 423
 424                         if (error)
 425                                 *error = 0;
 426                         return base + (promva & (8192 - 1));
 427                 }
 428         }
 429         if (error)
 430                 *error = 1;
 431         return 0UL;
 432 }
 433
 434 /* The obp translations are saved based on 8k pagesize, since obp can
 435  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 436  * HI_OBP_ADDRESS range are handled in ktlb.S.
 437  */
 438 static inline int in_obp_range(unsigned long vaddr)
 439 {
 440         return (vaddr >= LOW_OBP_ADDRESS &&
 441                 vaddr < HI_OBP_ADDRESS);
 442 }
 443
 444 static int cmp_ptrans(const void *a, const void *b)
 445 {
 446         const struct linux_prom_translation *x = a, *y = b;
 447
 448         if (x->virt > y->virt)
 449                 return 1;
 450         if (x->virt < y->virt)
 451                 return -1;
 452         return 0;
 453 }
 454
 455 /* Read OBP translations property into 'prom_trans[]'.  */
 456 static void __init read_obp_translations(void)
 457 {
 458         int n, node, ents, first, last, i;
 459
 460         node = prom_finddevice("/virtual-memory");
 461         n = prom_getproplen(node, "translations");
 462         if (unlikely(n == 0 || n == -1)) {
 463                 prom_printf("prom_mappings: Couldn't get size.\n");
 464                 prom_halt();
 465         }
 466         if (unlikely(n > sizeof(prom_trans))) {
 467                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
 468                 prom_halt();
 469         }
 470
 471         if ((n = prom_getproperty(node, "translations",
 472                                   (char *)&prom_trans[0],
 473                                   sizeof(prom_trans))) == -1) {
 474                 prom_printf("prom_mappings: Couldn't get property.\n");
 475                 prom_halt();
 476         }
 477
 478         n = n / sizeof(struct linux_prom_translation);
 479
 480         ents = n;
 481
 482         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 483              cmp_ptrans, NULL);
 484
 485         /* Now kick out all the non-OBP entries.  */
 486         for (i = 0; i < ents; i++) {
 487                 if (in_obp_range(prom_trans[i].virt))
 488                         break;
 489         }
 490         first = i;
 491         for (; i < ents; i++) {
 492                 if (!in_obp_range(prom_trans[i].virt))
 493                         break;
 494         }
 495         last = i;
 496
 497         for (i = 0; i < (last - first); i++) {
 498                 struct linux_prom_translation *src = &prom_trans[i + first];
 499                 struct linux_prom_translation *dest = &prom_trans[i];
 500
 501                 *dest = *src;
 502         }
 503         for (; i < ents; i++) {
 504                 struct linux_prom_translation *dest = &prom_trans[i];
 505                 dest->virt = dest->size = dest->data = 0x0UL;
 506         }
 507
 508         prom_trans_ents = last - first;
 509
 510         if (tlb_type == spitfire) {
 511                 /* Clear diag TTE bits. */
 512                 for (i = 0; i < prom_trans_ents; i++)
 513                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 514         }
 515 }
 516
 517 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 518                                        unsigned long pte,
 519                                        unsigned long mmu)
 520 {
 521         register unsigned long func asm("%o5");
 522         register unsigned long arg0 asm("%o0");
 523         register unsigned long arg1 asm("%o1");
 524         register unsigned long arg2 asm("%o2");
 525         register unsigned long arg3 asm("%o3");
 526
 527         func = HV_FAST_MMU_MAP_PERM_ADDR;
 528         arg0 = vaddr;
 529         arg1 = 0;
 530         arg2 = pte;
 531         arg3 = mmu;
 532         __asm__ __volatile__("ta        0x80"
 533                              : "=&r" (func), "=&r" (arg0),
 534                                "=&r" (arg1), "=&r" (arg2),
 535                                "=&r" (arg3)
 536                              : "0" (func), "1" (arg0), "2" (arg1),
 537                                "3" (arg2), "4" (arg3));
 538 }
 539
 540 static void __init remap_kernel(void)
 541 {
 542         unsigned long phys_page, tte_vaddr, tte_data;
 543         int tlb_ent = sparc64_highest_locked_tlbent();
 544
 545         tte_vaddr = (unsigned long) KERNBASE;
 546         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 547         tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
 548                                  _PAGE_CP | _PAGE_CV | _PAGE_P |
 549                                  _PAGE_L | _PAGE_W));
 550
 551         kern_locked_tte_data = tte_data;
 552
 553         /* Now lock us into the TLBs via Hypervisor or OBP. */
 554         if (tlb_type == hypervisor) {
 555                 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 556                 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 557                 if (bigkernel) {
 558                         tte_vaddr += 0x400000;
 559                         tte_data += 0x400000;
 560                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 561                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 562                 }
 563         } else {
 564                 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
 565                 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
 566                 if (bigkernel) {
 567                         tlb_ent -= 1;
 568                         prom_dtlb_load(tlb_ent,
 569                                        tte_data + 0x400000,
 570                                        tte_vaddr + 0x400000);
 571                         prom_itlb_load(tlb_ent,
 572                                        tte_data + 0x400000,
 573                                        tte_vaddr + 0x400000);
 574                 }
 575                 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
 576         }
 577         if (tlb_type == cheetah_plus) {
 578                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 579                                             CTX_CHEETAH_PLUS_NUC);
 580                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 581                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 582         }
 583 }
 584
 585
 586 static void __init inherit_prom_mappings(void)
 587 {
 588         read_obp_translations();
 589
 590         /* Now fixup OBP's idea about where we really are mapped. */
 591         prom_printf("Remapping the kernel... ");
 592         remap_kernel();
 593         prom_printf("done.\n");
 594
 595         prom_printf("Registering callbacks... ");
 596         register_prom_callbacks();
 597         prom_printf("done.\n");
 598 }
 599
 600 void prom_world(int enter)
 601 {
 602         if (!enter)
 603                 set_fs((mm_segment_t) { get_thread_current_ds() });
 604
 605         __asm__ __volatile__("flushw");
 606 }
 607
 608 #ifdef DCACHE_ALIASING_POSSIBLE
 609 void __flush_dcache_range(unsigned long start, unsigned long end)
 610 {
 611         unsigned long va;
 612
 613         if (tlb_type == spitfire) {
 614                 int n = 0;
 615
 616                 for (va = start; va < end; va += 32) {
 617                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 618                         if (++n >= 512)
 619                                 break;
 620                 }
 621         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 622                 start = __pa(start);
 623                 end = __pa(end);
 624                 for (va = start; va < end; va += 32)
 625                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 626                                              "membar #Sync"
 627                                              : /* no outputs */
 628                                              : "r" (va),
 629                                                "i" (ASI_DCACHE_INVALIDATE));
 630         }
 631 }
 632 #endif /* DCACHE_ALIASING_POSSIBLE */
 633
 634 /* If not locked, zap it. */
 635 void __flush_tlb_all(void)
 636 {
 637         unsigned long pstate;
 638         int i;
 639
 640         __asm__ __volatile__("flushw\n\t"
 641                              "rdpr      %%pstate, %0\n\t"
 642                              "wrpr      %0, %1, %%pstate"
 643                              : "=r" (pstate)
 644                              : "i" (PSTATE_IE));
 645         if (tlb_type == spitfire) {
 646                 for (i = 0; i < 64; i++) {
 647                         /* Spitfire Errata #32 workaround */
 648                         /* NOTE: Always runs on spitfire, so no
 649                          *       cheetah+ page size encodings.
 650                          */
 651                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 652                                              "flush     %%g6"
 653                                              : /* No outputs */
 654                                              : "r" (0),
 655                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 656
 657                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
 658                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 659                                                      "membar #Sync"
 660                                                      : /* no outputs */
 661                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 662                                 spitfire_put_dtlb_data(i, 0x0UL);
 663                         }
 664
 665                         /* Spitfire Errata #32 workaround */
 666                         /* NOTE: Always runs on spitfire, so no
 667                          *       cheetah+ page size encodings.
 668                          */
 669                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 670                                              "flush     %%g6"
 671                                              : /* No outputs */
 672                                              : "r" (0),
 673                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 674
 675                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
 676                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 677                                                      "membar #Sync"
 678                                                      : /* no outputs */
 679                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 680                                 spitfire_put_itlb_data(i, 0x0UL);
 681                         }
 682                 }
 683         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 684                 cheetah_flush_dtlb_all();
 685                 cheetah_flush_itlb_all();
 686         }
 687         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 688                              : : "r" (pstate));
 689 }
 690
 691 /* Caller does TLB context flushing on local CPU if necessary.
 692  * The caller also ensures that CTX_VALID(mm->context) is false.
 693  *
 694  * We must be careful about boundary cases so that we never
 695  * let the user have CTX 0 (nucleus) or we ever use a CTX
 696  * version of zero (and thus NO_CONTEXT would not be caught
 697  * by version mis-match tests in mmu_context.h).
 698  */
 699 void get_new_mmu_context(struct mm_struct *mm)
 700 {
 701         unsigned long ctx, new_ctx;
 702         unsigned long orig_pgsz_bits;
 703
 704
 705         spin_lock(&ctx_alloc_lock);
 706         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 707         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 708         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 709         if (new_ctx >= (1 << CTX_NR_BITS)) {
 710                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 711                 if (new_ctx >= ctx) {
 712                         int i;
 713                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 714                                 CTX_FIRST_VERSION;
 715                         if (new_ctx == 1)
 716                                 new_ctx = CTX_FIRST_VERSION;
 717
 718                         /* Don't call memset, for 16 entries that's just
 719                          * plain silly...
 720                          */
 721                         mmu_context_bmap[0] = 3;
 722                         mmu_context_bmap[1] = 0;
 723                         mmu_context_bmap[2] = 0;
 724                         mmu_context_bmap[3] = 0;
 725                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 726                                 mmu_context_bmap[i + 0] = 0;
 727                                 mmu_context_bmap[i + 1] = 0;
 728                                 mmu_context_bmap[i + 2] = 0;
 729                                 mmu_context_bmap[i + 3] = 0;
 730                         }
 731                         goto out;
 732                 }
 733         }
 734         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 735         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 736 out:
 737         tlb_context_cache = new_ctx;
 738         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 739         spin_unlock(&ctx_alloc_lock);
 740 }
 741
 742 void sparc_ultra_dump_itlb(void)
 743 {
 744         int slot;
 745
 746         if (tlb_type == spitfire) {
 747                 printk ("Contents of itlb: ");
 748                 for (slot = 0; slot < 14; slot++) printk ("    ");
 749                 printk ("%2x:%016lx,%016lx\n",
 750                         0,
 751                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
 752                 for (slot = 1; slot < 64; slot+=3) {
 753                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 754                                 slot,
 755                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
 756                                 slot+1,
 757                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
 758                                 slot+2,
 759                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
 760                 }
 761         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 762                 printk ("Contents of itlb0:\n");
 763                 for (slot = 0; slot < 16; slot+=2) {
 764                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 765                                 slot,
 766                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
 767                                 slot+1,
 768                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
 769                 }
 770                 printk ("Contents of itlb2:\n");
 771                 for (slot = 0; slot < 128; slot+=2) {
 772                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 773                                 slot,
 774                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
 775                                 slot+1,
 776                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
 777                 }
 778         }
 779 }
 780
 781 void sparc_ultra_dump_dtlb(void)
 782 {
 783         int slot;
 784
 785         if (tlb_type == spitfire) {
 786                 printk ("Contents of dtlb: ");
 787                 for (slot = 0; slot < 14; slot++) printk ("    ");
 788                 printk ("%2x:%016lx,%016lx\n", 0,
 789                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
 790                 for (slot = 1; slot < 64; slot+=3) {
 791                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 792                                 slot,
 793                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
 794                                 slot+1,
 795                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
 796                                 slot+2,
 797                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
 798                 }
 799         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 800                 printk ("Contents of dtlb0:\n");
 801                 for (slot = 0; slot < 16; slot+=2) {
 802                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 803                                 slot,
 804                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
 805                                 slot+1,
 806                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
 807                 }
 808                 printk ("Contents of dtlb2:\n");
 809                 for (slot = 0; slot < 512; slot+=2) {
 810                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 811                                 slot,
 812                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
 813                                 slot+1,
 814                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
 815                 }
 816                 if (tlb_type == cheetah_plus) {
 817                         printk ("Contents of dtlb3:\n");
 818                         for (slot = 0; slot < 512; slot+=2) {
 819                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 820                                         slot,
 821                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
 822                                         slot+1,
 823                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
 824                         }
 825                 }
 826         }
 827 }
 828
 829 extern unsigned long cmdline_memory_size;
 830
 831 unsigned long __init bootmem_init(unsigned long *pages_avail)
 832 {
 833         unsigned long bootmap_size, start_pfn, end_pfn;
 834         unsigned long end_of_phys_memory = 0UL;
 835         unsigned long bootmap_pfn, bytes_avail, size;
 836         int i;
 837
 838 #ifdef CONFIG_DEBUG_BOOTMEM
 839         prom_printf("bootmem_init: Scan pavail, ");
 840 #endif
 841
 842         bytes_avail = 0UL;
 843         for (i = 0; i < pavail_ents; i++) {
 844                 end_of_phys_memory = pavail[i].phys_addr +
 845                         pavail[i].reg_size;
 846                 bytes_avail += pavail[i].reg_size;
 847                 if (cmdline_memory_size) {
 848                         if (bytes_avail > cmdline_memory_size) {
 849                                 unsigned long slack = bytes_avail - cmdline_memory_size;
 850
 851                                 bytes_avail -= slack;
 852                                 end_of_phys_memory -= slack;
 853
 854                                 pavail[i].reg_size -= slack;
 855                                 if ((long)pavail[i].reg_size <= 0L) {
 856                                         pavail[i].phys_addr = 0xdeadbeefUL;
 857                                         pavail[i].reg_size = 0UL;
 858                                         pavail_ents = i;
 859                                 } else {
 860                                         pavail[i+1].reg_size = 0Ul;
 861                                         pavail[i+1].phys_addr = 0xdeadbeefUL;
 862                                         pavail_ents = i + 1;
 863                                 }
 864                                 break;
 865                         }
 866                 }
 867         }
 868
 869         *pages_avail = bytes_avail >> PAGE_SHIFT;
 870
 871         /* Start with page aligned address of last symbol in kernel
 872          * image.  The kernel is hard mapped below PAGE_OFFSET in a
 873          * 4MB locked TLB translation.
 874          */
 875         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
 876
 877         bootmap_pfn = start_pfn;
 878
 879         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
 880
 881 #ifdef CONFIG_BLK_DEV_INITRD
 882         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
 883         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 884                 unsigned long ramdisk_image = sparc_ramdisk_image ?
 885                         sparc_ramdisk_image : sparc_ramdisk_image64;
 886                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
 887                         ramdisk_image -= KERNBASE;
 888                 initrd_start = ramdisk_image + phys_base;
 889                 initrd_end = initrd_start + sparc_ramdisk_size;
 890                 if (initrd_end > end_of_phys_memory) {
 891                         printk(KERN_CRIT "initrd extends beyond end of memory "
 892                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
 893                                initrd_end, end_of_phys_memory);
 894                         initrd_start = 0;
 895                 }
 896                 if (initrd_start) {
 897                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
 898                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
 899                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
 900                 }
 901         }
 902 #endif
 903         /* Initialize the boot-time allocator. */
 904         max_pfn = max_low_pfn = end_pfn;
 905         min_low_pfn = pfn_base;
 906
 907 #ifdef CONFIG_DEBUG_BOOTMEM
 908         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
 909                     min_low_pfn, bootmap_pfn, max_low_pfn);
 910 #endif
 911         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
 912
 913         /* Now register the available physical memory with the
 914          * allocator.
 915          */
 916         for (i = 0; i < pavail_ents; i++) {
 917 #ifdef CONFIG_DEBUG_BOOTMEM
 918                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
 919                             i, pavail[i].phys_addr, pavail[i].reg_size);
 920 #endif
 921                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
 922         }
 923
 924 #ifdef CONFIG_BLK_DEV_INITRD
 925         if (initrd_start) {
 926                 size = initrd_end - initrd_start;
 927
 928                 /* Resert the initrd image area. */
 929 #ifdef CONFIG_DEBUG_BOOTMEM
 930                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
 931                         initrd_start, initrd_end);
 932 #endif
 933                 reserve_bootmem(initrd_start, size);
 934                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
 935
 936                 initrd_start += PAGE_OFFSET;
 937                 initrd_end += PAGE_OFFSET;
 938         }
 939 #endif
 940         /* Reserve the kernel text/data/bss. */
 941 #ifdef CONFIG_DEBUG_BOOTMEM
 942         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
 943 #endif
 944         reserve_bootmem(kern_base, kern_size);
 945         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
 946
 947         /* Reserve the bootmem map.   We do not account for it
 948          * in pages_avail because we will release that memory
 949          * in free_all_bootmem.
 950          */
 951         size = bootmap_size;
 952 #ifdef CONFIG_DEBUG_BOOTMEM
 953         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
 954                     (bootmap_pfn << PAGE_SHIFT), size);
 955 #endif
 956         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
 957         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
 958
 959         return end_pfn;
 960 }
 961
 962 #ifdef CONFIG_DEBUG_PAGEALLOC
 963 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
 964 {
 965         unsigned long vstart = PAGE_OFFSET + pstart;
 966         unsigned long vend = PAGE_OFFSET + pend;
 967         unsigned long alloc_bytes = 0UL;
 968
 969         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
 970                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
 971                             vstart, vend);
 972                 prom_halt();
 973         }
 974
 975         while (vstart < vend) {
 976                 unsigned long this_end, paddr = __pa(vstart);
 977                 pgd_t *pgd = pgd_offset_k(vstart);
 978                 pud_t *pud;
 979                 pmd_t *pmd;
 980                 pte_t *pte;
 981
 982                 pud = pud_offset(pgd, vstart);
 983                 if (pud_none(*pud)) {
 984                         pmd_t *new;
 985
 986                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
 987                         alloc_bytes += PAGE_SIZE;
 988                         pud_populate(&init_mm, pud, new);
 989                 }
 990
 991                 pmd = pmd_offset(pud, vstart);
 992                 if (!pmd_present(*pmd)) {
 993                         pte_t *new;
 994
 995                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
 996                         alloc_bytes += PAGE_SIZE;
 997                         pmd_populate_kernel(&init_mm, pmd, new);
 998                 }
 999
1000                 pte = pte_offset_kernel(pmd, vstart);
1001                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1002                 if (this_end > vend)
1003                         this_end = vend;
1004
1005                 while (vstart < this_end) {
1006                         pte_val(*pte) = (paddr | pgprot_val(prot));
1007
1008                         vstart += PAGE_SIZE;
1009                         paddr += PAGE_SIZE;
1010                         pte++;
1011                 }
1012         }
1013
1014         return alloc_bytes;
1015 }
1016
1017 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1018 static int pall_ents __initdata;
1019
1020 extern unsigned int kvmap_linear_patch[1];
1021
1022 static void __init kernel_physical_mapping_init(void)
1023 {
1024         unsigned long i, mem_alloced = 0UL;
1025
1026         read_obp_memory("reg", &pall[0], &pall_ents);
1027
1028         for (i = 0; i < pall_ents; i++) {
1029                 unsigned long phys_start, phys_end;
1030
1031                 phys_start = pall[i].phys_addr;
1032                 phys_end = phys_start + pall[i].reg_size;
1033                 mem_alloced += kernel_map_range(phys_start, phys_end,
1034                                                 PAGE_KERNEL);
1035         }
1036
1037         printk("Allocated %ld bytes for kernel page tables.\n",
1038                mem_alloced);
1039
1040         kvmap_linear_patch[0] = 0x01000000; /* nop */
1041         flushi(&kvmap_linear_patch[0]);
1042
1043         __flush_tlb_all();
1044 }
1045
1046 void kernel_map_pages(struct page *page, int numpages, int enable)
1047 {
1048         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1049         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1050
1051         kernel_map_range(phys_start, phys_end,
1052                          (enable ? PAGE_KERNEL : __pgprot(0)));
1053
1054         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1055                                PAGE_OFFSET + phys_end);
1056
1057         /* we should perform an IPI and flush all tlbs,
1058          * but that can deadlock->flush only current cpu.
1059          */
1060         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1061                                  PAGE_OFFSET + phys_end);
1062 }
1063 #endif
1064
1065 unsigned long __init find_ecache_flush_span(unsigned long size)
1066 {
1067         int i;
1068
1069         for (i = 0; i < pavail_ents; i++) {
1070                 if (pavail[i].reg_size >= size)
1071                         return pavail[i].phys_addr;
1072         }
1073
1074         return ~0UL;
1075 }
1076
1077 static void __init tsb_phys_patch(void)
1078 {
1079         struct tsb_ldquad_phys_patch_entry *pquad;
1080         struct tsb_phys_patch_entry *p;
1081
1082         pquad = &__tsb_ldquad_phys_patch;
1083         while (pquad < &__tsb_ldquad_phys_patch_end) {
1084                 unsigned long addr = pquad->addr;
1085
1086                 if (tlb_type == hypervisor)
1087                         *(unsigned int *) addr = pquad->sun4v_insn;
1088                 else
1089                         *(unsigned int *) addr = pquad->sun4u_insn;
1090                 wmb();
1091                 __asm__ __volatile__("flush     %0"
1092                                      : /* no outputs */
1093                                      : "r" (addr));
1094
1095                 pquad++;
1096         }
1097
1098         p = &__tsb_phys_patch;
1099         while (p < &__tsb_phys_patch_end) {
1100                 unsigned long addr = p->addr;
1101
1102                 *(unsigned int *) addr = p->insn;
1103                 wmb();
1104                 __asm__ __volatile__("flush     %0"
1105                                      : /* no outputs */
1106                                      : "r" (addr));
1107
1108                 p++;
1109         }
1110 }
1111
1112 /* paging_init() sets up the page tables */
1113
1114 extern void cheetah_ecache_flush_init(void);
1115 extern void sun4v_patch_tlb_handlers(void);
1116
1117 static unsigned long last_valid_pfn;
1118 pgd_t swapper_pg_dir[2048];
1119
1120 void __init paging_init(void)
1121 {
1122         unsigned long end_pfn, pages_avail, shift;
1123         unsigned long real_end, i;
1124
1125         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1126         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1127
1128         if (tlb_type == cheetah_plus ||
1129             tlb_type == hypervisor)
1130                 tsb_phys_patch();
1131
1132         if (tlb_type == hypervisor)
1133                 sun4v_patch_tlb_handlers();
1134
1135         /* Find available physical memory... */
1136         read_obp_memory("available", &pavail[0], &pavail_ents);
1137
1138         phys_base = 0xffffffffffffffffUL;
1139         for (i = 0; i < pavail_ents; i++)
1140                 phys_base = min(phys_base, pavail[i].phys_addr);
1141
1142         pfn_base = phys_base >> PAGE_SHIFT;
1143
1144         set_bit(0, mmu_context_bmap);
1145
1146         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1147
1148         real_end = (unsigned long)_end;
1149         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1150                 bigkernel = 1;
1151         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1152                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1153                 prom_halt();
1154         }
1155
1156         /* Set kernel pgd to upper alias so physical page computations
1157          * work.
1158          */
1159         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1160
1161         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1162
1163         /* Now can init the kernel/bad page tables. */
1164         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1165                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1166
1167         inherit_prom_mappings();
1168
1169         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1170         setup_tba();
1171
1172         __flush_tlb_all();
1173
1174         /* Setup bootmem... */
1175         pages_avail = 0;
1176         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1177
1178 #ifdef CONFIG_DEBUG_PAGEALLOC
1179         kernel_physical_mapping_init();
1180 #endif
1181
1182         {
1183                 unsigned long zones_size[MAX_NR_ZONES];
1184                 unsigned long zholes_size[MAX_NR_ZONES];
1185                 unsigned long npages;
1186                 int znum;
1187
1188                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1189                         zones_size[znum] = zholes_size[znum] = 0;
1190
1191                 npages = end_pfn - pfn_base;
1192                 zones_size[ZONE_DMA] = npages;
1193                 zholes_size[ZONE_DMA] = npages - pages_avail;
1194
1195                 free_area_init_node(0, &contig_page_data, zones_size,
1196                                     phys_base >> PAGE_SHIFT, zholes_size);
1197         }
1198
1199         device_scan();
1200 }
1201
1202 static void __init taint_real_pages(void)
1203 {
1204         int i;
1205
1206         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1207
1208         /* Find changes discovered in the physmem available rescan and
1209          * reserve the lost portions in the bootmem maps.
1210          */
1211         for (i = 0; i < pavail_ents; i++) {
1212                 unsigned long old_start, old_end;
1213
1214                 old_start = pavail[i].phys_addr;
1215                 old_end = old_start +
1216                         pavail[i].reg_size;
1217                 while (old_start < old_end) {
1218                         int n;
1219
1220                         for (n = 0; pavail_rescan_ents; n++) {
1221                                 unsigned long new_start, new_end;
1222
1223                                 new_start = pavail_rescan[n].phys_addr;
1224                                 new_end = new_start +
1225                                         pavail_rescan[n].reg_size;
1226
1227                                 if (new_start <= old_start &&
1228                                     new_end >= (old_start + PAGE_SIZE)) {
1229                                         set_bit(old_start >> 22,
1230                                                 sparc64_valid_addr_bitmap);
1231                                         goto do_next_page;
1232                                 }
1233                         }
1234                         reserve_bootmem(old_start, PAGE_SIZE);
1235
1236                 do_next_page:
1237                         old_start += PAGE_SIZE;
1238                 }
1239         }
1240 }
1241
1242 void __init mem_init(void)
1243 {
1244         unsigned long codepages, datapages, initpages;
1245         unsigned long addr, last;
1246         int i;
1247
1248         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1249         i += 1;
1250         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1251         if (sparc64_valid_addr_bitmap == NULL) {
1252                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1253                 prom_halt();
1254         }
1255         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1256
1257         addr = PAGE_OFFSET + kern_base;
1258         last = PAGE_ALIGN(kern_size) + addr;
1259         while (addr < last) {
1260                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1261                 addr += PAGE_SIZE;
1262         }
1263
1264         taint_real_pages();
1265
1266         max_mapnr = last_valid_pfn - pfn_base;
1267         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1268
1269 #ifdef CONFIG_DEBUG_BOOTMEM
1270         prom_printf("mem_init: Calling free_all_bootmem().\n");
1271 #endif
1272         totalram_pages = num_physpages = free_all_bootmem() - 1;
1273
1274         /*
1275          * Set up the zero page, mark it reserved, so that page count
1276          * is not manipulated when freeing the page from user ptes.
1277          */
1278         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1279         if (mem_map_zero == NULL) {
1280                 prom_printf("paging_init: Cannot alloc zero page.\n");
1281                 prom_halt();
1282         }
1283         SetPageReserved(mem_map_zero);
1284
1285         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1286         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1287         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1288         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1289         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1290         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1291
1292         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1293                nr_free_pages() << (PAGE_SHIFT-10),
1294                codepages << (PAGE_SHIFT-10),
1295                datapages << (PAGE_SHIFT-10),
1296                initpages << (PAGE_SHIFT-10),
1297                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1298
1299         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1300                 cheetah_ecache_flush_init();
1301 }
1302
1303 void free_initmem(void)
1304 {
1305         unsigned long addr, initend;
1306
1307         /*
1308          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1309          */
1310         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1311         initend = (unsigned long)(__init_end) & PAGE_MASK;
1312         for (; addr < initend; addr += PAGE_SIZE) {
1313                 unsigned long page;
1314                 struct page *p;
1315
1316                 page = (addr +
1317                         ((unsigned long) __va(kern_base)) -
1318                         ((unsigned long) KERNBASE));
1319                 memset((void *)addr, 0xcc, PAGE_SIZE);
1320                 p = virt_to_page(page);
1321
1322                 ClearPageReserved(p);
1323                 set_page_count(p, 1);
1324                 __free_page(p);
1325                 num_physpages++;
1326                 totalram_pages++;
1327         }
1328 }
1329
1330 #ifdef CONFIG_BLK_DEV_INITRD
1331 void free_initrd_mem(unsigned long start, unsigned long end)
1332 {
1333         if (start < end)
1334                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1335         for (; start < end; start += PAGE_SIZE) {
1336                 struct page *p = virt_to_page(start);
1337
1338                 ClearPageReserved(p);
1339                 set_page_count(p, 1);
1340                 __free_page(p);
1341                 num_physpages++;
1342                 totalram_pages++;
1343         }
1344 }
1345 #endif