1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
27 #include <asm/system.h>
29 #include <asm/pgalloc.h>
30 #include <asm/pgtable.h>
31 #include <asm/oplib.h>
32 #include <asm/iommu.h>
34 #include <asm/uaccess.h>
35 #include <asm/mmu_context.h>
36 #include <asm/tlbflush.h>
38 #include <asm/starfire.h>
40 #include <asm/spitfire.h>
41 #include <asm/sections.h>
43 extern void device_scan(void);
47 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
48 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
49 static int pavail_ents __initdata;
50 static int pavail_rescan_ents __initdata;
52 static int cmp_p64(const void *a, const void *b)
54 const struct linux_prom64_registers *x = a, *y = b;
56 if (x->phys_addr > y->phys_addr)
58 if (x->phys_addr < y->phys_addr)
63 static void __init read_obp_memory(const char *property,
64 struct linux_prom64_registers *regs,
67 int node = prom_finddevice("/memory");
68 int prop_size = prom_getproplen(node, property);
71 ents = prop_size / sizeof(struct linux_prom64_registers);
72 if (ents > MAX_BANKS) {
73 prom_printf("The machine has more %s property entries than "
74 "this kernel can support (%d).\n",
79 ret = prom_getproperty(node, property, (char *) regs, prop_size);
81 prom_printf("Couldn't get %s property from /memory.\n");
87 /* Sanitize what we got from the firmware, by page aligning
90 for (i = 0; i < ents; i++) {
91 unsigned long base, size;
93 base = regs[i].phys_addr;
94 size = regs[i].reg_size;
97 if (base & ~PAGE_MASK) {
98 unsigned long new_base = PAGE_ALIGN(base);
100 size -= new_base - base;
101 if ((long) size < 0L)
105 regs[i].phys_addr = base;
106 regs[i].reg_size = size;
108 sort(regs, ents, sizeof(struct linux_prom64_registers),
112 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
114 /* Ugly, but necessary... -DaveM */
115 unsigned long phys_base __read_mostly;
116 unsigned long kern_base __read_mostly;
117 unsigned long kern_size __read_mostly;
118 unsigned long pfn_base __read_mostly;
120 /* get_new_mmu_context() uses "cache + 1". */
121 DEFINE_SPINLOCK(ctx_alloc_lock);
122 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
123 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
124 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
126 /* References to special section boundaries */
127 extern char _start[], _end[];
129 /* Initial ramdisk setup */
130 extern unsigned long sparc_ramdisk_image64;
131 extern unsigned int sparc_ramdisk_image;
132 extern unsigned int sparc_ramdisk_size;
134 struct page *mem_map_zero __read_mostly;
136 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
138 unsigned long sparc64_kern_pri_context __read_mostly;
139 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
140 unsigned long sparc64_kern_sec_context __read_mostly;
144 /* XXX Tune this... */
145 #define PGT_CACHE_LOW 25
146 #define PGT_CACHE_HIGH 50
149 struct pgtable_cache_struct pgt_quicklists;
152 void check_pgt_cache(void)
155 if (pgtable_cache_size > PGT_CACHE_HIGH) {
158 free_pgd_slow(get_pgd_fast());
160 free_pte_slow(pte_alloc_one_fast());
161 } while (pgtable_cache_size > PGT_CACHE_LOW);
166 #ifdef CONFIG_DEBUG_DCFLUSH
167 atomic_t dcpage_flushes = ATOMIC_INIT(0);
169 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
173 __inline__ void flush_dcache_page_impl(struct page *page)
175 #ifdef CONFIG_DEBUG_DCFLUSH
176 atomic_inc(&dcpage_flushes);
179 #ifdef DCACHE_ALIASING_POSSIBLE
180 __flush_dcache_page(page_address(page),
181 ((tlb_type == spitfire) &&
182 page_mapping(page) != NULL));
184 if (page_mapping(page) != NULL &&
185 tlb_type == spitfire)
186 __flush_icache_page(__pa(page_address(page)));
190 #define PG_dcache_dirty PG_arch_1
191 #define PG_dcache_cpu_shift 24
192 #define PG_dcache_cpu_mask (256 - 1)
195 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
198 #define dcache_dirty_cpu(page) \
199 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
201 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
203 unsigned long mask = this_cpu;
204 unsigned long non_cpu_bits;
206 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
207 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
209 __asm__ __volatile__("1:\n\t"
211 "and %%g7, %1, %%g1\n\t"
212 "or %%g1, %0, %%g1\n\t"
213 "casx [%2], %%g7, %%g1\n\t"
215 "membar #StoreLoad | #StoreStore\n\t"
216 "bne,pn %%xcc, 1b\n\t"
219 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
225 unsigned long mask = (1UL << PG_dcache_dirty);
227 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
230 "srlx %%g7, %4, %%g1\n\t"
231 "and %%g1, %3, %%g1\n\t"
233 "bne,pn %%icc, 2f\n\t"
234 " andn %%g7, %1, %%g1\n\t"
235 "casx [%2], %%g7, %%g1\n\t"
237 "membar #StoreLoad | #StoreStore\n\t"
238 "bne,pn %%xcc, 1b\n\t"
242 : "r" (cpu), "r" (mask), "r" (&page->flags),
243 "i" (PG_dcache_cpu_mask),
244 "i" (PG_dcache_cpu_shift)
248 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
252 unsigned long pg_flags;
255 if (pfn_valid(pfn) &&
256 (page = pfn_to_page(pfn), page_mapping(page)) &&
257 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
258 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
260 int this_cpu = get_cpu();
262 /* This is just to optimize away some function calls
266 flush_dcache_page_impl(page);
268 smp_flush_dcache_page_impl(page, cpu);
270 clear_dcache_dirty_cpu(page, cpu);
276 void flush_dcache_page(struct page *page)
278 struct address_space *mapping;
281 /* Do not bother with the expensive D-cache flush if it
282 * is merely the zero page. The 'bigcore' testcase in GDB
283 * causes this case to run millions of times.
285 if (page == ZERO_PAGE(0))
288 this_cpu = get_cpu();
290 mapping = page_mapping(page);
291 if (mapping && !mapping_mapped(mapping)) {
292 int dirty = test_bit(PG_dcache_dirty, &page->flags);
294 int dirty_cpu = dcache_dirty_cpu(page);
296 if (dirty_cpu == this_cpu)
298 smp_flush_dcache_page_impl(page, dirty_cpu);
300 set_dcache_dirty(page, this_cpu);
302 /* We could delay the flush for the !page_mapping
303 * case too. But that case is for exec env/arg
304 * pages and those are %99 certainly going to get
305 * faulted into the tlb (and thus flushed) anyways.
307 flush_dcache_page_impl(page);
314 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
316 /* Cheetah has coherent I-cache. */
317 if (tlb_type == spitfire) {
320 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
321 __flush_icache_page(__get_phys(kaddr));
325 unsigned long page_to_pfn(struct page *page)
327 return (unsigned long) ((page - mem_map) + pfn_base);
330 struct page *pfn_to_page(unsigned long pfn)
332 return (mem_map + (pfn - pfn_base));
337 printk("Mem-info:\n");
339 printk("Free swap: %6ldkB\n",
340 nr_swap_pages << (PAGE_SHIFT-10));
341 printk("%ld pages of RAM\n", num_physpages);
342 printk("%d free pages\n", nr_free_pages());
343 printk("%d pages in page table cache\n",pgtable_cache_size);
346 void mmu_info(struct seq_file *m)
348 if (tlb_type == cheetah)
349 seq_printf(m, "MMU Type\t: Cheetah\n");
350 else if (tlb_type == cheetah_plus)
351 seq_printf(m, "MMU Type\t: Cheetah+\n");
352 else if (tlb_type == spitfire)
353 seq_printf(m, "MMU Type\t: Spitfire\n");
355 seq_printf(m, "MMU Type\t: ???\n");
357 #ifdef CONFIG_DEBUG_DCFLUSH
358 seq_printf(m, "DCPageFlushes\t: %d\n",
359 atomic_read(&dcpage_flushes));
361 seq_printf(m, "DCPageFlushesXC\t: %d\n",
362 atomic_read(&dcpage_flushes_xcall));
363 #endif /* CONFIG_SMP */
364 #endif /* CONFIG_DEBUG_DCFLUSH */
367 struct linux_prom_translation {
373 /* Exported for kernel TLB miss handling in ktlb.S */
374 struct linux_prom_translation prom_trans[512] __read_mostly;
375 unsigned int prom_trans_ents __read_mostly;
376 unsigned int swapper_pgd_zero __read_mostly;
378 extern unsigned long prom_boot_page;
379 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
380 extern int prom_get_mmu_ihandle(void);
381 extern void register_prom_callbacks(void);
383 /* Exported for SMP bootup purposes. */
384 unsigned long kern_locked_tte_data;
387 * Translate PROM's mapping we capture at boot time into physical address.
388 * The second parameter is only set from prom_callback() invocations.
390 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
394 for (i = 0; i < prom_trans_ents; i++) {
395 struct linux_prom_translation *p = &prom_trans[i];
397 if (promva >= p->virt &&
398 promva < (p->virt + p->size)) {
399 unsigned long base = p->data & _PAGE_PADDR;
403 return base + (promva & (8192 - 1));
411 /* The obp translations are saved based on 8k pagesize, since obp can
412 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
413 * HI_OBP_ADDRESS range are handled in ktlb.S.
415 static inline int in_obp_range(unsigned long vaddr)
417 return (vaddr >= LOW_OBP_ADDRESS &&
418 vaddr < HI_OBP_ADDRESS);
421 static int cmp_ptrans(const void *a, const void *b)
423 const struct linux_prom_translation *x = a, *y = b;
425 if (x->virt > y->virt)
427 if (x->virt < y->virt)
432 /* Read OBP translations property into 'prom_trans[]'. */
433 static void __init read_obp_translations(void)
435 int n, node, ents, first, last, i;
437 node = prom_finddevice("/virtual-memory");
438 n = prom_getproplen(node, "translations");
439 if (unlikely(n == 0 || n == -1)) {
440 prom_printf("prom_mappings: Couldn't get size.\n");
443 if (unlikely(n > sizeof(prom_trans))) {
444 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
448 if ((n = prom_getproperty(node, "translations",
449 (char *)&prom_trans[0],
450 sizeof(prom_trans))) == -1) {
451 prom_printf("prom_mappings: Couldn't get property.\n");
455 n = n / sizeof(struct linux_prom_translation);
459 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
462 /* Now kick out all the non-OBP entries. */
463 for (i = 0; i < ents; i++) {
464 if (in_obp_range(prom_trans[i].virt))
468 for (; i < ents; i++) {
469 if (!in_obp_range(prom_trans[i].virt))
474 for (i = 0; i < (last - first); i++) {
475 struct linux_prom_translation *src = &prom_trans[i + first];
476 struct linux_prom_translation *dest = &prom_trans[i];
480 for (; i < ents; i++) {
481 struct linux_prom_translation *dest = &prom_trans[i];
482 dest->virt = dest->size = dest->data = 0x0UL;
485 prom_trans_ents = last - first;
487 if (tlb_type == spitfire) {
488 /* Clear diag TTE bits. */
489 for (i = 0; i < prom_trans_ents; i++)
490 prom_trans[i].data &= ~0x0003fe0000000000UL;
494 static void __init remap_kernel(void)
496 unsigned long phys_page, tte_vaddr, tte_data;
497 int tlb_ent = sparc64_highest_locked_tlbent();
499 tte_vaddr = (unsigned long) KERNBASE;
500 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
501 tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
502 _PAGE_CP | _PAGE_CV | _PAGE_P |
505 kern_locked_tte_data = tte_data;
507 /* Now lock us into the TLBs via OBP. */
508 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
509 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
512 prom_dtlb_load(tlb_ent,
514 tte_vaddr + 0x400000);
515 prom_itlb_load(tlb_ent,
517 tte_vaddr + 0x400000);
519 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
520 if (tlb_type == cheetah_plus) {
521 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
522 CTX_CHEETAH_PLUS_NUC);
523 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
524 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
529 static void __init inherit_prom_mappings(void)
531 read_obp_translations();
533 /* Now fixup OBP's idea about where we really are mapped. */
534 prom_printf("Remapping the kernel... ");
536 prom_printf("done.\n");
538 prom_printf("Registering callbacks... ");
539 register_prom_callbacks();
540 prom_printf("done.\n");
543 static int prom_ditlb_set;
544 struct prom_tlb_entry {
546 unsigned long tlb_tag;
547 unsigned long tlb_data;
549 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
551 void prom_world(int enter)
553 unsigned long pstate;
557 set_fs((mm_segment_t) { get_thread_current_ds() });
562 /* Make sure the following runs atomically. */
563 __asm__ __volatile__("flushw\n\t"
564 "rdpr %%pstate, %0\n\t"
565 "wrpr %0, %1, %%pstate"
570 /* Install PROM world. */
571 for (i = 0; i < 16; i++) {
572 if (prom_dtlb[i].tlb_ent != -1) {
573 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
575 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
577 if (tlb_type == spitfire)
578 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
579 prom_dtlb[i].tlb_data);
580 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
581 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
582 prom_dtlb[i].tlb_data);
584 if (prom_itlb[i].tlb_ent != -1) {
585 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
587 : : "r" (prom_itlb[i].tlb_tag),
588 "r" (TLB_TAG_ACCESS),
590 if (tlb_type == spitfire)
591 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
592 prom_itlb[i].tlb_data);
593 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
594 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
595 prom_itlb[i].tlb_data);
599 for (i = 0; i < 16; i++) {
600 if (prom_dtlb[i].tlb_ent != -1) {
601 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
603 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
604 if (tlb_type == spitfire)
605 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
607 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
609 if (prom_itlb[i].tlb_ent != -1) {
610 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
612 : : "r" (TLB_TAG_ACCESS),
614 if (tlb_type == spitfire)
615 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
617 cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
621 __asm__ __volatile__("wrpr %0, 0, %%pstate"
625 void inherit_locked_prom_mappings(int save_p)
631 /* Fucking losing PROM has more mappings in the TLB, but
632 * it (conveniently) fails to mention any of these in the
633 * translations property. The only ones that matter are
634 * the locked PROM tlb entries, so we impose the following
635 * irrecovable rule on the PROM, it is allowed 8 locked
636 * entries in the ITLB and 8 in the DTLB.
638 * Supposedly the upper 16GB of the address space is
639 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
640 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
641 * used between the client program and the firmware on sun5
642 * systems to coordinate mmu mappings is also COMPLETELY
643 * UNDOCUMENTED!!!!!! Thanks S(t)un!
646 for (i = 0; i < 16; i++) {
647 prom_itlb[i].tlb_ent = -1;
648 prom_dtlb[i].tlb_ent = -1;
651 if (tlb_type == spitfire) {
652 int high = sparc64_highest_unlocked_tlb_ent;
653 for (i = 0; i <= high; i++) {
656 /* Spitfire Errata #32 workaround */
657 /* NOTE: Always runs on spitfire, so no cheetah+
658 * page size encodings.
660 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
664 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
666 data = spitfire_get_dtlb_data(i);
667 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
670 /* Spitfire Errata #32 workaround */
671 /* NOTE: Always runs on spitfire, so no
672 * cheetah+ page size encodings.
674 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
678 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
680 tag = spitfire_get_dtlb_tag(i);
682 prom_dtlb[dtlb_seen].tlb_ent = i;
683 prom_dtlb[dtlb_seen].tlb_tag = tag;
684 prom_dtlb[dtlb_seen].tlb_data = data;
686 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
688 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
689 spitfire_put_dtlb_data(i, 0x0UL);
697 for (i = 0; i < high; i++) {
700 /* Spitfire Errata #32 workaround */
701 /* NOTE: Always runs on spitfire, so no
702 * cheetah+ page size encodings.
704 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
708 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
710 data = spitfire_get_itlb_data(i);
711 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
714 /* Spitfire Errata #32 workaround */
715 /* NOTE: Always runs on spitfire, so no
716 * cheetah+ page size encodings.
718 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
722 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
724 tag = spitfire_get_itlb_tag(i);
726 prom_itlb[itlb_seen].tlb_ent = i;
727 prom_itlb[itlb_seen].tlb_tag = tag;
728 prom_itlb[itlb_seen].tlb_data = data;
730 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
732 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
733 spitfire_put_itlb_data(i, 0x0UL);
740 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
741 int high = sparc64_highest_unlocked_tlb_ent;
743 for (i = 0; i <= high; i++) {
746 data = cheetah_get_ldtlb_data(i);
747 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
750 tag = cheetah_get_ldtlb_tag(i);
752 prom_dtlb[dtlb_seen].tlb_ent = i;
753 prom_dtlb[dtlb_seen].tlb_tag = tag;
754 prom_dtlb[dtlb_seen].tlb_data = data;
756 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
758 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
759 cheetah_put_ldtlb_data(i, 0x0UL);
767 for (i = 0; i < high; i++) {
770 data = cheetah_get_litlb_data(i);
771 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
774 tag = cheetah_get_litlb_tag(i);
776 prom_itlb[itlb_seen].tlb_ent = i;
777 prom_itlb[itlb_seen].tlb_tag = tag;
778 prom_itlb[itlb_seen].tlb_data = data;
780 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
782 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
783 cheetah_put_litlb_data(i, 0x0UL);
791 /* Implement me :-) */
798 /* Give PROM back his world, done during reboots... */
799 void prom_reload_locked(void)
803 for (i = 0; i < 16; i++) {
804 if (prom_dtlb[i].tlb_ent != -1) {
805 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
807 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
809 if (tlb_type == spitfire)
810 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
811 prom_dtlb[i].tlb_data);
812 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
813 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
814 prom_dtlb[i].tlb_data);
817 if (prom_itlb[i].tlb_ent != -1) {
818 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
820 : : "r" (prom_itlb[i].tlb_tag),
821 "r" (TLB_TAG_ACCESS),
823 if (tlb_type == spitfire)
824 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
825 prom_itlb[i].tlb_data);
827 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
828 prom_itlb[i].tlb_data);
833 #ifdef DCACHE_ALIASING_POSSIBLE
834 void __flush_dcache_range(unsigned long start, unsigned long end)
838 if (tlb_type == spitfire) {
841 for (va = start; va < end; va += 32) {
842 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
849 for (va = start; va < end; va += 32)
850 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
854 "i" (ASI_DCACHE_INVALIDATE));
857 #endif /* DCACHE_ALIASING_POSSIBLE */
859 /* If not locked, zap it. */
860 void __flush_tlb_all(void)
862 unsigned long pstate;
865 __asm__ __volatile__("flushw\n\t"
866 "rdpr %%pstate, %0\n\t"
867 "wrpr %0, %1, %%pstate"
870 if (tlb_type == spitfire) {
871 for (i = 0; i < 64; i++) {
872 /* Spitfire Errata #32 workaround */
873 /* NOTE: Always runs on spitfire, so no
874 * cheetah+ page size encodings.
876 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
880 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
882 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
883 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
886 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
887 spitfire_put_dtlb_data(i, 0x0UL);
890 /* Spitfire Errata #32 workaround */
891 /* NOTE: Always runs on spitfire, so no
892 * cheetah+ page size encodings.
894 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
898 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
900 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
901 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
904 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
905 spitfire_put_itlb_data(i, 0x0UL);
908 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
909 cheetah_flush_dtlb_all();
910 cheetah_flush_itlb_all();
912 __asm__ __volatile__("wrpr %0, 0, %%pstate"
916 /* Caller does TLB context flushing on local CPU if necessary.
917 * The caller also ensures that CTX_VALID(mm->context) is false.
919 * We must be careful about boundary cases so that we never
920 * let the user have CTX 0 (nucleus) or we ever use a CTX
921 * version of zero (and thus NO_CONTEXT would not be caught
922 * by version mis-match tests in mmu_context.h).
924 void get_new_mmu_context(struct mm_struct *mm)
926 unsigned long ctx, new_ctx;
927 unsigned long orig_pgsz_bits;
930 spin_lock(&ctx_alloc_lock);
931 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
932 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
933 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
934 if (new_ctx >= (1 << CTX_NR_BITS)) {
935 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
936 if (new_ctx >= ctx) {
938 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
941 new_ctx = CTX_FIRST_VERSION;
943 /* Don't call memset, for 16 entries that's just
946 mmu_context_bmap[0] = 3;
947 mmu_context_bmap[1] = 0;
948 mmu_context_bmap[2] = 0;
949 mmu_context_bmap[3] = 0;
950 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
951 mmu_context_bmap[i + 0] = 0;
952 mmu_context_bmap[i + 1] = 0;
953 mmu_context_bmap[i + 2] = 0;
954 mmu_context_bmap[i + 3] = 0;
959 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
960 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
962 tlb_context_cache = new_ctx;
963 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
964 spin_unlock(&ctx_alloc_lock);
967 void sparc_ultra_dump_itlb(void)
971 if (tlb_type == spitfire) {
972 printk ("Contents of itlb: ");
973 for (slot = 0; slot < 14; slot++) printk (" ");
974 printk ("%2x:%016lx,%016lx\n",
976 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
977 for (slot = 1; slot < 64; slot+=3) {
978 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
980 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
982 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
984 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
986 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
987 printk ("Contents of itlb0:\n");
988 for (slot = 0; slot < 16; slot+=2) {
989 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
991 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
993 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
995 printk ("Contents of itlb2:\n");
996 for (slot = 0; slot < 128; slot+=2) {
997 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
999 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1001 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1006 void sparc_ultra_dump_dtlb(void)
1010 if (tlb_type == spitfire) {
1011 printk ("Contents of dtlb: ");
1012 for (slot = 0; slot < 14; slot++) printk (" ");
1013 printk ("%2x:%016lx,%016lx\n", 0,
1014 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1015 for (slot = 1; slot < 64; slot+=3) {
1016 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1018 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1020 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1022 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1024 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1025 printk ("Contents of dtlb0:\n");
1026 for (slot = 0; slot < 16; slot+=2) {
1027 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1029 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1031 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1033 printk ("Contents of dtlb2:\n");
1034 for (slot = 0; slot < 512; slot+=2) {
1035 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1037 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1039 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1041 if (tlb_type == cheetah_plus) {
1042 printk ("Contents of dtlb3:\n");
1043 for (slot = 0; slot < 512; slot+=2) {
1044 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1046 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1048 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1054 extern unsigned long cmdline_memory_size;
1056 unsigned long __init bootmem_init(unsigned long *pages_avail)
1058 unsigned long bootmap_size, start_pfn, end_pfn;
1059 unsigned long end_of_phys_memory = 0UL;
1060 unsigned long bootmap_pfn, bytes_avail, size;
1063 #ifdef CONFIG_DEBUG_BOOTMEM
1064 prom_printf("bootmem_init: Scan pavail, ");
1068 for (i = 0; i < pavail_ents; i++) {
1069 end_of_phys_memory = pavail[i].phys_addr +
1071 bytes_avail += pavail[i].reg_size;
1072 if (cmdline_memory_size) {
1073 if (bytes_avail > cmdline_memory_size) {
1074 unsigned long slack = bytes_avail - cmdline_memory_size;
1076 bytes_avail -= slack;
1077 end_of_phys_memory -= slack;
1079 pavail[i].reg_size -= slack;
1080 if ((long)pavail[i].reg_size <= 0L) {
1081 pavail[i].phys_addr = 0xdeadbeefUL;
1082 pavail[i].reg_size = 0UL;
1085 pavail[i+1].reg_size = 0Ul;
1086 pavail[i+1].phys_addr = 0xdeadbeefUL;
1087 pavail_ents = i + 1;
1094 *pages_avail = bytes_avail >> PAGE_SHIFT;
1096 /* Start with page aligned address of last symbol in kernel
1097 * image. The kernel is hard mapped below PAGE_OFFSET in a
1098 * 4MB locked TLB translation.
1100 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1102 bootmap_pfn = start_pfn;
1104 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1106 #ifdef CONFIG_BLK_DEV_INITRD
1107 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1108 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1109 unsigned long ramdisk_image = sparc_ramdisk_image ?
1110 sparc_ramdisk_image : sparc_ramdisk_image64;
1111 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1112 ramdisk_image -= KERNBASE;
1113 initrd_start = ramdisk_image + phys_base;
1114 initrd_end = initrd_start + sparc_ramdisk_size;
1115 if (initrd_end > end_of_phys_memory) {
1116 printk(KERN_CRIT "initrd extends beyond end of memory "
1117 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1118 initrd_end, end_of_phys_memory);
1122 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1123 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1124 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1128 /* Initialize the boot-time allocator. */
1129 max_pfn = max_low_pfn = end_pfn;
1130 min_low_pfn = pfn_base;
1132 #ifdef CONFIG_DEBUG_BOOTMEM
1133 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1134 min_low_pfn, bootmap_pfn, max_low_pfn);
1136 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1138 /* Now register the available physical memory with the
1141 for (i = 0; i < pavail_ents; i++) {
1142 #ifdef CONFIG_DEBUG_BOOTMEM
1143 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
1144 i, pavail[i].phys_addr, pavail[i].reg_size);
1146 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1149 #ifdef CONFIG_BLK_DEV_INITRD
1151 size = initrd_end - initrd_start;
1153 /* Resert the initrd image area. */
1154 #ifdef CONFIG_DEBUG_BOOTMEM
1155 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1156 initrd_start, initrd_end);
1158 reserve_bootmem(initrd_start, size);
1159 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1161 initrd_start += PAGE_OFFSET;
1162 initrd_end += PAGE_OFFSET;
1165 /* Reserve the kernel text/data/bss. */
1166 #ifdef CONFIG_DEBUG_BOOTMEM
1167 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1169 reserve_bootmem(kern_base, kern_size);
1170 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1172 /* Reserve the bootmem map. We do not account for it
1173 * in pages_avail because we will release that memory
1174 * in free_all_bootmem.
1176 size = bootmap_size;
1177 #ifdef CONFIG_DEBUG_BOOTMEM
1178 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1179 (bootmap_pfn << PAGE_SHIFT), size);
1181 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1182 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1187 #ifdef CONFIG_DEBUG_PAGEALLOC
1188 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1190 unsigned long vstart = PAGE_OFFSET + pstart;
1191 unsigned long vend = PAGE_OFFSET + pend;
1192 unsigned long alloc_bytes = 0UL;
1194 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1195 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1200 while (vstart < vend) {
1201 unsigned long this_end, paddr = __pa(vstart);
1202 pgd_t *pgd = pgd_offset_k(vstart);
1207 pud = pud_offset(pgd, vstart);
1208 if (pud_none(*pud)) {
1211 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1212 alloc_bytes += PAGE_SIZE;
1213 pud_populate(&init_mm, pud, new);
1216 pmd = pmd_offset(pud, vstart);
1217 if (!pmd_present(*pmd)) {
1220 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1221 alloc_bytes += PAGE_SIZE;
1222 pmd_populate_kernel(&init_mm, pmd, new);
1225 pte = pte_offset_kernel(pmd, vstart);
1226 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1227 if (this_end > vend)
1230 while (vstart < this_end) {
1231 pte_val(*pte) = (paddr | pgprot_val(prot));
1233 vstart += PAGE_SIZE;
1242 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1243 static int pall_ents __initdata;
1245 extern unsigned int kvmap_linear_patch[1];
1247 static void __init kernel_physical_mapping_init(void)
1249 unsigned long i, mem_alloced = 0UL;
1251 read_obp_memory("reg", &pall[0], &pall_ents);
1253 for (i = 0; i < pall_ents; i++) {
1254 unsigned long phys_start, phys_end;
1256 phys_start = pall[i].phys_addr;
1257 phys_end = phys_start + pall[i].reg_size;
1258 mem_alloced += kernel_map_range(phys_start, phys_end,
1262 printk("Allocated %ld bytes for kernel page tables.\n",
1265 kvmap_linear_patch[0] = 0x01000000; /* nop */
1266 flushi(&kvmap_linear_patch[0]);
1271 void kernel_map_pages(struct page *page, int numpages, int enable)
1273 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1274 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1276 kernel_map_range(phys_start, phys_end,
1277 (enable ? PAGE_KERNEL : __pgprot(0)));
1279 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1280 PAGE_OFFSET + phys_end);
1282 /* we should perform an IPI and flush all tlbs,
1283 * but that can deadlock->flush only current cpu.
1285 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1286 PAGE_OFFSET + phys_end);
1290 unsigned long __init find_ecache_flush_span(unsigned long size)
1294 for (i = 0; i < pavail_ents; i++) {
1295 if (pavail[i].reg_size >= size)
1296 return pavail[i].phys_addr;
1302 /* paging_init() sets up the page tables */
1304 extern void cheetah_ecache_flush_init(void);
1306 static unsigned long last_valid_pfn;
1307 pgd_t swapper_pg_dir[2048];
1309 void __init paging_init(void)
1311 unsigned long end_pfn, pages_avail, shift;
1312 unsigned long real_end, i;
1314 /* Find available physical memory... */
1315 read_obp_memory("available", &pavail[0], &pavail_ents);
1317 phys_base = 0xffffffffffffffffUL;
1318 for (i = 0; i < pavail_ents; i++)
1319 phys_base = min(phys_base, pavail[i].phys_addr);
1321 pfn_base = phys_base >> PAGE_SHIFT;
1323 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1324 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1326 set_bit(0, mmu_context_bmap);
1328 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1330 real_end = (unsigned long)_end;
1331 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1333 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1334 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1338 /* Set kernel pgd to upper alias so physical page computations
1341 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1343 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1345 /* Now can init the kernel/bad page tables. */
1346 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1347 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1349 swapper_pgd_zero = pgd_val(swapper_pg_dir[0]);
1351 inherit_prom_mappings();
1353 /* Ok, we can use our TLB miss and window trap handlers safely.
1354 * We need to do a quick peek here to see if we are on StarFire
1355 * or not, so setup_tba can setup the IRQ globals correctly (it
1356 * needs to get the hard smp processor id correctly).
1359 extern void setup_tba(int);
1360 setup_tba(this_is_starfire);
1363 inherit_locked_prom_mappings(1);
1367 /* Setup bootmem... */
1369 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1371 #ifdef CONFIG_DEBUG_PAGEALLOC
1372 kernel_physical_mapping_init();
1376 unsigned long zones_size[MAX_NR_ZONES];
1377 unsigned long zholes_size[MAX_NR_ZONES];
1378 unsigned long npages;
1381 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1382 zones_size[znum] = zholes_size[znum] = 0;
1384 npages = end_pfn - pfn_base;
1385 zones_size[ZONE_DMA] = npages;
1386 zholes_size[ZONE_DMA] = npages - pages_avail;
1388 free_area_init_node(0, &contig_page_data, zones_size,
1389 phys_base >> PAGE_SHIFT, zholes_size);
1395 static void __init taint_real_pages(void)
1399 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1401 /* Find changes discovered in the physmem available rescan and
1402 * reserve the lost portions in the bootmem maps.
1404 for (i = 0; i < pavail_ents; i++) {
1405 unsigned long old_start, old_end;
1407 old_start = pavail[i].phys_addr;
1408 old_end = old_start +
1410 while (old_start < old_end) {
1413 for (n = 0; pavail_rescan_ents; n++) {
1414 unsigned long new_start, new_end;
1416 new_start = pavail_rescan[n].phys_addr;
1417 new_end = new_start +
1418 pavail_rescan[n].reg_size;
1420 if (new_start <= old_start &&
1421 new_end >= (old_start + PAGE_SIZE)) {
1422 set_bit(old_start >> 22,
1423 sparc64_valid_addr_bitmap);
1427 reserve_bootmem(old_start, PAGE_SIZE);
1430 old_start += PAGE_SIZE;
1435 void __init mem_init(void)
1437 unsigned long codepages, datapages, initpages;
1438 unsigned long addr, last;
1441 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1443 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1444 if (sparc64_valid_addr_bitmap == NULL) {
1445 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1448 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1450 addr = PAGE_OFFSET + kern_base;
1451 last = PAGE_ALIGN(kern_size) + addr;
1452 while (addr < last) {
1453 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1459 max_mapnr = last_valid_pfn - pfn_base;
1460 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1462 #ifdef CONFIG_DEBUG_BOOTMEM
1463 prom_printf("mem_init: Calling free_all_bootmem().\n");
1465 totalram_pages = num_physpages = free_all_bootmem() - 1;
1468 * Set up the zero page, mark it reserved, so that page count
1469 * is not manipulated when freeing the page from user ptes.
1471 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1472 if (mem_map_zero == NULL) {
1473 prom_printf("paging_init: Cannot alloc zero page.\n");
1476 SetPageReserved(mem_map_zero);
1478 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1479 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1480 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1481 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1482 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1483 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1485 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1486 nr_free_pages() << (PAGE_SHIFT-10),
1487 codepages << (PAGE_SHIFT-10),
1488 datapages << (PAGE_SHIFT-10),
1489 initpages << (PAGE_SHIFT-10),
1490 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1492 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1493 cheetah_ecache_flush_init();
1496 void free_initmem(void)
1498 unsigned long addr, initend;
1501 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1503 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1504 initend = (unsigned long)(__init_end) & PAGE_MASK;
1505 for (; addr < initend; addr += PAGE_SIZE) {
1510 ((unsigned long) __va(kern_base)) -
1511 ((unsigned long) KERNBASE));
1512 memset((void *)addr, 0xcc, PAGE_SIZE);
1513 p = virt_to_page(page);
1515 ClearPageReserved(p);
1516 set_page_count(p, 1);
1523 #ifdef CONFIG_BLK_DEV_INITRD
1524 void free_initrd_mem(unsigned long start, unsigned long end)
1527 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1528 for (; start < end; start += PAGE_SIZE) {
1529 struct page *p = virt_to_page(start);
1531 ClearPageReserved(p);
1532 set_page_count(p, 1);