2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV architectural definitions
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #ifndef _ASM_X86_UV_UV_HUB_H
12 #define _ASM_X86_UV_UV_HUB_H
14 #include <linux/numa.h>
15 #include <linux/percpu.h>
16 #include <linux/timer.h>
17 #include <asm/types.h>
18 #include <asm/percpu.h>
22 * Addressing Terminology
24 * M - The low M bits of a physical address represent the offset
25 * into the blade local memory. RAM memory on a blade is physically
26 * contiguous (although various IO spaces may punch holes in
29 * N - Number of bits in the node portion of a socket physical
32 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
33 * routers always have low bit of 1, C/MBricks have low bit
34 * equal to 0. Most addressing macros that target UV hub chips
35 * right shift the NASID by 1 to exclude the always-zero bit.
36 * NASIDs contain up to 15 bits.
38 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
41 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
42 * of the nasid for socket usage.
45 * NumaLink Global Physical Address Format:
46 * +--------------------------------+---------------------+
47 * |00..000| GNODE | NodeOffset |
48 * +--------------------------------+---------------------+
49 * |<-------53 - M bits --->|<--------M bits ----->
51 * M - number of node offset bits (35 .. 40)
54 * Memory/UV-HUB Processor Socket Address Format:
55 * +----------------+---------------+---------------------+
56 * |00..000000000000| PNODE | NodeOffset |
57 * +----------------+---------------+---------------------+
58 * <--- N bits --->|<--------M bits ----->
60 * M - number of node offset bits (35 .. 40)
61 * N - number of PNODE bits (0 .. 10)
63 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
64 * The actual values are configuration dependent and are set at
65 * boot time. M & N values are set by the hardware/BIOS at boot.
69 * NOTE!!!!!! This is the current format of the APICID. However, code
70 * should assume that this will change in the future. Use functions
71 * in this file for all APICID bit manipulations and conversion.
79 * l = socket number on board
82 * s = bits that are in the SOCKET_ID CSR
84 * Note: Processor only supports 12 bits in the APICID register. The ACPI
85 * tables hold all 16 bits. Software needs to be aware of this.
87 * Unless otherwise specified, all references to APICID refer to
88 * the FULL value contained in ACPI tables, not the subset in the
89 * processor APICID register.
94 * Maximum number of bricks in all partitions and in all coherency domains.
95 * This is the total number of bricks accessible in the numalink fabric. It
96 * includes all C & M bricks. Routers are NOT included.
98 * This value is also the value of the maximum number of non-router NASIDs
99 * in the numalink fabric.
101 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
103 #define UV_MAX_NUMALINK_BLADES 16384
106 * Maximum number of C/Mbricks within a software SSI (hardware may support
109 #define UV_MAX_SSI_BLADES 256
112 * The largest possible NASID of a C or M brick (+ 2)
114 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
117 struct timer_list timer;
118 unsigned long offset;
120 unsigned long idle_on;
121 unsigned long idle_off;
123 unsigned char enabled;
127 * The following defines attributes of the HUB chip. These attributes are
128 * frequently referenced and are kept in the per-cpu data areas of each cpu.
129 * They are kept together in a struct to minimize cache misses.
131 struct uv_hub_info_s {
132 unsigned long global_mmr_base;
133 unsigned long gpa_mask;
134 unsigned long gnode_upper;
135 unsigned long lowmem_remap_top;
136 unsigned long lowmem_remap_base;
137 unsigned short pnode;
138 unsigned short pnode_mask;
139 unsigned short coherency_domain_number;
140 unsigned short numa_blade_id;
141 unsigned char blade_processor_id;
144 struct uv_scir_s scir;
147 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
148 #define uv_hub_info (&__get_cpu_var(__uv_hub_info))
149 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
152 * Local & Global MMR space macros.
153 * Note: macros are intended to be used ONLY by inline functions
154 * in this file - not by other kernel code.
155 * n - NASID (full 15-bit global nasid)
156 * g - GNODE (full 15-bit global nasid, right shifted 1)
157 * p - PNODE (local part of nsids, right shifted 1)
159 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
160 #define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
162 #define UV_LOCAL_MMR_BASE 0xf4000000UL
163 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL
164 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
165 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
166 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
168 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15
169 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26
171 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
173 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \
174 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
176 #define UV_APIC_PNODE_SHIFT 6
178 /* Local Bus from cpu's perspective */
179 #define LOCAL_BUS_BASE 0x1c00000
180 #define LOCAL_BUS_SIZE (4 * 1024 * 1024)
183 * System Controller Interface Reg
185 * Note there are NO leds on a UV system. This register is only
186 * used by the system controller to monitor system-wide operation.
187 * There are 64 regs per node. With Nahelem cpus (2 cores per node,
188 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
191 * The window is located at top of ACPI MMR space
193 #define SCIR_WINDOW_COUNT 64
194 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
198 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
199 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */
200 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
203 * Macros for converting between kernel virtual addresses, socket local physical
204 * addresses, and UV global physical addresses.
205 * Note: use the standard __pa() & __va() macros for converting
206 * between socket virtual and socket physical addresses.
209 /* socket phys RAM --> UV global physical address */
210 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
212 if (paddr < uv_hub_info->lowmem_remap_top)
213 paddr |= uv_hub_info->lowmem_remap_base;
214 return paddr | uv_hub_info->gnode_upper;
218 /* socket virtual --> UV global physical address */
219 static inline unsigned long uv_gpa(void *v)
221 return uv_soc_phys_ram_to_gpa(__pa(v));
224 /* pnode, offset --> socket virtual */
225 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
227 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
232 * Extract a PNODE from an APICID (full apicid, not processor subset)
234 static inline int uv_apicid_to_pnode(int apicid)
236 return (apicid >> UV_APIC_PNODE_SHIFT);
240 * Access global MMRs using the low memory MMR32 space. This region supports
241 * faster MMR access but not all MMRs are accessible in this space.
243 static inline unsigned long *uv_global_mmr32_address(int pnode,
244 unsigned long offset)
246 return __va(UV_GLOBAL_MMR32_BASE |
247 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
250 static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
253 *uv_global_mmr32_address(pnode, offset) = val;
256 static inline unsigned long uv_read_global_mmr32(int pnode,
257 unsigned long offset)
259 return *uv_global_mmr32_address(pnode, offset);
263 * Access Global MMR space using the MMR space located at the top of physical
266 static inline unsigned long *uv_global_mmr64_address(int pnode,
267 unsigned long offset)
269 return __va(UV_GLOBAL_MMR64_BASE |
270 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
273 static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
276 *uv_global_mmr64_address(pnode, offset) = val;
279 static inline unsigned long uv_read_global_mmr64(int pnode,
280 unsigned long offset)
282 return *uv_global_mmr64_address(pnode, offset);
286 * Access hub local MMRs. Faster than using global space but only local MMRs
289 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
291 return __va(UV_LOCAL_MMR_BASE | offset);
294 static inline unsigned long uv_read_local_mmr(unsigned long offset)
296 return *uv_local_mmr_address(offset);
299 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
301 *uv_local_mmr_address(offset) = val;
304 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
306 return *((unsigned char *)uv_local_mmr_address(offset));
309 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
311 *((unsigned char *)uv_local_mmr_address(offset)) = val;
315 * Structures and definitions for converting between cpu, node, pnode, and blade
318 struct uv_blade_info {
319 unsigned short nr_possible_cpus;
320 unsigned short nr_online_cpus;
321 unsigned short pnode;
323 extern struct uv_blade_info *uv_blade_info;
324 extern short *uv_node_to_blade;
325 extern short *uv_cpu_to_blade;
326 extern short uv_possible_blades;
328 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
329 static inline int uv_blade_processor_id(void)
331 return uv_hub_info->blade_processor_id;
334 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
335 static inline int uv_numa_blade_id(void)
337 return uv_hub_info->numa_blade_id;
340 /* Convert a cpu number to the the UV blade number */
341 static inline int uv_cpu_to_blade_id(int cpu)
343 return uv_cpu_to_blade[cpu];
346 /* Convert linux node number to the UV blade number */
347 static inline int uv_node_to_blade_id(int nid)
349 return uv_node_to_blade[nid];
352 /* Convert a blade id to the PNODE of the blade */
353 static inline int uv_blade_to_pnode(int bid)
355 return uv_blade_info[bid].pnode;
358 /* Determine the number of possible cpus on a blade */
359 static inline int uv_blade_nr_possible_cpus(int bid)
361 return uv_blade_info[bid].nr_possible_cpus;
364 /* Determine the number of online cpus on a blade */
365 static inline int uv_blade_nr_online_cpus(int bid)
367 return uv_blade_info[bid].nr_online_cpus;
370 /* Convert a cpu id to the PNODE of the blade containing the cpu */
371 static inline int uv_cpu_to_pnode(int cpu)
373 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
376 /* Convert a linux node number to the PNODE of the blade */
377 static inline int uv_node_to_pnode(int nid)
379 return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
382 /* Maximum possible number of blades */
383 static inline int uv_num_possible_blades(void)
385 return uv_possible_blades;
388 /* Update SCIR state */
389 static inline void uv_set_scir_bits(unsigned char value)
391 if (uv_hub_info->scir.state != value) {
392 uv_hub_info->scir.state = value;
393 uv_write_local_mmr8(uv_hub_info->scir.offset, value);
396 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
398 if (uv_cpu_hub_info(cpu)->scir.state != value) {
399 uv_cpu_hub_info(cpu)->scir.state = value;
400 uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value);
404 #endif /* _ASM_X86_UV_UV_HUB_H */