2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV architectural definitions
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #ifndef _ASM_X86_UV_UV_HUB_H
12 #define _ASM_X86_UV_UV_HUB_H
14 #include <linux/numa.h>
15 #include <linux/percpu.h>
16 #include <linux/timer.h>
17 #include <asm/types.h>
18 #include <asm/percpu.h>
22 * Addressing Terminology
24 * M - The low M bits of a physical address represent the offset
25 * into the blade local memory. RAM memory on a blade is physically
26 * contiguous (although various IO spaces may punch holes in
29 * N - Number of bits in the node portion of a socket physical
32 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
33 * routers always have low bit of 1, C/MBricks have low bit
34 * equal to 0. Most addressing macros that target UV hub chips
35 * right shift the NASID by 1 to exclude the always-zero bit.
36 * NASIDs contain up to 15 bits.
38 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
41 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
42 * of the nasid for socket usage.
45 * NumaLink Global Physical Address Format:
46 * +--------------------------------+---------------------+
47 * |00..000| GNODE | NodeOffset |
48 * +--------------------------------+---------------------+
49 * |<-------53 - M bits --->|<--------M bits ----->
51 * M - number of node offset bits (35 .. 40)
54 * Memory/UV-HUB Processor Socket Address Format:
55 * +----------------+---------------+---------------------+
56 * |00..000000000000| PNODE | NodeOffset |
57 * +----------------+---------------+---------------------+
58 * <--- N bits --->|<--------M bits ----->
60 * M - number of node offset bits (35 .. 40)
61 * N - number of PNODE bits (0 .. 10)
63 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
64 * The actual values are configuration dependent and are set at
65 * boot time. M & N values are set by the hardware/BIOS at boot.
69 * NOTE!!!!!! This is the current format of the APICID. However, code
70 * should assume that this will change in the future. Use functions
71 * in this file for all APICID bit manipulations and conversion.
79 * l = socket number on board
82 * s = bits that are in the SOCKET_ID CSR
84 * Note: Processor only supports 12 bits in the APICID register. The ACPI
85 * tables hold all 16 bits. Software needs to be aware of this.
87 * Unless otherwise specified, all references to APICID refer to
88 * the FULL value contained in ACPI tables, not the subset in the
89 * processor APICID register.
94 * Maximum number of bricks in all partitions and in all coherency domains.
95 * This is the total number of bricks accessible in the numalink fabric. It
96 * includes all C & M bricks. Routers are NOT included.
98 * This value is also the value of the maximum number of non-router NASIDs
99 * in the numalink fabric.
101 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
103 #define UV_MAX_NUMALINK_BLADES 16384
106 * Maximum number of C/Mbricks within a software SSI (hardware may support
109 #define UV_MAX_SSI_BLADES 256
112 * The largest possible NASID of a C or M brick (+ 2)
114 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
117 * The following defines attributes of the HUB chip. These attributes are
118 * frequently referenced and are kept in the per-cpu data areas of each cpu.
119 * They are kept together in a struct to minimize cache misses.
121 struct uv_hub_info_s {
122 unsigned long global_mmr_base;
123 unsigned long gpa_mask;
124 unsigned long gnode_upper;
125 unsigned long lowmem_remap_top;
126 unsigned long lowmem_remap_base;
127 unsigned short pnode;
128 unsigned short pnode_mask;
129 unsigned short coherency_domain_number;
130 unsigned short numa_blade_id;
131 unsigned char blade_processor_id;
135 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
136 #define uv_hub_info (&__get_cpu_var(__uv_hub_info))
137 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
140 * Local & Global MMR space macros.
141 * Note: macros are intended to be used ONLY by inline functions
142 * in this file - not by other kernel code.
143 * n - NASID (full 15-bit global nasid)
144 * g - GNODE (full 15-bit global nasid, right shifted 1)
145 * p - PNODE (local part of nsids, right shifted 1)
147 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
148 #define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
150 #define UV_LOCAL_MMR_BASE 0xf4000000UL
151 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL
152 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
153 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
154 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
156 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15
157 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26
159 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
161 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \
162 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
164 #define UV_APIC_PNODE_SHIFT 6
167 * Macros for converting between kernel virtual addresses, socket local physical
168 * addresses, and UV global physical addresses.
169 * Note: use the standard __pa() & __va() macros for converting
170 * between socket virtual and socket physical addresses.
173 /* socket phys RAM --> UV global physical address */
174 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
176 if (paddr < uv_hub_info->lowmem_remap_top)
177 paddr += uv_hub_info->lowmem_remap_base;
178 return paddr | uv_hub_info->gnode_upper;
182 /* socket virtual --> UV global physical address */
183 static inline unsigned long uv_gpa(void *v)
185 return __pa(v) | uv_hub_info->gnode_upper;
188 /* socket virtual --> UV global physical address */
189 static inline void *uv_vgpa(void *v)
191 return (void *)uv_gpa(v);
194 /* UV global physical address --> socket virtual */
195 static inline void *uv_va(unsigned long gpa)
197 return __va(gpa & uv_hub_info->gpa_mask);
200 /* pnode, offset --> socket virtual */
201 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
203 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
208 * Extract a PNODE from an APICID (full apicid, not processor subset)
210 static inline int uv_apicid_to_pnode(int apicid)
212 return (apicid >> UV_APIC_PNODE_SHIFT);
216 * Access global MMRs using the low memory MMR32 space. This region supports
217 * faster MMR access but not all MMRs are accessible in this space.
219 static inline unsigned long *uv_global_mmr32_address(int pnode,
220 unsigned long offset)
222 return __va(UV_GLOBAL_MMR32_BASE |
223 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
226 static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
229 *uv_global_mmr32_address(pnode, offset) = val;
232 static inline unsigned long uv_read_global_mmr32(int pnode,
233 unsigned long offset)
235 return *uv_global_mmr32_address(pnode, offset);
239 * Access Global MMR space using the MMR space located at the top of physical
242 static inline unsigned long *uv_global_mmr64_address(int pnode,
243 unsigned long offset)
245 return __va(UV_GLOBAL_MMR64_BASE |
246 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
249 static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
252 *uv_global_mmr64_address(pnode, offset) = val;
255 static inline unsigned long uv_read_global_mmr64(int pnode,
256 unsigned long offset)
258 return *uv_global_mmr64_address(pnode, offset);
262 * Access hub local MMRs. Faster than using global space but only local MMRs
265 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
267 return __va(UV_LOCAL_MMR_BASE | offset);
270 static inline unsigned long uv_read_local_mmr(unsigned long offset)
272 return *uv_local_mmr_address(offset);
275 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
277 *uv_local_mmr_address(offset) = val;
281 * Structures and definitions for converting between cpu, node, pnode, and blade
284 struct uv_blade_info {
285 unsigned short nr_possible_cpus;
286 unsigned short nr_online_cpus;
287 unsigned short pnode;
289 extern struct uv_blade_info *uv_blade_info;
290 extern short *uv_node_to_blade;
291 extern short *uv_cpu_to_blade;
292 extern short uv_possible_blades;
294 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
295 static inline int uv_blade_processor_id(void)
297 return uv_hub_info->blade_processor_id;
300 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
301 static inline int uv_numa_blade_id(void)
303 return uv_hub_info->numa_blade_id;
306 /* Convert a cpu number to the the UV blade number */
307 static inline int uv_cpu_to_blade_id(int cpu)
309 return uv_cpu_to_blade[cpu];
312 /* Convert linux node number to the UV blade number */
313 static inline int uv_node_to_blade_id(int nid)
315 return uv_node_to_blade[nid];
318 /* Convert a blade id to the PNODE of the blade */
319 static inline int uv_blade_to_pnode(int bid)
321 return uv_blade_info[bid].pnode;
324 /* Determine the number of possible cpus on a blade */
325 static inline int uv_blade_nr_possible_cpus(int bid)
327 return uv_blade_info[bid].nr_possible_cpus;
330 /* Determine the number of online cpus on a blade */
331 static inline int uv_blade_nr_online_cpus(int bid)
333 return uv_blade_info[bid].nr_online_cpus;
336 /* Convert a cpu id to the PNODE of the blade containing the cpu */
337 static inline int uv_cpu_to_pnode(int cpu)
339 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
342 /* Convert a linux node number to the PNODE of the blade */
343 static inline int uv_node_to_pnode(int nid)
345 return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
348 /* Maximum possible number of blades */
349 static inline int uv_num_possible_blades(void)
351 return uv_possible_blades;
354 #endif /* _ASM_X86_UV_UV_HUB_H */