2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
27 #include <asm/amd_iommu_types.h>
28 #include <asm/amd_iommu.h>
30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
32 #define EXIT_LOOP_COUNT 10000000
34 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
37 * general struct to manage commands send to an IOMMU
43 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
44 struct unity_map_entry *e);
46 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
47 static int iommu_has_npcache(struct amd_iommu *iommu)
49 return iommu->cap & IOMMU_CAP_NPCACHE;
52 /****************************************************************************
54 * IOMMU command queuing functions
56 ****************************************************************************/
59 * Writes the command to the IOMMUs command buffer and informs the
60 * hardware about the new command. Must be called with iommu->lock held.
62 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
67 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
68 target = iommu->cmd_buf + tail;
69 memcpy_toio(target, cmd, sizeof(*cmd));
70 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
71 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
74 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
80 * General queuing function for commands. Takes iommu->lock and calls
81 * __iommu_queue_command().
83 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
88 spin_lock_irqsave(&iommu->lock, flags);
89 ret = __iommu_queue_command(iommu, cmd);
90 spin_unlock_irqrestore(&iommu->lock, flags);
96 * This function is called whenever we need to ensure that the IOMMU has
97 * completed execution of all commands we sent. It sends a
98 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
99 * us about that by writing a value to a physical address we pass with
102 static int iommu_completion_wait(struct amd_iommu *iommu)
106 struct iommu_cmd cmd;
109 memset(&cmd, 0, sizeof(cmd));
110 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
111 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
113 iommu->need_sync = 0;
115 ret = iommu_queue_command(iommu, &cmd);
120 while (!ready && (i < EXIT_LOOP_COUNT)) {
122 /* wait for the bit to become one */
123 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
124 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
127 /* set bit back to zero */
128 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
129 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
131 if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
132 printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
138 * Command send function for invalidating a device table entry
140 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
142 struct iommu_cmd cmd;
144 BUG_ON(iommu == NULL);
146 memset(&cmd, 0, sizeof(cmd));
147 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
150 iommu->need_sync = 1;
152 return iommu_queue_command(iommu, &cmd);
156 * Generic command send function for invalidaing TLB entries
158 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
159 u64 address, u16 domid, int pde, int s)
161 struct iommu_cmd cmd;
163 memset(&cmd, 0, sizeof(cmd));
164 address &= PAGE_MASK;
165 CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
166 cmd.data[1] |= domid;
167 cmd.data[2] = lower_32_bits(address);
168 cmd.data[3] = upper_32_bits(address);
169 if (s) /* size bit - we flush more than one 4kb page */
170 cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
171 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
172 cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
174 iommu->need_sync = 1;
176 return iommu_queue_command(iommu, &cmd);
180 * TLB invalidation function which is called from the mapping functions.
181 * It invalidates a single PTE if the range to flush is within a single
182 * page. Otherwise it flushes the whole TLB of the IOMMU.
184 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
185 u64 address, size_t size)
188 unsigned pages = iommu_num_pages(address, size);
190 address &= PAGE_MASK;
194 * If we have to flush more than one page, flush all
195 * TLB entries for this domain
197 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
201 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
206 /* Flush the whole IO/TLB for a given protection domain */
207 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
209 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
211 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
214 /****************************************************************************
216 * The functions below are used the create the page table mappings for
217 * unity mapped regions.
219 ****************************************************************************/
222 * Generic mapping functions. It maps a physical address into a DMA
223 * address space. It allocates the page table pages if necessary.
224 * In the future it can be extended to a generic mapping function
225 * supporting all features of AMD IOMMU page tables like level skipping
226 * and full 64 bit address spaces.
228 static int iommu_map(struct protection_domain *dom,
229 unsigned long bus_addr,
230 unsigned long phys_addr,
233 u64 __pte, *pte, *page;
235 bus_addr = PAGE_ALIGN(bus_addr);
236 phys_addr = PAGE_ALIGN(bus_addr);
238 /* only support 512GB address spaces for now */
239 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
242 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
244 if (!IOMMU_PTE_PRESENT(*pte)) {
245 page = (u64 *)get_zeroed_page(GFP_KERNEL);
248 *pte = IOMMU_L2_PDE(virt_to_phys(page));
251 pte = IOMMU_PTE_PAGE(*pte);
252 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
254 if (!IOMMU_PTE_PRESENT(*pte)) {
255 page = (u64 *)get_zeroed_page(GFP_KERNEL);
258 *pte = IOMMU_L1_PDE(virt_to_phys(page));
261 pte = IOMMU_PTE_PAGE(*pte);
262 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
264 if (IOMMU_PTE_PRESENT(*pte))
267 __pte = phys_addr | IOMMU_PTE_P;
268 if (prot & IOMMU_PROT_IR)
269 __pte |= IOMMU_PTE_IR;
270 if (prot & IOMMU_PROT_IW)
271 __pte |= IOMMU_PTE_IW;
279 * This function checks if a specific unity mapping entry is needed for
280 * this specific IOMMU.
282 static int iommu_for_unity_map(struct amd_iommu *iommu,
283 struct unity_map_entry *entry)
287 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
288 bdf = amd_iommu_alias_table[i];
289 if (amd_iommu_rlookup_table[bdf] == iommu)
297 * Init the unity mappings for a specific IOMMU in the system
299 * Basically iterates over all unity mapping entries and applies them to
300 * the default domain DMA of that IOMMU if necessary.
302 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
304 struct unity_map_entry *entry;
307 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
308 if (!iommu_for_unity_map(iommu, entry))
310 ret = dma_ops_unity_map(iommu->default_dom, entry);
319 * This function actually applies the mapping to the page table of the
322 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
323 struct unity_map_entry *e)
328 for (addr = e->address_start; addr < e->address_end;
330 ret = iommu_map(&dma_dom->domain, addr, addr, e->prot);
334 * if unity mapping is in aperture range mark the page
335 * as allocated in the aperture
337 if (addr < dma_dom->aperture_size)
338 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
345 * Inits the unity mappings required for a specific device
347 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
350 struct unity_map_entry *e;
353 list_for_each_entry(e, &amd_iommu_unity_map, list) {
354 if (!(devid >= e->devid_start && devid <= e->devid_end))
356 ret = dma_ops_unity_map(dma_dom, e);
364 /****************************************************************************
366 * The next functions belong to the address allocator for the dma_ops
367 * interface functions. They work like the allocators in the other IOMMU
368 * drivers. Its basically a bitmap which marks the allocated pages in
369 * the aperture. Maybe it could be enhanced in the future to a more
370 * efficient allocator.
372 ****************************************************************************/
373 static unsigned long dma_mask_to_pages(unsigned long mask)
375 return (mask >> PAGE_SHIFT) +
376 (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT);
380 * The address allocator core function.
382 * called with domain->lock held
384 static unsigned long dma_ops_alloc_addresses(struct device *dev,
385 struct dma_ops_domain *dom,
387 unsigned long align_mask)
389 unsigned long limit = dma_mask_to_pages(*dev->dma_mask);
390 unsigned long address;
391 unsigned long size = dom->aperture_size >> PAGE_SHIFT;
392 unsigned long boundary_size;
394 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
395 PAGE_SIZE) >> PAGE_SHIFT;
396 limit = limit < size ? limit : size;
398 if (dom->next_bit >= limit) {
400 dom->need_flush = true;
403 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
404 0 , boundary_size, align_mask);
406 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
407 0, boundary_size, align_mask);
408 dom->need_flush = true;
411 if (likely(address != -1)) {
412 dom->next_bit = address + pages;
413 address <<= PAGE_SHIFT;
415 address = bad_dma_address;
417 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
423 * The address free function.
425 * called with domain->lock held
427 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
428 unsigned long address,
431 address >>= PAGE_SHIFT;
432 iommu_area_free(dom->bitmap, address, pages);
435 /****************************************************************************
437 * The next functions belong to the domain allocation. A domain is
438 * allocated for every IOMMU as the default domain. If device isolation
439 * is enabled, every device get its own domain. The most important thing
440 * about domains is the page table mapping the DMA address space they
443 ****************************************************************************/
445 static u16 domain_id_alloc(void)
450 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
451 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
453 if (id > 0 && id < MAX_DOMAIN_ID)
454 __set_bit(id, amd_iommu_pd_alloc_bitmap);
457 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
463 * Used to reserve address ranges in the aperture (e.g. for exclusion
466 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
467 unsigned long start_page,
470 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
472 if (start_page + pages > last_page)
473 pages = last_page - start_page;
475 set_bit_string(dom->bitmap, start_page, pages);
478 static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
483 p1 = dma_dom->domain.pt_root;
488 for (i = 0; i < 512; ++i) {
489 if (!IOMMU_PTE_PRESENT(p1[i]))
492 p2 = IOMMU_PTE_PAGE(p1[i]);
493 for (j = 0; j < 512; ++i) {
494 if (!IOMMU_PTE_PRESENT(p2[j]))
496 p3 = IOMMU_PTE_PAGE(p2[j]);
497 free_page((unsigned long)p3);
500 free_page((unsigned long)p2);
503 free_page((unsigned long)p1);
507 * Free a domain, only used if something went wrong in the
508 * allocation path and we need to free an already allocated page table
510 static void dma_ops_domain_free(struct dma_ops_domain *dom)
515 dma_ops_free_pagetable(dom);
517 kfree(dom->pte_pages);
525 * Allocates a new protection domain usable for the dma_ops functions.
526 * It also intializes the page table and the address allocator data
527 * structures required for the dma_ops interface
529 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
532 struct dma_ops_domain *dma_dom;
533 unsigned i, num_pte_pages;
538 * Currently the DMA aperture must be between 32 MB and 1GB in size
540 if ((order < 25) || (order > 30))
543 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
547 spin_lock_init(&dma_dom->domain.lock);
549 dma_dom->domain.id = domain_id_alloc();
550 if (dma_dom->domain.id == 0)
552 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
553 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
554 dma_dom->domain.priv = dma_dom;
555 if (!dma_dom->domain.pt_root)
557 dma_dom->aperture_size = (1ULL << order);
558 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
560 if (!dma_dom->bitmap)
563 * mark the first page as allocated so we never return 0 as
564 * a valid dma-address. So we can use 0 as error value
566 dma_dom->bitmap[0] = 1;
567 dma_dom->next_bit = 0;
569 dma_dom->need_flush = false;
571 /* Intialize the exclusion range if necessary */
572 if (iommu->exclusion_start &&
573 iommu->exclusion_start < dma_dom->aperture_size) {
574 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
575 int pages = iommu_num_pages(iommu->exclusion_start,
576 iommu->exclusion_length);
577 dma_ops_reserve_addresses(dma_dom, startpage, pages);
581 * At the last step, build the page tables so we don't need to
582 * allocate page table pages in the dma_ops mapping/unmapping
585 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
586 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
588 if (!dma_dom->pte_pages)
591 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
595 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
597 for (i = 0; i < num_pte_pages; ++i) {
598 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
599 if (!dma_dom->pte_pages[i])
601 address = virt_to_phys(dma_dom->pte_pages[i]);
602 l2_pde[i] = IOMMU_L1_PDE(address);
608 dma_ops_domain_free(dma_dom);
614 * Find out the protection domain structure for a given PCI device. This
615 * will give us the pointer to the page table root for example.
617 static struct protection_domain *domain_for_device(u16 devid)
619 struct protection_domain *dom;
622 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
623 dom = amd_iommu_pd_table[devid];
624 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
630 * If a device is not yet associated with a domain, this function does
631 * assigns it visible for the hardware
633 static void set_device_domain(struct amd_iommu *iommu,
634 struct protection_domain *domain,
639 u64 pte_root = virt_to_phys(domain->pt_root);
641 pte_root |= (domain->mode & 0x07) << 9;
642 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2;
644 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
645 amd_iommu_dev_table[devid].data[0] = pte_root;
646 amd_iommu_dev_table[devid].data[1] = pte_root >> 32;
647 amd_iommu_dev_table[devid].data[2] = domain->id;
649 amd_iommu_pd_table[devid] = domain;
650 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
652 iommu_queue_inv_dev_entry(iommu, devid);
654 iommu->need_sync = 1;
657 /*****************************************************************************
659 * The next functions belong to the dma_ops mapping/unmapping code.
661 *****************************************************************************/
664 * This function checks if the driver got a valid device from the caller to
665 * avoid dereferencing invalid pointers.
667 static bool check_device(struct device *dev)
669 if (!dev || !dev->dma_mask)
676 * In the dma_ops path we only have the struct device. This function
677 * finds the corresponding IOMMU, the protection domain and the
678 * requestor id for a given device.
679 * If the device is not yet associated with a domain this is also done
682 static int get_device_resources(struct device *dev,
683 struct amd_iommu **iommu,
684 struct protection_domain **domain,
687 struct dma_ops_domain *dma_dom;
688 struct pci_dev *pcidev;
695 if (dev->bus != &pci_bus_type)
698 pcidev = to_pci_dev(dev);
699 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
701 /* device not translated by any IOMMU in the system? */
702 if (_bdf > amd_iommu_last_bdf)
705 *bdf = amd_iommu_alias_table[_bdf];
707 *iommu = amd_iommu_rlookup_table[*bdf];
710 dma_dom = (*iommu)->default_dom;
711 *domain = domain_for_device(*bdf);
712 if (*domain == NULL) {
713 *domain = &dma_dom->domain;
714 set_device_domain(*iommu, *domain, *bdf);
715 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
716 "device ", (*domain)->id);
717 print_devid(_bdf, 1);
724 * This is the generic map function. It maps one 4kb page at paddr to
725 * the given address in the DMA address space for the domain.
727 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
728 struct dma_ops_domain *dom,
729 unsigned long address,
735 WARN_ON(address > dom->aperture_size);
739 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
740 pte += IOMMU_PTE_L0_INDEX(address);
742 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
744 if (direction == DMA_TO_DEVICE)
745 __pte |= IOMMU_PTE_IR;
746 else if (direction == DMA_FROM_DEVICE)
747 __pte |= IOMMU_PTE_IW;
748 else if (direction == DMA_BIDIRECTIONAL)
749 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
755 return (dma_addr_t)address;
759 * The generic unmapping function for on page in the DMA address space.
761 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
762 struct dma_ops_domain *dom,
763 unsigned long address)
767 if (address >= dom->aperture_size)
770 WARN_ON(address & 0xfffULL || address > dom->aperture_size);
772 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
773 pte += IOMMU_PTE_L0_INDEX(address);
781 * This function contains common code for mapping of a physically
782 * contiguous memory region into DMA address space. It is uses by all
783 * mapping functions provided by this IOMMU driver.
784 * Must be called with the domain lock held.
786 static dma_addr_t __map_single(struct device *dev,
787 struct amd_iommu *iommu,
788 struct dma_ops_domain *dma_dom,
794 dma_addr_t offset = paddr & ~PAGE_MASK;
795 dma_addr_t address, start;
797 unsigned long align_mask = 0;
800 pages = iommu_num_pages(paddr, size);
804 align_mask = (1UL << get_order(size)) - 1;
806 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask);
807 if (unlikely(address == bad_dma_address))
811 for (i = 0; i < pages; ++i) {
812 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
818 if (unlikely(dma_dom->need_flush && !iommu_fullflush)) {
819 iommu_flush_tlb(iommu, dma_dom->domain.id);
820 dma_dom->need_flush = false;
821 } else if (unlikely(iommu_has_npcache(iommu)))
822 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
829 * Does the reverse of the __map_single function. Must be called with
830 * the domain lock held too
832 static void __unmap_single(struct amd_iommu *iommu,
833 struct dma_ops_domain *dma_dom,
841 if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size))
844 pages = iommu_num_pages(dma_addr, size);
845 dma_addr &= PAGE_MASK;
848 for (i = 0; i < pages; ++i) {
849 dma_ops_domain_unmap(iommu, dma_dom, start);
853 dma_ops_free_addresses(dma_dom, dma_addr, pages);
856 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
860 * The exported map_single function for dma_ops.
862 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
863 size_t size, int dir)
866 struct amd_iommu *iommu;
867 struct protection_domain *domain;
871 if (!check_device(dev))
872 return bad_dma_address;
874 get_device_resources(dev, &iommu, &domain, &devid);
876 if (iommu == NULL || domain == NULL)
877 /* device not handled by any AMD IOMMU */
878 return (dma_addr_t)paddr;
880 spin_lock_irqsave(&domain->lock, flags);
881 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false);
882 if (addr == bad_dma_address)
885 if (unlikely(iommu->need_sync))
886 iommu_completion_wait(iommu);
889 spin_unlock_irqrestore(&domain->lock, flags);
895 * The exported unmap_single function for dma_ops.
897 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
898 size_t size, int dir)
901 struct amd_iommu *iommu;
902 struct protection_domain *domain;
905 if (!check_device(dev) ||
906 !get_device_resources(dev, &iommu, &domain, &devid))
907 /* device not handled by any AMD IOMMU */
910 spin_lock_irqsave(&domain->lock, flags);
912 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
914 if (unlikely(iommu->need_sync))
915 iommu_completion_wait(iommu);
917 spin_unlock_irqrestore(&domain->lock, flags);
921 * This is a special map_sg function which is used if we should map a
922 * device which is not handled by an AMD IOMMU in the system.
924 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
927 struct scatterlist *s;
930 for_each_sg(sglist, s, nelems, i) {
931 s->dma_address = (dma_addr_t)sg_phys(s);
932 s->dma_length = s->length;
939 * The exported map_sg function for dma_ops (handles scatter-gather
942 static int map_sg(struct device *dev, struct scatterlist *sglist,
946 struct amd_iommu *iommu;
947 struct protection_domain *domain;
950 struct scatterlist *s;
952 int mapped_elems = 0;
954 if (!check_device(dev))
957 get_device_resources(dev, &iommu, &domain, &devid);
959 if (!iommu || !domain)
960 return map_sg_no_iommu(dev, sglist, nelems, dir);
962 spin_lock_irqsave(&domain->lock, flags);
964 for_each_sg(sglist, s, nelems, i) {
967 s->dma_address = __map_single(dev, iommu, domain->priv,
968 paddr, s->length, dir, false);
970 if (s->dma_address) {
971 s->dma_length = s->length;
977 if (unlikely(iommu->need_sync))
978 iommu_completion_wait(iommu);
981 spin_unlock_irqrestore(&domain->lock, flags);
985 for_each_sg(sglist, s, mapped_elems, i) {
987 __unmap_single(iommu, domain->priv, s->dma_address,
989 s->dma_address = s->dma_length = 0;
998 * The exported map_sg function for dma_ops (handles scatter-gather
1001 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1002 int nelems, int dir)
1004 unsigned long flags;
1005 struct amd_iommu *iommu;
1006 struct protection_domain *domain;
1007 struct scatterlist *s;
1011 if (!check_device(dev) ||
1012 !get_device_resources(dev, &iommu, &domain, &devid))
1015 spin_lock_irqsave(&domain->lock, flags);
1017 for_each_sg(sglist, s, nelems, i) {
1018 __unmap_single(iommu, domain->priv, s->dma_address,
1019 s->dma_length, dir);
1020 s->dma_address = s->dma_length = 0;
1023 if (unlikely(iommu->need_sync))
1024 iommu_completion_wait(iommu);
1026 spin_unlock_irqrestore(&domain->lock, flags);
1030 * The exported alloc_coherent function for dma_ops.
1032 static void *alloc_coherent(struct device *dev, size_t size,
1033 dma_addr_t *dma_addr, gfp_t flag)
1035 unsigned long flags;
1037 struct amd_iommu *iommu;
1038 struct protection_domain *domain;
1042 if (!check_device(dev))
1045 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1049 memset(virt_addr, 0, size);
1050 paddr = virt_to_phys(virt_addr);
1052 get_device_resources(dev, &iommu, &domain, &devid);
1054 if (!iommu || !domain) {
1055 *dma_addr = (dma_addr_t)paddr;
1059 spin_lock_irqsave(&domain->lock, flags);
1061 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1062 size, DMA_BIDIRECTIONAL, true);
1064 if (*dma_addr == bad_dma_address) {
1065 free_pages((unsigned long)virt_addr, get_order(size));
1070 if (unlikely(iommu->need_sync))
1071 iommu_completion_wait(iommu);
1074 spin_unlock_irqrestore(&domain->lock, flags);
1080 * The exported free_coherent function for dma_ops.
1082 static void free_coherent(struct device *dev, size_t size,
1083 void *virt_addr, dma_addr_t dma_addr)
1085 unsigned long flags;
1086 struct amd_iommu *iommu;
1087 struct protection_domain *domain;
1090 if (!check_device(dev))
1093 get_device_resources(dev, &iommu, &domain, &devid);
1095 if (!iommu || !domain)
1098 spin_lock_irqsave(&domain->lock, flags);
1100 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1102 if (unlikely(iommu->need_sync))
1103 iommu_completion_wait(iommu);
1105 spin_unlock_irqrestore(&domain->lock, flags);
1108 free_pages((unsigned long)virt_addr, get_order(size));
1112 * The function for pre-allocating protection domains.
1114 * If the driver core informs the DMA layer if a driver grabs a device
1115 * we don't need to preallocate the protection domains anymore.
1116 * For now we have to.
1118 void prealloc_protection_domains(void)
1120 struct pci_dev *dev = NULL;
1121 struct dma_ops_domain *dma_dom;
1122 struct amd_iommu *iommu;
1123 int order = amd_iommu_aperture_order;
1126 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1127 devid = (dev->bus->number << 8) | dev->devfn;
1128 if (devid > amd_iommu_last_bdf)
1130 devid = amd_iommu_alias_table[devid];
1131 if (domain_for_device(devid))
1133 iommu = amd_iommu_rlookup_table[devid];
1136 dma_dom = dma_ops_domain_alloc(iommu, order);
1139 init_unity_mappings_for_device(dma_dom, devid);
1140 set_device_domain(iommu, &dma_dom->domain, devid);
1141 printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ",
1142 dma_dom->domain.id);
1143 print_devid(devid, 1);
1147 static struct dma_mapping_ops amd_iommu_dma_ops = {
1148 .alloc_coherent = alloc_coherent,
1149 .free_coherent = free_coherent,
1150 .map_single = map_single,
1151 .unmap_single = unmap_single,
1153 .unmap_sg = unmap_sg,
1157 * The function which clues the AMD IOMMU driver into dma_ops.
1159 int __init amd_iommu_init_dma_ops(void)
1161 struct amd_iommu *iommu;
1162 int order = amd_iommu_aperture_order;
1166 * first allocate a default protection domain for every IOMMU we
1167 * found in the system. Devices not assigned to any other
1168 * protection domain will be assigned to the default one.
1170 list_for_each_entry(iommu, &amd_iommu_list, list) {
1171 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1172 if (iommu->default_dom == NULL)
1174 ret = iommu_init_unity_mappings(iommu);
1180 * If device isolation is enabled, pre-allocate the protection
1181 * domains for each device.
1183 if (amd_iommu_isolate)
1184 prealloc_protection_domains();
1188 bad_dma_address = 0;
1189 #ifdef CONFIG_GART_IOMMU
1190 gart_iommu_aperture_disabled = 1;
1191 gart_iommu_aperture = 0;
1194 /* Make the driver finally visible to the drivers */
1195 dma_ops = &amd_iommu_dma_ops;
1201 list_for_each_entry(iommu, &amd_iommu_list, list) {
1202 if (iommu->default_dom)
1203 dma_ops_domain_free(iommu->default_dom);