2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops;
50 * general struct to manage commands send to an IOMMU
56 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
57 struct unity_map_entry *e);
58 static struct dma_ops_domain *find_protection_domain(u16 devid);
61 #ifdef CONFIG_AMD_IOMMU_STATS
64 * Initialization code for statistics collection
67 DECLARE_STATS_COUNTER(compl_wait);
68 DECLARE_STATS_COUNTER(cnt_map_single);
69 DECLARE_STATS_COUNTER(cnt_unmap_single);
70 DECLARE_STATS_COUNTER(cnt_map_sg);
71 DECLARE_STATS_COUNTER(cnt_unmap_sg);
72 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
73 DECLARE_STATS_COUNTER(cnt_free_coherent);
74 DECLARE_STATS_COUNTER(cross_page);
75 DECLARE_STATS_COUNTER(domain_flush_single);
77 static struct dentry *stats_dir;
78 static struct dentry *de_isolate;
79 static struct dentry *de_fflush;
81 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
83 if (stats_dir == NULL)
86 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
90 static void amd_iommu_stats_init(void)
92 stats_dir = debugfs_create_dir("amd-iommu", NULL);
93 if (stats_dir == NULL)
96 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
97 (u32 *)&amd_iommu_isolate);
99 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
100 (u32 *)&amd_iommu_unmap_flush);
102 amd_iommu_stats_add(&compl_wait);
103 amd_iommu_stats_add(&cnt_map_single);
104 amd_iommu_stats_add(&cnt_unmap_single);
105 amd_iommu_stats_add(&cnt_map_sg);
106 amd_iommu_stats_add(&cnt_unmap_sg);
107 amd_iommu_stats_add(&cnt_alloc_coherent);
108 amd_iommu_stats_add(&cnt_free_coherent);
109 amd_iommu_stats_add(&cross_page);
110 amd_iommu_stats_add(&domain_flush_single);
115 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
116 static int iommu_has_npcache(struct amd_iommu *iommu)
118 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
121 /****************************************************************************
123 * Interrupt handling functions
125 ****************************************************************************/
127 static void iommu_print_event(void *__evt)
130 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
131 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
132 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
133 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
134 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
136 printk(KERN_ERR "AMD IOMMU: Event logged [");
139 case EVENT_TYPE_ILL_DEV:
140 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
141 "address=0x%016llx flags=0x%04x]\n",
142 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
145 case EVENT_TYPE_IO_FAULT:
146 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
147 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
148 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
149 domid, address, flags);
151 case EVENT_TYPE_DEV_TAB_ERR:
152 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
153 "address=0x%016llx flags=0x%04x]\n",
154 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
157 case EVENT_TYPE_PAGE_TAB_ERR:
158 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
159 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
160 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
161 domid, address, flags);
163 case EVENT_TYPE_ILL_CMD:
164 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
166 case EVENT_TYPE_CMD_HARD_ERR:
167 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
168 "flags=0x%04x]\n", address, flags);
170 case EVENT_TYPE_IOTLB_INV_TO:
171 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
172 "address=0x%016llx]\n",
173 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
176 case EVENT_TYPE_INV_DEV_REQ:
177 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
178 "address=0x%016llx flags=0x%04x]\n",
179 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
183 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
187 static void iommu_poll_events(struct amd_iommu *iommu)
192 spin_lock_irqsave(&iommu->lock, flags);
194 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
195 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
197 while (head != tail) {
198 iommu_print_event(iommu->evt_buf + head);
199 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
202 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
204 spin_unlock_irqrestore(&iommu->lock, flags);
207 irqreturn_t amd_iommu_int_handler(int irq, void *data)
209 struct amd_iommu *iommu;
211 list_for_each_entry(iommu, &amd_iommu_list, list)
212 iommu_poll_events(iommu);
217 /****************************************************************************
219 * IOMMU command queuing functions
221 ****************************************************************************/
224 * Writes the command to the IOMMUs command buffer and informs the
225 * hardware about the new command. Must be called with iommu->lock held.
227 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
232 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
233 target = iommu->cmd_buf + tail;
234 memcpy_toio(target, cmd, sizeof(*cmd));
235 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
236 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
239 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
245 * General queuing function for commands. Takes iommu->lock and calls
246 * __iommu_queue_command().
248 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
253 spin_lock_irqsave(&iommu->lock, flags);
254 ret = __iommu_queue_command(iommu, cmd);
256 iommu->need_sync = true;
257 spin_unlock_irqrestore(&iommu->lock, flags);
263 * This function waits until an IOMMU has completed a completion
266 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
272 INC_STATS_COUNTER(compl_wait);
274 while (!ready && (i < EXIT_LOOP_COUNT)) {
276 /* wait for the bit to become one */
277 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
278 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
281 /* set bit back to zero */
282 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
283 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
285 if (unlikely(i == EXIT_LOOP_COUNT))
286 panic("AMD IOMMU: Completion wait loop failed\n");
290 * This function queues a completion wait command into the command
293 static int __iommu_completion_wait(struct amd_iommu *iommu)
295 struct iommu_cmd cmd;
297 memset(&cmd, 0, sizeof(cmd));
298 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
299 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
301 return __iommu_queue_command(iommu, &cmd);
305 * This function is called whenever we need to ensure that the IOMMU has
306 * completed execution of all commands we sent. It sends a
307 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
308 * us about that by writing a value to a physical address we pass with
311 static int iommu_completion_wait(struct amd_iommu *iommu)
316 spin_lock_irqsave(&iommu->lock, flags);
318 if (!iommu->need_sync)
321 ret = __iommu_completion_wait(iommu);
323 iommu->need_sync = false;
328 __iommu_wait_for_completion(iommu);
331 spin_unlock_irqrestore(&iommu->lock, flags);
337 * Command send function for invalidating a device table entry
339 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
341 struct iommu_cmd cmd;
344 BUG_ON(iommu == NULL);
346 memset(&cmd, 0, sizeof(cmd));
347 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
350 ret = iommu_queue_command(iommu, &cmd);
355 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
356 u16 domid, int pde, int s)
358 memset(cmd, 0, sizeof(*cmd));
359 address &= PAGE_MASK;
360 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
361 cmd->data[1] |= domid;
362 cmd->data[2] = lower_32_bits(address);
363 cmd->data[3] = upper_32_bits(address);
364 if (s) /* size bit - we flush more than one 4kb page */
365 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
366 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
367 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
371 * Generic command send function for invalidaing TLB entries
373 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
374 u64 address, u16 domid, int pde, int s)
376 struct iommu_cmd cmd;
379 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
381 ret = iommu_queue_command(iommu, &cmd);
387 * TLB invalidation function which is called from the mapping functions.
388 * It invalidates a single PTE if the range to flush is within a single
389 * page. Otherwise it flushes the whole TLB of the IOMMU.
391 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
392 u64 address, size_t size)
395 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
397 address &= PAGE_MASK;
401 * If we have to flush more than one page, flush all
402 * TLB entries for this domain
404 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
408 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
413 /* Flush the whole IO/TLB for a given protection domain */
414 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
416 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
418 INC_STATS_COUNTER(domain_flush_single);
420 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
423 #ifdef CONFIG_IOMMU_API
425 * This function is used to flush the IO/TLB for a given protection domain
426 * on every IOMMU in the system
428 static void iommu_flush_domain(u16 domid)
431 struct amd_iommu *iommu;
432 struct iommu_cmd cmd;
434 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
437 list_for_each_entry(iommu, &amd_iommu_list, list) {
438 spin_lock_irqsave(&iommu->lock, flags);
439 __iommu_queue_command(iommu, &cmd);
440 __iommu_completion_wait(iommu);
441 __iommu_wait_for_completion(iommu);
442 spin_unlock_irqrestore(&iommu->lock, flags);
447 /****************************************************************************
449 * The functions below are used the create the page table mappings for
450 * unity mapped regions.
452 ****************************************************************************/
455 * Generic mapping functions. It maps a physical address into a DMA
456 * address space. It allocates the page table pages if necessary.
457 * In the future it can be extended to a generic mapping function
458 * supporting all features of AMD IOMMU page tables like level skipping
459 * and full 64 bit address spaces.
461 static int iommu_map_page(struct protection_domain *dom,
462 unsigned long bus_addr,
463 unsigned long phys_addr,
466 u64 __pte, *pte, *page;
468 bus_addr = PAGE_ALIGN(bus_addr);
469 phys_addr = PAGE_ALIGN(phys_addr);
471 /* only support 512GB address spaces for now */
472 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
475 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
477 if (!IOMMU_PTE_PRESENT(*pte)) {
478 page = (u64 *)get_zeroed_page(GFP_KERNEL);
481 *pte = IOMMU_L2_PDE(virt_to_phys(page));
484 pte = IOMMU_PTE_PAGE(*pte);
485 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
487 if (!IOMMU_PTE_PRESENT(*pte)) {
488 page = (u64 *)get_zeroed_page(GFP_KERNEL);
491 *pte = IOMMU_L1_PDE(virt_to_phys(page));
494 pte = IOMMU_PTE_PAGE(*pte);
495 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
497 if (IOMMU_PTE_PRESENT(*pte))
500 __pte = phys_addr | IOMMU_PTE_P;
501 if (prot & IOMMU_PROT_IR)
502 __pte |= IOMMU_PTE_IR;
503 if (prot & IOMMU_PROT_IW)
504 __pte |= IOMMU_PTE_IW;
511 #ifdef CONFIG_IOMMU_API
512 static void iommu_unmap_page(struct protection_domain *dom,
513 unsigned long bus_addr)
517 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
519 if (!IOMMU_PTE_PRESENT(*pte))
522 pte = IOMMU_PTE_PAGE(*pte);
523 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
525 if (!IOMMU_PTE_PRESENT(*pte))
528 pte = IOMMU_PTE_PAGE(*pte);
529 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
536 * This function checks if a specific unity mapping entry is needed for
537 * this specific IOMMU.
539 static int iommu_for_unity_map(struct amd_iommu *iommu,
540 struct unity_map_entry *entry)
544 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
545 bdf = amd_iommu_alias_table[i];
546 if (amd_iommu_rlookup_table[bdf] == iommu)
554 * Init the unity mappings for a specific IOMMU in the system
556 * Basically iterates over all unity mapping entries and applies them to
557 * the default domain DMA of that IOMMU if necessary.
559 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
561 struct unity_map_entry *entry;
564 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
565 if (!iommu_for_unity_map(iommu, entry))
567 ret = dma_ops_unity_map(iommu->default_dom, entry);
576 * This function actually applies the mapping to the page table of the
579 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
580 struct unity_map_entry *e)
585 for (addr = e->address_start; addr < e->address_end;
587 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
591 * if unity mapping is in aperture range mark the page
592 * as allocated in the aperture
594 if (addr < dma_dom->aperture_size)
595 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
602 * Inits the unity mappings required for a specific device
604 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
607 struct unity_map_entry *e;
610 list_for_each_entry(e, &amd_iommu_unity_map, list) {
611 if (!(devid >= e->devid_start && devid <= e->devid_end))
613 ret = dma_ops_unity_map(dma_dom, e);
621 /****************************************************************************
623 * The next functions belong to the address allocator for the dma_ops
624 * interface functions. They work like the allocators in the other IOMMU
625 * drivers. Its basically a bitmap which marks the allocated pages in
626 * the aperture. Maybe it could be enhanced in the future to a more
627 * efficient allocator.
629 ****************************************************************************/
632 * The address allocator core function.
634 * called with domain->lock held
636 static unsigned long dma_ops_alloc_addresses(struct device *dev,
637 struct dma_ops_domain *dom,
639 unsigned long align_mask,
643 unsigned long address;
644 unsigned long boundary_size;
646 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
647 PAGE_SIZE) >> PAGE_SHIFT;
648 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
649 dma_mask >> PAGE_SHIFT);
651 if (dom->next_bit >= limit) {
653 dom->need_flush = true;
656 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
657 0 , boundary_size, align_mask);
659 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
660 0, boundary_size, align_mask);
661 dom->need_flush = true;
664 if (likely(address != -1)) {
665 dom->next_bit = address + pages;
666 address <<= PAGE_SHIFT;
668 address = bad_dma_address;
670 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
676 * The address free function.
678 * called with domain->lock held
680 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
681 unsigned long address,
684 address >>= PAGE_SHIFT;
685 iommu_area_free(dom->bitmap, address, pages);
687 if (address >= dom->next_bit)
688 dom->need_flush = true;
691 /****************************************************************************
693 * The next functions belong to the domain allocation. A domain is
694 * allocated for every IOMMU as the default domain. If device isolation
695 * is enabled, every device get its own domain. The most important thing
696 * about domains is the page table mapping the DMA address space they
699 ****************************************************************************/
701 static u16 domain_id_alloc(void)
706 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
707 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
709 if (id > 0 && id < MAX_DOMAIN_ID)
710 __set_bit(id, amd_iommu_pd_alloc_bitmap);
713 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
718 #ifdef CONFIG_IOMMU_API
719 static void domain_id_free(int id)
723 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
724 if (id > 0 && id < MAX_DOMAIN_ID)
725 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
726 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
731 * Used to reserve address ranges in the aperture (e.g. for exclusion
734 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
735 unsigned long start_page,
738 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
740 if (start_page + pages > last_page)
741 pages = last_page - start_page;
743 iommu_area_reserve(dom->bitmap, start_page, pages);
746 static void free_pagetable(struct protection_domain *domain)
751 p1 = domain->pt_root;
756 for (i = 0; i < 512; ++i) {
757 if (!IOMMU_PTE_PRESENT(p1[i]))
760 p2 = IOMMU_PTE_PAGE(p1[i]);
761 for (j = 0; j < 512; ++j) {
762 if (!IOMMU_PTE_PRESENT(p2[j]))
764 p3 = IOMMU_PTE_PAGE(p2[j]);
765 free_page((unsigned long)p3);
768 free_page((unsigned long)p2);
771 free_page((unsigned long)p1);
773 domain->pt_root = NULL;
777 * Free a domain, only used if something went wrong in the
778 * allocation path and we need to free an already allocated page table
780 static void dma_ops_domain_free(struct dma_ops_domain *dom)
785 free_pagetable(&dom->domain);
787 kfree(dom->pte_pages);
795 * Allocates a new protection domain usable for the dma_ops functions.
796 * It also intializes the page table and the address allocator data
797 * structures required for the dma_ops interface
799 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
802 struct dma_ops_domain *dma_dom;
803 unsigned i, num_pte_pages;
808 * Currently the DMA aperture must be between 32 MB and 1GB in size
810 if ((order < 25) || (order > 30))
813 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
817 spin_lock_init(&dma_dom->domain.lock);
819 dma_dom->domain.id = domain_id_alloc();
820 if (dma_dom->domain.id == 0)
822 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
823 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
824 dma_dom->domain.flags = PD_DMA_OPS_MASK;
825 dma_dom->domain.priv = dma_dom;
826 if (!dma_dom->domain.pt_root)
828 dma_dom->aperture_size = (1ULL << order);
829 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
831 if (!dma_dom->bitmap)
834 * mark the first page as allocated so we never return 0 as
835 * a valid dma-address. So we can use 0 as error value
837 dma_dom->bitmap[0] = 1;
838 dma_dom->next_bit = 0;
840 dma_dom->need_flush = false;
841 dma_dom->target_dev = 0xffff;
843 /* Intialize the exclusion range if necessary */
844 if (iommu->exclusion_start &&
845 iommu->exclusion_start < dma_dom->aperture_size) {
846 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
847 int pages = iommu_num_pages(iommu->exclusion_start,
848 iommu->exclusion_length,
850 dma_ops_reserve_addresses(dma_dom, startpage, pages);
854 * At the last step, build the page tables so we don't need to
855 * allocate page table pages in the dma_ops mapping/unmapping
858 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
859 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
861 if (!dma_dom->pte_pages)
864 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
868 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
870 for (i = 0; i < num_pte_pages; ++i) {
871 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
872 if (!dma_dom->pte_pages[i])
874 address = virt_to_phys(dma_dom->pte_pages[i]);
875 l2_pde[i] = IOMMU_L1_PDE(address);
881 dma_ops_domain_free(dma_dom);
887 * little helper function to check whether a given protection domain is a
890 static bool dma_ops_domain(struct protection_domain *domain)
892 return domain->flags & PD_DMA_OPS_MASK;
896 * Find out the protection domain structure for a given PCI device. This
897 * will give us the pointer to the page table root for example.
899 static struct protection_domain *domain_for_device(u16 devid)
901 struct protection_domain *dom;
904 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
905 dom = amd_iommu_pd_table[devid];
906 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
912 * If a device is not yet associated with a domain, this function does
913 * assigns it visible for the hardware
915 static void attach_device(struct amd_iommu *iommu,
916 struct protection_domain *domain,
920 u64 pte_root = virt_to_phys(domain->pt_root);
922 domain->dev_cnt += 1;
924 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
925 << DEV_ENTRY_MODE_SHIFT;
926 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
928 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
929 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
930 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
931 amd_iommu_dev_table[devid].data[2] = domain->id;
933 amd_iommu_pd_table[devid] = domain;
934 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
936 iommu_queue_inv_dev_entry(iommu, devid);
940 * Removes a device from a protection domain (unlocked)
942 static void __detach_device(struct protection_domain *domain, u16 devid)
946 spin_lock(&domain->lock);
948 /* remove domain from the lookup table */
949 amd_iommu_pd_table[devid] = NULL;
951 /* remove entry from the device table seen by the hardware */
952 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
953 amd_iommu_dev_table[devid].data[1] = 0;
954 amd_iommu_dev_table[devid].data[2] = 0;
956 /* decrease reference counter */
957 domain->dev_cnt -= 1;
960 spin_unlock(&domain->lock);
964 * Removes a device from a protection domain (with devtable_lock held)
966 static void detach_device(struct protection_domain *domain, u16 devid)
970 /* lock device table */
971 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
972 __detach_device(domain, devid);
973 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
976 static int device_change_notifier(struct notifier_block *nb,
977 unsigned long action, void *data)
979 struct device *dev = data;
980 struct pci_dev *pdev = to_pci_dev(dev);
981 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
982 struct protection_domain *domain;
983 struct dma_ops_domain *dma_domain;
984 struct amd_iommu *iommu;
985 int order = amd_iommu_aperture_order;
988 if (devid > amd_iommu_last_bdf)
991 devid = amd_iommu_alias_table[devid];
993 iommu = amd_iommu_rlookup_table[devid];
997 domain = domain_for_device(devid);
999 if (domain && !dma_ops_domain(domain))
1000 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1001 "to a non-dma-ops domain\n", dev_name(dev));
1004 case BUS_NOTIFY_BOUND_DRIVER:
1007 dma_domain = find_protection_domain(devid);
1009 dma_domain = iommu->default_dom;
1010 attach_device(iommu, &dma_domain->domain, devid);
1011 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1012 "device %s\n", dma_domain->domain.id, dev_name(dev));
1014 case BUS_NOTIFY_UNBIND_DRIVER:
1017 detach_device(domain, devid);
1019 case BUS_NOTIFY_ADD_DEVICE:
1020 /* allocate a protection domain if a device is added */
1021 dma_domain = find_protection_domain(devid);
1024 dma_domain = dma_ops_domain_alloc(iommu, order);
1027 dma_domain->target_dev = devid;
1029 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1030 list_add_tail(&dma_domain->list, &iommu_pd_list);
1031 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1038 iommu_queue_inv_dev_entry(iommu, devid);
1039 iommu_completion_wait(iommu);
1045 struct notifier_block device_nb = {
1046 .notifier_call = device_change_notifier,
1049 /*****************************************************************************
1051 * The next functions belong to the dma_ops mapping/unmapping code.
1053 *****************************************************************************/
1056 * This function checks if the driver got a valid device from the caller to
1057 * avoid dereferencing invalid pointers.
1059 static bool check_device(struct device *dev)
1061 if (!dev || !dev->dma_mask)
1068 * In this function the list of preallocated protection domains is traversed to
1069 * find the domain for a specific device
1071 static struct dma_ops_domain *find_protection_domain(u16 devid)
1073 struct dma_ops_domain *entry, *ret = NULL;
1074 unsigned long flags;
1076 if (list_empty(&iommu_pd_list))
1079 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1081 list_for_each_entry(entry, &iommu_pd_list, list) {
1082 if (entry->target_dev == devid) {
1088 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1094 * In the dma_ops path we only have the struct device. This function
1095 * finds the corresponding IOMMU, the protection domain and the
1096 * requestor id for a given device.
1097 * If the device is not yet associated with a domain this is also done
1100 static int get_device_resources(struct device *dev,
1101 struct amd_iommu **iommu,
1102 struct protection_domain **domain,
1105 struct dma_ops_domain *dma_dom;
1106 struct pci_dev *pcidev;
1113 if (dev->bus != &pci_bus_type)
1116 pcidev = to_pci_dev(dev);
1117 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1119 /* device not translated by any IOMMU in the system? */
1120 if (_bdf > amd_iommu_last_bdf)
1123 *bdf = amd_iommu_alias_table[_bdf];
1125 *iommu = amd_iommu_rlookup_table[*bdf];
1128 *domain = domain_for_device(*bdf);
1129 if (*domain == NULL) {
1130 dma_dom = find_protection_domain(*bdf);
1132 dma_dom = (*iommu)->default_dom;
1133 *domain = &dma_dom->domain;
1134 attach_device(*iommu, *domain, *bdf);
1135 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1136 "device %s\n", (*domain)->id, dev_name(dev));
1139 if (domain_for_device(_bdf) == NULL)
1140 attach_device(*iommu, *domain, _bdf);
1146 * This is the generic map function. It maps one 4kb page at paddr to
1147 * the given address in the DMA address space for the domain.
1149 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1150 struct dma_ops_domain *dom,
1151 unsigned long address,
1157 WARN_ON(address > dom->aperture_size);
1161 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1162 pte += IOMMU_PTE_L0_INDEX(address);
1164 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1166 if (direction == DMA_TO_DEVICE)
1167 __pte |= IOMMU_PTE_IR;
1168 else if (direction == DMA_FROM_DEVICE)
1169 __pte |= IOMMU_PTE_IW;
1170 else if (direction == DMA_BIDIRECTIONAL)
1171 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1177 return (dma_addr_t)address;
1181 * The generic unmapping function for on page in the DMA address space.
1183 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1184 struct dma_ops_domain *dom,
1185 unsigned long address)
1189 if (address >= dom->aperture_size)
1192 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1194 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1195 pte += IOMMU_PTE_L0_INDEX(address);
1203 * This function contains common code for mapping of a physically
1204 * contiguous memory region into DMA address space. It is used by all
1205 * mapping functions provided with this IOMMU driver.
1206 * Must be called with the domain lock held.
1208 static dma_addr_t __map_single(struct device *dev,
1209 struct amd_iommu *iommu,
1210 struct dma_ops_domain *dma_dom,
1217 dma_addr_t offset = paddr & ~PAGE_MASK;
1218 dma_addr_t address, start;
1220 unsigned long align_mask = 0;
1223 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1227 INC_STATS_COUNTER(cross_page);
1230 align_mask = (1UL << get_order(size)) - 1;
1232 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1234 if (unlikely(address == bad_dma_address))
1238 for (i = 0; i < pages; ++i) {
1239 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1245 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1246 iommu_flush_tlb(iommu, dma_dom->domain.id);
1247 dma_dom->need_flush = false;
1248 } else if (unlikely(iommu_has_npcache(iommu)))
1249 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1256 * Does the reverse of the __map_single function. Must be called with
1257 * the domain lock held too
1259 static void __unmap_single(struct amd_iommu *iommu,
1260 struct dma_ops_domain *dma_dom,
1261 dma_addr_t dma_addr,
1265 dma_addr_t i, start;
1268 if ((dma_addr == bad_dma_address) ||
1269 (dma_addr + size > dma_dom->aperture_size))
1272 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1273 dma_addr &= PAGE_MASK;
1276 for (i = 0; i < pages; ++i) {
1277 dma_ops_domain_unmap(iommu, dma_dom, start);
1281 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1283 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1284 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1285 dma_dom->need_flush = false;
1290 * The exported map_single function for dma_ops.
1292 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1293 size_t size, int dir)
1295 unsigned long flags;
1296 struct amd_iommu *iommu;
1297 struct protection_domain *domain;
1302 INC_STATS_COUNTER(cnt_map_single);
1304 if (!check_device(dev))
1305 return bad_dma_address;
1307 dma_mask = *dev->dma_mask;
1309 get_device_resources(dev, &iommu, &domain, &devid);
1311 if (iommu == NULL || domain == NULL)
1312 /* device not handled by any AMD IOMMU */
1313 return (dma_addr_t)paddr;
1315 if (!dma_ops_domain(domain))
1316 return bad_dma_address;
1318 spin_lock_irqsave(&domain->lock, flags);
1319 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1321 if (addr == bad_dma_address)
1324 iommu_completion_wait(iommu);
1327 spin_unlock_irqrestore(&domain->lock, flags);
1333 * The exported unmap_single function for dma_ops.
1335 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1336 size_t size, int dir)
1338 unsigned long flags;
1339 struct amd_iommu *iommu;
1340 struct protection_domain *domain;
1343 INC_STATS_COUNTER(cnt_unmap_single);
1345 if (!check_device(dev) ||
1346 !get_device_resources(dev, &iommu, &domain, &devid))
1347 /* device not handled by any AMD IOMMU */
1350 if (!dma_ops_domain(domain))
1353 spin_lock_irqsave(&domain->lock, flags);
1355 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1357 iommu_completion_wait(iommu);
1359 spin_unlock_irqrestore(&domain->lock, flags);
1363 * This is a special map_sg function which is used if we should map a
1364 * device which is not handled by an AMD IOMMU in the system.
1366 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1367 int nelems, int dir)
1369 struct scatterlist *s;
1372 for_each_sg(sglist, s, nelems, i) {
1373 s->dma_address = (dma_addr_t)sg_phys(s);
1374 s->dma_length = s->length;
1381 * The exported map_sg function for dma_ops (handles scatter-gather
1384 static int map_sg(struct device *dev, struct scatterlist *sglist,
1385 int nelems, int dir)
1387 unsigned long flags;
1388 struct amd_iommu *iommu;
1389 struct protection_domain *domain;
1392 struct scatterlist *s;
1394 int mapped_elems = 0;
1397 INC_STATS_COUNTER(cnt_map_sg);
1399 if (!check_device(dev))
1402 dma_mask = *dev->dma_mask;
1404 get_device_resources(dev, &iommu, &domain, &devid);
1406 if (!iommu || !domain)
1407 return map_sg_no_iommu(dev, sglist, nelems, dir);
1409 if (!dma_ops_domain(domain))
1412 spin_lock_irqsave(&domain->lock, flags);
1414 for_each_sg(sglist, s, nelems, i) {
1417 s->dma_address = __map_single(dev, iommu, domain->priv,
1418 paddr, s->length, dir, false,
1421 if (s->dma_address) {
1422 s->dma_length = s->length;
1428 iommu_completion_wait(iommu);
1431 spin_unlock_irqrestore(&domain->lock, flags);
1433 return mapped_elems;
1435 for_each_sg(sglist, s, mapped_elems, i) {
1437 __unmap_single(iommu, domain->priv, s->dma_address,
1438 s->dma_length, dir);
1439 s->dma_address = s->dma_length = 0;
1448 * The exported map_sg function for dma_ops (handles scatter-gather
1451 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1452 int nelems, int dir)
1454 unsigned long flags;
1455 struct amd_iommu *iommu;
1456 struct protection_domain *domain;
1457 struct scatterlist *s;
1461 INC_STATS_COUNTER(cnt_unmap_sg);
1463 if (!check_device(dev) ||
1464 !get_device_resources(dev, &iommu, &domain, &devid))
1467 if (!dma_ops_domain(domain))
1470 spin_lock_irqsave(&domain->lock, flags);
1472 for_each_sg(sglist, s, nelems, i) {
1473 __unmap_single(iommu, domain->priv, s->dma_address,
1474 s->dma_length, dir);
1475 s->dma_address = s->dma_length = 0;
1478 iommu_completion_wait(iommu);
1480 spin_unlock_irqrestore(&domain->lock, flags);
1484 * The exported alloc_coherent function for dma_ops.
1486 static void *alloc_coherent(struct device *dev, size_t size,
1487 dma_addr_t *dma_addr, gfp_t flag)
1489 unsigned long flags;
1491 struct amd_iommu *iommu;
1492 struct protection_domain *domain;
1495 u64 dma_mask = dev->coherent_dma_mask;
1497 INC_STATS_COUNTER(cnt_alloc_coherent);
1499 if (!check_device(dev))
1502 if (!get_device_resources(dev, &iommu, &domain, &devid))
1503 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1506 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1510 paddr = virt_to_phys(virt_addr);
1512 if (!iommu || !domain) {
1513 *dma_addr = (dma_addr_t)paddr;
1517 if (!dma_ops_domain(domain))
1521 dma_mask = *dev->dma_mask;
1523 spin_lock_irqsave(&domain->lock, flags);
1525 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1526 size, DMA_BIDIRECTIONAL, true, dma_mask);
1528 if (*dma_addr == bad_dma_address)
1531 iommu_completion_wait(iommu);
1533 spin_unlock_irqrestore(&domain->lock, flags);
1539 free_pages((unsigned long)virt_addr, get_order(size));
1545 * The exported free_coherent function for dma_ops.
1547 static void free_coherent(struct device *dev, size_t size,
1548 void *virt_addr, dma_addr_t dma_addr)
1550 unsigned long flags;
1551 struct amd_iommu *iommu;
1552 struct protection_domain *domain;
1555 INC_STATS_COUNTER(cnt_free_coherent);
1557 if (!check_device(dev))
1560 get_device_resources(dev, &iommu, &domain, &devid);
1562 if (!iommu || !domain)
1565 if (!dma_ops_domain(domain))
1568 spin_lock_irqsave(&domain->lock, flags);
1570 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1572 iommu_completion_wait(iommu);
1574 spin_unlock_irqrestore(&domain->lock, flags);
1577 free_pages((unsigned long)virt_addr, get_order(size));
1581 * This function is called by the DMA layer to find out if we can handle a
1582 * particular device. It is part of the dma_ops.
1584 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1587 struct pci_dev *pcidev;
1589 /* No device or no PCI device */
1590 if (!dev || dev->bus != &pci_bus_type)
1593 pcidev = to_pci_dev(dev);
1595 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1597 /* Out of our scope? */
1598 if (bdf > amd_iommu_last_bdf)
1605 * The function for pre-allocating protection domains.
1607 * If the driver core informs the DMA layer if a driver grabs a device
1608 * we don't need to preallocate the protection domains anymore.
1609 * For now we have to.
1611 void prealloc_protection_domains(void)
1613 struct pci_dev *dev = NULL;
1614 struct dma_ops_domain *dma_dom;
1615 struct amd_iommu *iommu;
1616 int order = amd_iommu_aperture_order;
1619 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1620 devid = calc_devid(dev->bus->number, dev->devfn);
1621 if (devid > amd_iommu_last_bdf)
1623 devid = amd_iommu_alias_table[devid];
1624 if (domain_for_device(devid))
1626 iommu = amd_iommu_rlookup_table[devid];
1629 dma_dom = dma_ops_domain_alloc(iommu, order);
1632 init_unity_mappings_for_device(dma_dom, devid);
1633 dma_dom->target_dev = devid;
1635 list_add_tail(&dma_dom->list, &iommu_pd_list);
1639 static struct dma_mapping_ops amd_iommu_dma_ops = {
1640 .alloc_coherent = alloc_coherent,
1641 .free_coherent = free_coherent,
1642 .map_single = map_single,
1643 .unmap_single = unmap_single,
1645 .unmap_sg = unmap_sg,
1646 .dma_supported = amd_iommu_dma_supported,
1650 * The function which clues the AMD IOMMU driver into dma_ops.
1652 int __init amd_iommu_init_dma_ops(void)
1654 struct amd_iommu *iommu;
1655 int order = amd_iommu_aperture_order;
1659 * first allocate a default protection domain for every IOMMU we
1660 * found in the system. Devices not assigned to any other
1661 * protection domain will be assigned to the default one.
1663 list_for_each_entry(iommu, &amd_iommu_list, list) {
1664 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1665 if (iommu->default_dom == NULL)
1667 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1668 ret = iommu_init_unity_mappings(iommu);
1674 * If device isolation is enabled, pre-allocate the protection
1675 * domains for each device.
1677 if (amd_iommu_isolate)
1678 prealloc_protection_domains();
1682 bad_dma_address = 0;
1683 #ifdef CONFIG_GART_IOMMU
1684 gart_iommu_aperture_disabled = 1;
1685 gart_iommu_aperture = 0;
1688 /* Make the driver finally visible to the drivers */
1689 dma_ops = &amd_iommu_dma_ops;
1691 #ifdef CONFIG_IOMMU_API
1692 register_iommu(&amd_iommu_ops);
1695 bus_register_notifier(&pci_bus_type, &device_nb);
1697 amd_iommu_stats_init();
1703 list_for_each_entry(iommu, &amd_iommu_list, list) {
1704 if (iommu->default_dom)
1705 dma_ops_domain_free(iommu->default_dom);
1711 /*****************************************************************************
1713 * The following functions belong to the exported interface of AMD IOMMU
1715 * This interface allows access to lower level functions of the IOMMU
1716 * like protection domain handling and assignement of devices to domains
1717 * which is not possible with the dma_ops interface.
1719 *****************************************************************************/
1721 #ifdef CONFIG_IOMMU_API
1723 static void cleanup_domain(struct protection_domain *domain)
1725 unsigned long flags;
1728 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1730 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1731 if (amd_iommu_pd_table[devid] == domain)
1732 __detach_device(domain, devid);
1734 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1737 static int amd_iommu_domain_init(struct iommu_domain *dom)
1739 struct protection_domain *domain;
1741 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1745 spin_lock_init(&domain->lock);
1746 domain->mode = PAGE_MODE_3_LEVEL;
1747 domain->id = domain_id_alloc();
1750 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1751 if (!domain->pt_root)
1764 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1766 struct protection_domain *domain = dom->priv;
1771 if (domain->dev_cnt > 0)
1772 cleanup_domain(domain);
1774 BUG_ON(domain->dev_cnt != 0);
1776 free_pagetable(domain);
1778 domain_id_free(domain->id);
1785 static void amd_iommu_detach_device(struct iommu_domain *dom,
1788 struct protection_domain *domain = dom->priv;
1789 struct amd_iommu *iommu;
1790 struct pci_dev *pdev;
1793 if (dev->bus != &pci_bus_type)
1796 pdev = to_pci_dev(dev);
1798 devid = calc_devid(pdev->bus->number, pdev->devfn);
1801 detach_device(domain, devid);
1803 iommu = amd_iommu_rlookup_table[devid];
1807 iommu_queue_inv_dev_entry(iommu, devid);
1808 iommu_completion_wait(iommu);
1811 static int amd_iommu_attach_device(struct iommu_domain *dom,
1814 struct protection_domain *domain = dom->priv;
1815 struct protection_domain *old_domain;
1816 struct amd_iommu *iommu;
1817 struct pci_dev *pdev;
1820 if (dev->bus != &pci_bus_type)
1823 pdev = to_pci_dev(dev);
1825 devid = calc_devid(pdev->bus->number, pdev->devfn);
1827 if (devid >= amd_iommu_last_bdf ||
1828 devid != amd_iommu_alias_table[devid])
1831 iommu = amd_iommu_rlookup_table[devid];
1835 old_domain = domain_for_device(devid);
1839 attach_device(iommu, domain, devid);
1841 iommu_completion_wait(iommu);
1846 static int amd_iommu_map_range(struct iommu_domain *dom,
1847 unsigned long iova, phys_addr_t paddr,
1848 size_t size, int iommu_prot)
1850 struct protection_domain *domain = dom->priv;
1851 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1855 if (iommu_prot & IOMMU_READ)
1856 prot |= IOMMU_PROT_IR;
1857 if (iommu_prot & IOMMU_WRITE)
1858 prot |= IOMMU_PROT_IW;
1863 for (i = 0; i < npages; ++i) {
1864 ret = iommu_map_page(domain, iova, paddr, prot);
1875 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1876 unsigned long iova, size_t size)
1879 struct protection_domain *domain = dom->priv;
1880 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1884 for (i = 0; i < npages; ++i) {
1885 iommu_unmap_page(domain, iova);
1889 iommu_flush_domain(domain->id);
1892 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1895 struct protection_domain *domain = dom->priv;
1896 unsigned long offset = iova & ~PAGE_MASK;
1900 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1902 if (!IOMMU_PTE_PRESENT(*pte))
1905 pte = IOMMU_PTE_PAGE(*pte);
1906 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1908 if (!IOMMU_PTE_PRESENT(*pte))
1911 pte = IOMMU_PTE_PAGE(*pte);
1912 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1914 if (!IOMMU_PTE_PRESENT(*pte))
1917 paddr = *pte & IOMMU_PAGE_MASK;
1923 static struct iommu_ops amd_iommu_ops = {
1924 .domain_init = amd_iommu_domain_init,
1925 .domain_destroy = amd_iommu_domain_destroy,
1926 .attach_dev = amd_iommu_attach_device,
1927 .detach_dev = amd_iommu_detach_device,
1928 .map = amd_iommu_map_range,
1929 .unmap = amd_iommu_unmap_range,
1930 .iova_to_phys = amd_iommu_iova_to_phys,