2 * Firmware replacement code.
4 * Work around broken BIOSes that don't set an aperture or only set the
5 * aperture in the AGP bridge.
6 * If all fails map the aperture over some low memory. This is cheaper than
7 * doing bounce buffering. The memory is lost. This is done at early boot
8 * because only the bootmem allocator can allocate 32+MB.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/init.h>
15 #include <linux/bootmem.h>
16 #include <linux/mmzone.h>
17 #include <linux/pci_ids.h>
18 #include <linux/pci.h>
19 #include <linux/bitops.h>
20 #include <linux/ioport.h>
21 #include <linux/suspend.h>
25 #include <asm/pci-direct.h>
29 int gart_iommu_aperture;
30 int gart_iommu_aperture_disabled __initdata;
31 int gart_iommu_aperture_allowed __initdata;
33 int fallback_aper_order __initdata = 1; /* 64MB */
34 int fallback_aper_force __initdata;
36 int fix_aperture __initdata = 1;
38 static struct resource gart_resource = {
40 .flags = IORESOURCE_MEM,
43 static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
45 gart_resource.start = aper_base;
46 gart_resource.end = aper_base + aper_size - 1;
47 insert_resource(&iomem_resource, &gart_resource);
50 /* This code runs before the PCI subsystem is initialized, so just
51 access the northbridge directly. */
53 static u32 __init allocate_aperture(void)
58 /* aper_size should <= 1G */
59 if (fallback_aper_order > 5)
60 fallback_aper_order = 5;
61 aper_size = (32 * 1024 * 1024) << fallback_aper_order;
64 * Aperture has to be naturally aligned. This means a 2GB aperture
65 * won't have much chance of finding a place in the lower 4GB of
66 * memory. Unfortunately we cannot move it up because that would
67 * make the IOMMU useless.
70 * using 512M as goal, in case kexec will load kernel_big
71 * that will do the on position decompress, and could overlap with
72 * that positon with gart that is used.
75 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
76 * ==> kernel_small(gart area become e820_reserved)
77 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
78 * ==> kerne_big (uncompressed size will be big than 64M or 128M)
79 * so don't use 512M below as gart iommu, leave the space for kernel
82 p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20);
83 if (!p || __pa(p)+aper_size > 0xffffffff) {
85 "Cannot allocate aperture memory hole (%p,%uK)\n",
88 free_bootmem(__pa(p), aper_size);
91 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
92 aper_size >> 10, __pa(p));
93 insert_aperture_resource((u32)__pa(p), aper_size);
94 register_nosave_region((u32)__pa(p) >> PAGE_SHIFT,
95 (u32)__pa(p+aper_size) >> PAGE_SHIFT);
100 static int __init aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
105 if (aper_base + aper_size > 0x100000000UL) {
106 printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
109 if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
110 printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
113 if (aper_size < min_size) {
114 printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n",
115 aper_size>>20, min_size>>20);
122 /* Find a PCI capability */
123 static __u32 __init find_cap(int num, int slot, int func, int cap)
128 if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
129 PCI_STATUS_CAP_LIST))
132 pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
133 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
137 id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
142 pos = read_pci_config_byte(num, slot, func,
143 pos+PCI_CAP_LIST_NEXT);
148 /* Read a standard AGPv3 bridge header */
149 static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
154 u32 aper_low, aper_hi;
158 printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func);
159 apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
160 if (apsizereg == 0xffffffff) {
161 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
165 /* old_order could be the value from NB gart setting */
168 apsize = apsizereg & 0xfff;
169 /* Some BIOS use weird encodings not in the AGPv3 table. */
172 nbits = hweight16(apsize);
174 if ((int)*order < 0) /* < 32MB */
177 aper_low = read_pci_config(num, slot, func, 0x10);
178 aper_hi = read_pci_config(num, slot, func, 0x14);
179 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
182 * On some sick chips, APSIZE is 0. It means it wants 4G
183 * so let double check that order, and lets trust AMD NB settings:
185 printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n",
186 aper, 32 << old_order);
187 if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
188 printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
189 32 << *order, apsizereg);
193 printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
194 aper, 32 << *order, apsizereg);
196 if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
202 * Look for an AGP bridge. Windows only expects the aperture in the
203 * AGP bridge and some BIOS forget to initialize the Northbridge too.
204 * Work around this here.
206 * Do an PCI bus scan by hand because we're running before the PCI
209 * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
210 * generically. It's probably overkill to always scan all slots because
211 * the AGP bridges should be always an own bus on the HT hierarchy,
212 * but do it here for future safety.
214 static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
218 /* Poor man's PCI discovery */
219 for (num = 0; num < 256; num++) {
220 for (slot = 0; slot < 32; slot++) {
221 for (func = 0; func < 8; func++) {
224 class = read_pci_config(num, slot, func,
226 if (class == 0xffffffff)
229 switch (class >> 16) {
230 case PCI_CLASS_BRIDGE_HOST:
231 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
233 cap = find_cap(num, slot, func,
238 return read_agp(num, slot, func, cap,
242 /* No multi-function device? */
243 type = read_pci_config_byte(num, slot, func,
250 printk(KERN_INFO "No AGP bridge found\n");
255 static int gart_fix_e820 __initdata = 1;
257 static int __init parse_gart_mem(char *p)
262 if (!strncmp(p, "off", 3))
264 else if (!strncmp(p, "on", 2))
269 early_param("gart_fix_e820", parse_gart_mem);
271 void __init early_gart_iommu_check(void)
274 * in case it is enabled before, esp for kexec/kdump,
275 * previous kernel already enable that. memset called
276 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
277 * or second kernel have different position for GART hole. and new
278 * kernel could use hole as RAM that is still used by GART set by
280 * or BIOS forget to put that in reserved.
281 * try to update e820 to make that region as reserved.
285 u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
286 u64 aper_base = 0, last_aper_base = 0;
287 int aper_enabled = 0, last_aper_enabled = 0;
289 if (!early_pci_allowed())
293 for (num = 24; num < 32; num++) {
294 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
297 ctl = read_pci_config(0, num, 3, 0x90);
298 aper_enabled = ctl & 1;
299 aper_order = (ctl >> 1) & 7;
300 aper_size = (32 * 1024 * 1024) << aper_order;
301 aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
304 if ((last_aper_order && aper_order != last_aper_order) ||
305 (last_aper_base && aper_base != last_aper_base) ||
306 (last_aper_enabled && aper_enabled != last_aper_enabled)) {
310 last_aper_order = aper_order;
311 last_aper_base = aper_base;
312 last_aper_enabled = aper_enabled;
315 if (!fix && !aper_enabled)
318 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
321 if (gart_fix_e820 && !fix && aper_enabled) {
322 if (!e820_all_mapped(aper_base, aper_base + aper_size,
324 /* reserved it, so we can resuse it in second kernel */
325 printk(KERN_INFO "update e820 for GART\n");
326 add_memory_region(aper_base, aper_size, E820_RESERVED);
332 /* different nodes have different setting, disable them all at first*/
333 for (num = 24; num < 32; num++) {
334 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
337 ctl = read_pci_config(0, num, 3, 0x90);
339 write_pci_config(0, num, 3, 0x90, ctl);
344 static int __initdata printed_gart_size_msg;
346 void __init gart_iommu_hole_init(void)
348 u32 agp_aper_base = 0, agp_aper_order = 0;
349 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
350 u64 aper_base, last_aper_base = 0;
351 int fix, num, valid_agp = 0;
354 if (gart_iommu_aperture_disabled || !fix_aperture ||
355 !early_pci_allowed())
358 printk(KERN_INFO "Checking aperture...\n");
360 if (!fallback_aper_force)
361 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
365 for (num = 24; num < 32; num++) {
366 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
370 gart_iommu_aperture = 1;
372 aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
373 aper_size = (32 * 1024 * 1024) << aper_order;
374 aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
377 printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
378 node, aper_base, aper_size >> 20);
381 if (!aperture_valid(aper_base, aper_size, 64<<20)) {
382 if (valid_agp && agp_aper_base &&
383 agp_aper_base == aper_base &&
384 agp_aper_order == aper_order) {
385 /* the same between two setting from NB and agp */
386 if (!no_iommu && end_pfn > MAX_DMA32_PFN && !printed_gart_size_msg) {
387 printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
388 printk(KERN_ERR "please increase GART size in your BIOS setup\n");
389 printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
390 printed_gart_size_msg = 1;
398 if ((last_aper_order && aper_order != last_aper_order) ||
399 (last_aper_base && aper_base != last_aper_base)) {
403 last_aper_order = aper_order;
404 last_aper_base = aper_base;
407 if (!fix && !fallback_aper_force) {
408 if (last_aper_base) {
409 unsigned long n = (32 * 1024 * 1024) << last_aper_order;
411 insert_aperture_resource((u32)last_aper_base, n);
416 if (!fallback_aper_force) {
417 aper_alloc = agp_aper_base;
418 aper_order = agp_aper_order;
422 /* Got the aperture from the AGP bridge */
423 } else if (swiotlb && !valid_agp) {
425 } else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) ||
428 fallback_aper_force) {
430 "Your BIOS doesn't leave a aperture memory hole\n");
432 "Please enable the IOMMU option in the BIOS setup\n");
434 "This costs you %d MB of RAM\n",
435 32 << fallback_aper_order);
437 aper_order = fallback_aper_order;
438 aper_alloc = allocate_aperture();
441 * Could disable AGP and IOMMU here, but it's
442 * probably not worth it. But the later users
443 * cannot deal with bad apertures and turning
444 * on the aperture over memory causes very
445 * strange problems, so it's better to panic
448 panic("Not enough memory for aperture");
454 /* Fix up the north bridges */
455 for (num = 24; num < 32; num++) {
456 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
460 * Don't enable translation yet. That is done later.
461 * Assume this BIOS didn't initialise the GART so
462 * just overwrite all previous bits
464 write_pci_config(0, num, 3, 0x90, aper_order<<1);
465 write_pci_config(0, num, 3, 0x94, aper_alloc>>25);