2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled;
67 /* Local APIC timer works in C2 */
68 int local_apic_timer_c2_ok;
69 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
71 int first_system_vector = 0xfe;
73 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
76 * Debug level, exported for io_apic.c
82 /* Have we found an MP table */
85 static struct resource lapic_resource = {
87 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
90 static unsigned int calibration_result;
92 static int lapic_next_event(unsigned long delta,
93 struct clock_event_device *evt);
94 static void lapic_timer_setup(enum clock_event_mode mode,
95 struct clock_event_device *evt);
96 static void lapic_timer_broadcast(cpumask_t mask);
97 static void apic_pm_activate(void);
100 * The local apic timer can be used for any function which is CPU local.
102 static struct clock_event_device lapic_clockevent = {
104 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
105 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
107 .set_mode = lapic_timer_setup,
108 .set_next_event = lapic_next_event,
109 .broadcast = lapic_timer_broadcast,
113 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase;
118 static unsigned long apic_phys;
121 * Get the LAPIC version
123 static inline int lapic_get_version(void)
125 return GET_APIC_VERSION(apic_read(APIC_LVR));
129 * Check, if the APIC is integrated or a separate chip
131 static inline int lapic_is_integrated(void)
133 return APIC_INTEGRATED(lapic_get_version());
137 * Check, whether this is a modern or a first generation APIC
139 static int modern_apic(void)
141 /* AMD systems use old APIC versions, so check the CPU */
142 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
143 boot_cpu_data.x86 >= 0xf)
145 return lapic_get_version() >= 0x14;
148 void apic_wait_icr_idle(void)
150 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
154 u32 safe_apic_wait_icr_idle(void)
161 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
165 } while (timeout++ < 1000);
171 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
173 void __cpuinit enable_NMI_through_LVT0(void)
175 unsigned int v = APIC_DM_NMI;
177 /* Level triggered for 82489DX */
178 if (!lapic_is_integrated())
179 v |= APIC_LVT_LEVEL_TRIGGER;
180 apic_write(APIC_LVT0, v);
184 * get_physical_broadcast - Get number of physical broadcast IDs
186 int get_physical_broadcast(void)
188 return modern_apic() ? 0xff : 0xf;
192 * lapic_get_maxlvt - get the maximum number of local vector table entries
194 int lapic_get_maxlvt(void)
196 unsigned int v = apic_read(APIC_LVR);
198 /* 82489DXs do not report # of LVT entries. */
199 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
206 /* Clock divisor is set to 16 */
207 #define APIC_DIVISOR 16
210 * This function sets up the local APIC timer, with a timeout of
211 * 'clocks' APIC bus clock. During calibration we actually call
212 * this function twice on the boot CPU, once with a bogus timeout
213 * value, second time for real. The other (noncalibrating) CPUs
214 * call this function only once, with the real, calibrated value.
216 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
218 unsigned int lvtt_value, tmp_value;
220 lvtt_value = LOCAL_TIMER_VECTOR;
222 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
223 if (!lapic_is_integrated())
224 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
227 lvtt_value |= APIC_LVT_MASKED;
229 apic_write(APIC_LVTT, lvtt_value);
234 tmp_value = apic_read(APIC_TDCR);
235 apic_write(APIC_TDCR,
236 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
240 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
244 * Program the next event, relative to now
246 static int lapic_next_event(unsigned long delta,
247 struct clock_event_device *evt)
249 apic_write(APIC_TMICT, delta);
254 * Setup the lapic timer in periodic or oneshot mode
256 static void lapic_timer_setup(enum clock_event_mode mode,
257 struct clock_event_device *evt)
262 /* Lapic used for broadcast ? */
263 if (!local_apic_timer_verify_ok)
266 local_irq_save(flags);
269 case CLOCK_EVT_MODE_PERIODIC:
270 case CLOCK_EVT_MODE_ONESHOT:
271 __setup_APIC_LVTT(calibration_result,
272 mode != CLOCK_EVT_MODE_PERIODIC, 1);
274 case CLOCK_EVT_MODE_UNUSED:
275 case CLOCK_EVT_MODE_SHUTDOWN:
276 v = apic_read(APIC_LVTT);
277 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
278 apic_write(APIC_LVTT, v);
280 case CLOCK_EVT_MODE_RESUME:
281 /* Nothing to do here */
285 local_irq_restore(flags);
289 * Local APIC timer broadcast function
291 static void lapic_timer_broadcast(cpumask_t mask)
294 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
299 * Setup the local APIC timer for this CPU. Copy the initilized values
300 * of the boot CPU and register the clock event in the framework.
302 static void __devinit setup_APIC_timer(void)
304 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
306 memcpy(levt, &lapic_clockevent, sizeof(*levt));
307 levt->cpumask = cpumask_of_cpu(smp_processor_id());
309 clockevents_register_device(levt);
313 * In this functions we calibrate APIC bus clocks to the external timer.
315 * We want to do the calibration only once since we want to have local timer
316 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
319 * This was previously done by reading the PIT/HPET and waiting for a wrap
320 * around to find out, that a tick has elapsed. I have a box, where the PIT
321 * readout is broken, so it never gets out of the wait loop again. This was
322 * also reported by others.
324 * Monitoring the jiffies value is inaccurate and the clockevents
325 * infrastructure allows us to do a simple substitution of the interrupt
328 * The calibration routine also uses the pm_timer when possible, as the PIT
329 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
330 * back to normal later in the boot process).
333 #define LAPIC_CAL_LOOPS (HZ/10)
335 static __initdata int lapic_cal_loops = -1;
336 static __initdata long lapic_cal_t1, lapic_cal_t2;
337 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
338 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
339 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
342 * Temporary interrupt handler.
344 static void __init lapic_cal_handler(struct clock_event_device *dev)
346 unsigned long long tsc = 0;
347 long tapic = apic_read(APIC_TMCCT);
348 unsigned long pm = acpi_pm_read_early();
353 switch (lapic_cal_loops++) {
355 lapic_cal_t1 = tapic;
356 lapic_cal_tsc1 = tsc;
358 lapic_cal_j1 = jiffies;
361 case LAPIC_CAL_LOOPS:
362 lapic_cal_t2 = tapic;
363 lapic_cal_tsc2 = tsc;
364 if (pm < lapic_cal_pm1)
365 pm += ACPI_PM_OVRRUN;
367 lapic_cal_j2 = jiffies;
373 * Setup the boot APIC
375 * Calibrate and verify the result.
377 void __init setup_boot_APIC_clock(void)
379 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
380 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
381 const long pm_thresh = pm_100ms/100;
382 void (*real_handler)(struct clock_event_device *dev);
383 unsigned long deltaj;
385 int pm_referenced = 0;
388 * The local apic timer can be disabled via the kernel
389 * commandline or from the CPU detection code. Register the lapic
390 * timer as a dummy clock event source on SMP systems, so the
391 * broadcast mechanism is used. On UP systems simply ignore it.
393 if (local_apic_timer_disabled) {
394 /* No broadcast on UP ! */
395 if (num_possible_cpus() > 1) {
396 lapic_clockevent.mult = 1;
402 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
403 "calibrating APIC timer ...\n");
407 /* Replace the global interrupt handler */
408 real_handler = global_clock_event->event_handler;
409 global_clock_event->event_handler = lapic_cal_handler;
412 * Setup the APIC counter to 1e9. There is no way the lapic
413 * can underflow in the 100ms detection time frame
415 __setup_APIC_LVTT(1000000000, 0, 0);
417 /* Let the interrupts run */
420 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
425 /* Restore the real event handler */
426 global_clock_event->event_handler = real_handler;
428 /* Build delta t1-t2 as apic timer counts down */
429 delta = lapic_cal_t1 - lapic_cal_t2;
430 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
432 /* Check, if the PM timer is available */
433 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
434 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
440 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
442 if (deltapm > (pm_100ms - pm_thresh) &&
443 deltapm < (pm_100ms + pm_thresh)) {
444 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
446 res = (((u64) deltapm) * mult) >> 22;
447 do_div(res, 1000000);
448 printk(KERN_WARNING "APIC calibration not consistent "
449 "with PM Timer: %ldms instead of 100ms\n",
451 /* Correct the lapic counter value */
452 res = (((u64) delta) * pm_100ms);
453 do_div(res, deltapm);
454 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
455 "%lu (%ld)\n", (unsigned long) res, delta);
461 /* Calculate the scaled math multiplication factor */
462 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
463 lapic_clockevent.shift);
464 lapic_clockevent.max_delta_ns =
465 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
466 lapic_clockevent.min_delta_ns =
467 clockevent_delta2ns(0xF, &lapic_clockevent);
469 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
471 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
472 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
473 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
477 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
478 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
480 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
481 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
484 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
486 calibration_result / (1000000 / HZ),
487 calibration_result % (1000000 / HZ));
489 local_apic_timer_verify_ok = 1;
492 * Do a sanity check on the APIC calibration result
494 if (calibration_result < (1000000 / HZ)) {
497 "APIC frequency too slow, disabling apic timer\n");
498 /* No broadcast on UP ! */
499 if (num_possible_cpus() > 1)
504 /* We trust the pm timer based calibration */
505 if (!pm_referenced) {
506 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
509 * Setup the apic timer manually
511 levt->event_handler = lapic_cal_handler;
512 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
513 lapic_cal_loops = -1;
515 /* Let the interrupts run */
518 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
523 /* Stop the lapic timer */
524 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
529 deltaj = lapic_cal_j2 - lapic_cal_j1;
530 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
532 /* Check, if the jiffies result is consistent */
533 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
534 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
536 local_apic_timer_verify_ok = 0;
540 if (!local_apic_timer_verify_ok) {
542 "APIC timer disabled due to verification failure.\n");
543 /* No broadcast on UP ! */
544 if (num_possible_cpus() == 1)
548 * If nmi_watchdog is set to IO_APIC, we need the
549 * PIT/HPET going. Otherwise register lapic as a dummy
552 if (nmi_watchdog != NMI_IO_APIC)
553 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
555 printk(KERN_WARNING "APIC timer registered as dummy,"
556 " due to nmi_watchdog=%d!\n", nmi_watchdog);
559 /* Setup the lapic or request the broadcast */
563 void __devinit setup_secondary_APIC_clock(void)
569 * The guts of the apic timer interrupt
571 static void local_apic_timer_interrupt(void)
573 int cpu = smp_processor_id();
574 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
577 * Normally we should not be here till LAPIC has been initialized but
578 * in some cases like kdump, its possible that there is a pending LAPIC
579 * timer interrupt from previous kernel's context and is delivered in
580 * new kernel the moment interrupts are enabled.
582 * Interrupts are enabled early and LAPIC is setup much later, hence
583 * its possible that when we get here evt->event_handler is NULL.
584 * Check for event_handler being NULL and discard the interrupt as
587 if (!evt->event_handler) {
589 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
591 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
596 * the NMI deadlock-detector uses this.
598 per_cpu(irq_stat, cpu).apic_timer_irqs++;
600 evt->event_handler(evt);
604 * Local APIC timer interrupt. This is the most natural way for doing
605 * local interrupts, but local timer interrupts can be emulated by
606 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
608 * [ if a single-CPU system runs an SMP kernel then we call the local
609 * interrupt as well. Thus we cannot inline the local irq ... ]
611 void smp_apic_timer_interrupt(struct pt_regs *regs)
613 struct pt_regs *old_regs = set_irq_regs(regs);
616 * NOTE! We'd better ACK the irq immediately,
617 * because timer handling can be slow.
621 * update_process_times() expects us to have done irq_enter().
622 * Besides, if we don't timer interrupts ignore the global
623 * interrupt lock, which is the WrongThing (tm) to do.
626 local_apic_timer_interrupt();
629 set_irq_regs(old_regs);
632 int setup_profiling_timer(unsigned int multiplier)
638 * Setup extended LVT, AMD specific (K8, family 10h)
640 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
641 * MCE interrupts are supported. Thus MCE offset must be set to 0.
644 #define APIC_EILVT_LVTOFF_MCE 0
645 #define APIC_EILVT_LVTOFF_IBS 1
647 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
649 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
650 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
654 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
656 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
657 return APIC_EILVT_LVTOFF_MCE;
660 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
662 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
663 return APIC_EILVT_LVTOFF_IBS;
667 * Local APIC start and shutdown
671 * clear_local_APIC - shutdown the local APIC
673 * This is called, when a CPU is disabled and before rebooting, so the state of
674 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
675 * leftovers during boot.
677 void clear_local_APIC(void)
682 /* APIC hasn't been mapped yet */
686 maxlvt = lapic_get_maxlvt();
688 * Masking an LVT entry can trigger a local APIC error
689 * if the vector is zero. Mask LVTERR first to prevent this.
692 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
693 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
696 * Careful: we have to set masks only first to deassert
697 * any level-triggered sources.
699 v = apic_read(APIC_LVTT);
700 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
701 v = apic_read(APIC_LVT0);
702 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
703 v = apic_read(APIC_LVT1);
704 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
706 v = apic_read(APIC_LVTPC);
707 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
710 /* lets not touch this if we didn't frob it */
711 #ifdef CONFIG_X86_MCE_P4THERMAL
713 v = apic_read(APIC_LVTTHMR);
714 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
718 * Clean APIC state for other OSs:
720 apic_write(APIC_LVTT, APIC_LVT_MASKED);
721 apic_write(APIC_LVT0, APIC_LVT_MASKED);
722 apic_write(APIC_LVT1, APIC_LVT_MASKED);
724 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
726 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
728 #ifdef CONFIG_X86_MCE_P4THERMAL
730 apic_write(APIC_LVTTHMR, APIC_LVT_MASKED);
732 /* Integrated APIC (!82489DX) ? */
733 if (lapic_is_integrated()) {
735 /* Clear ESR due to Pentium errata 3AP and 11AP */
736 apic_write(APIC_ESR, 0);
742 * disable_local_APIC - clear and disable the local APIC
744 void disable_local_APIC(void)
751 * Disable APIC (implies clearing of registers
754 value = apic_read(APIC_SPIV);
755 value &= ~APIC_SPIV_APIC_ENABLED;
756 apic_write(APIC_SPIV, value);
759 * When LAPIC was disabled by the BIOS and enabled by the kernel,
760 * restore the disabled state.
762 if (enabled_via_apicbase) {
765 rdmsr(MSR_IA32_APICBASE, l, h);
766 l &= ~MSR_IA32_APICBASE_ENABLE;
767 wrmsr(MSR_IA32_APICBASE, l, h);
772 * If Linux enabled the LAPIC against the BIOS default disable it down before
773 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
774 * not power-off. Additionally clear all LVT entries before disable_local_APIC
775 * for the case where Linux didn't enable the LAPIC.
777 void lapic_shutdown(void)
784 local_irq_save(flags);
787 if (enabled_via_apicbase)
788 disable_local_APIC();
790 local_irq_restore(flags);
794 * This is to verify that we're looking at a real local APIC.
795 * Check these against your board if the CPUs aren't getting
796 * started for no apparent reason.
798 int __init verify_local_APIC(void)
800 unsigned int reg0, reg1;
803 * The version register is read-only in a real APIC.
805 reg0 = apic_read(APIC_LVR);
806 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
807 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
808 reg1 = apic_read(APIC_LVR);
809 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
812 * The two version reads above should print the same
813 * numbers. If the second one is different, then we
814 * poke at a non-APIC.
820 * Check if the version looks reasonably.
822 reg1 = GET_APIC_VERSION(reg0);
823 if (reg1 == 0x00 || reg1 == 0xff)
825 reg1 = lapic_get_maxlvt();
826 if (reg1 < 0x02 || reg1 == 0xff)
830 * The ID register is read/write in a real APIC.
832 reg0 = apic_read(APIC_ID);
833 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
836 * The next two are just to see if we have sane values.
837 * They're only really relevant if we're in Virtual Wire
838 * compatibility mode, but most boxes are anymore.
840 reg0 = apic_read(APIC_LVT0);
841 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
842 reg1 = apic_read(APIC_LVT1);
843 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
849 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
851 void __init sync_Arb_IDs(void)
854 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
857 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
862 apic_wait_icr_idle();
864 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
866 APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);
870 * An initial setup of the virtual wire mode.
872 void __init init_bsp_APIC(void)
877 * Don't do the setup now if we have a SMP BIOS as the
878 * through-I/O-APIC virtual wire mode might be active.
880 if (smp_found_config || !cpu_has_apic)
884 * Do not trust the local APIC being empty at bootup.
891 value = apic_read(APIC_SPIV);
892 value &= ~APIC_VECTOR_MASK;
893 value |= APIC_SPIV_APIC_ENABLED;
895 /* This bit is reserved on P4/Xeon and should be cleared */
896 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
897 (boot_cpu_data.x86 == 15))
898 value &= ~APIC_SPIV_FOCUS_DISABLED;
900 value |= APIC_SPIV_FOCUS_DISABLED;
901 value |= SPURIOUS_APIC_VECTOR;
902 apic_write(APIC_SPIV, value);
905 * Set up the virtual wire mode.
907 apic_write(APIC_LVT0, APIC_DM_EXTINT);
909 if (!lapic_is_integrated()) /* 82489DX */
910 value |= APIC_LVT_LEVEL_TRIGGER;
911 apic_write(APIC_LVT1, value);
914 static void __cpuinit lapic_setup_esr(void)
916 unsigned long oldvalue, value, maxlvt;
917 if (lapic_is_integrated() && !esr_disable) {
919 maxlvt = lapic_get_maxlvt();
920 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
921 apic_write(APIC_ESR, 0);
922 oldvalue = apic_read(APIC_ESR);
924 /* enables sending errors */
925 value = ERROR_APIC_VECTOR;
926 apic_write(APIC_LVTERR, value);
928 * spec says clear errors after enabling vector.
931 apic_write(APIC_ESR, 0);
932 value = apic_read(APIC_ESR);
933 if (value != oldvalue)
934 apic_printk(APIC_VERBOSE, "ESR value before enabling "
935 "vector: 0x%08lx after: 0x%08lx\n",
940 * Something untraceable is creating bad interrupts on
941 * secondary quads ... for the moment, just leave the
942 * ESR disabled - we can't do anything useful with the
943 * errors anyway - mbligh
945 printk(KERN_INFO "Leaving ESR disabled.\n");
947 printk(KERN_INFO "No ESR for 82489DX.\n");
953 * setup_local_APIC - setup the local APIC
955 void __cpuinit setup_local_APIC(void)
957 unsigned long value, integrated;
960 /* Pound the ESR really hard over the head with a big hammer - mbligh */
962 apic_write(APIC_ESR, 0);
963 apic_write(APIC_ESR, 0);
964 apic_write(APIC_ESR, 0);
965 apic_write(APIC_ESR, 0);
968 integrated = lapic_is_integrated();
971 * Double-check whether this APIC is really registered.
973 if (!apic_id_registered())
977 * Intel recommends to set DFR, LDR and TPR before enabling
978 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
979 * document number 292116). So here it goes...
984 * Set Task Priority to 'accept all'. We never change this
987 value = apic_read(APIC_TASKPRI);
988 value &= ~APIC_TPRI_MASK;
989 apic_write(APIC_TASKPRI, value);
992 * After a crash, we no longer service the interrupts and a pending
993 * interrupt from previous kernel might still have ISR bit set.
995 * Most probably by now CPU has serviced that pending interrupt and
996 * it might not have done the ack_APIC_irq() because it thought,
997 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
998 * does not clear the ISR bit and cpu thinks it has already serivced
999 * the interrupt. Hence a vector might get locked. It was noticed
1000 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1002 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1003 value = apic_read(APIC_ISR + i*0x10);
1004 for (j = 31; j >= 0; j--) {
1011 * Now that we are all set up, enable the APIC
1013 value = apic_read(APIC_SPIV);
1014 value &= ~APIC_VECTOR_MASK;
1018 value |= APIC_SPIV_APIC_ENABLED;
1021 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1022 * certain networking cards. If high frequency interrupts are
1023 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1024 * entry is masked/unmasked at a high rate as well then sooner or
1025 * later IOAPIC line gets 'stuck', no more interrupts are received
1026 * from the device. If focus CPU is disabled then the hang goes
1029 * [ This bug can be reproduced easily with a level-triggered
1030 * PCI Ne2000 networking cards and PII/PIII processors, dual
1034 * Actually disabling the focus CPU check just makes the hang less
1035 * frequent as it makes the interrupt distributon model be more
1036 * like LRU than MRU (the short-term load is more even across CPUs).
1037 * See also the comment in end_level_ioapic_irq(). --macro
1040 /* Enable focus processor (bit==0) */
1041 value &= ~APIC_SPIV_FOCUS_DISABLED;
1044 * Set spurious IRQ vector
1046 value |= SPURIOUS_APIC_VECTOR;
1047 apic_write(APIC_SPIV, value);
1050 * Set up LVT0, LVT1:
1052 * set up through-local-APIC on the BP's LINT0. This is not
1053 * strictly necessary in pure symmetric-IO mode, but sometimes
1054 * we delegate interrupts to the 8259A.
1057 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1059 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1060 if (!smp_processor_id() && (pic_mode || !value)) {
1061 value = APIC_DM_EXTINT;
1062 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1063 smp_processor_id());
1065 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1066 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1067 smp_processor_id());
1069 apic_write(APIC_LVT0, value);
1072 * only the BP should see the LINT1 NMI signal, obviously.
1074 if (!smp_processor_id())
1075 value = APIC_DM_NMI;
1077 value = APIC_DM_NMI | APIC_LVT_MASKED;
1078 if (!integrated) /* 82489DX */
1079 value |= APIC_LVT_LEVEL_TRIGGER;
1080 apic_write(APIC_LVT1, value);
1083 void __cpuinit end_local_APIC_setup(void)
1085 unsigned long value;
1088 /* Disable the local apic timer */
1089 value = apic_read(APIC_LVTT);
1090 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1091 apic_write(APIC_LVTT, value);
1093 setup_apic_nmi_watchdog(NULL);
1098 * Detect and initialize APIC
1100 static int __init detect_init_APIC(void)
1104 /* Disabled by kernel option? */
1108 switch (boot_cpu_data.x86_vendor) {
1109 case X86_VENDOR_AMD:
1110 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1111 (boot_cpu_data.x86 == 15))
1114 case X86_VENDOR_INTEL:
1115 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1116 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1123 if (!cpu_has_apic) {
1125 * Over-ride BIOS and try to enable the local APIC only if
1126 * "lapic" specified.
1128 if (!force_enable_local_apic) {
1129 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1130 "you can enable it with \"lapic\"\n");
1134 * Some BIOSes disable the local APIC in the APIC_BASE
1135 * MSR. This can only be done in software for Intel P6 or later
1136 * and AMD K7 (Model > 1) or later.
1138 rdmsr(MSR_IA32_APICBASE, l, h);
1139 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1141 "Local APIC disabled by BIOS -- reenabling.\n");
1142 l &= ~MSR_IA32_APICBASE_BASE;
1143 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1144 wrmsr(MSR_IA32_APICBASE, l, h);
1145 enabled_via_apicbase = 1;
1149 * The APIC feature bit should now be enabled
1152 features = cpuid_edx(1);
1153 if (!(features & (1 << X86_FEATURE_APIC))) {
1154 printk(KERN_WARNING "Could not enable APIC!\n");
1157 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1158 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1160 /* The BIOS may have set up the APIC at some other address */
1161 rdmsr(MSR_IA32_APICBASE, l, h);
1162 if (l & MSR_IA32_APICBASE_ENABLE)
1163 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1165 printk(KERN_INFO "Found and enabled local APIC!\n");
1172 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1177 * init_apic_mappings - initialize APIC mappings
1179 void __init init_apic_mappings(void)
1182 * If no local APIC can be found then set up a fake all
1183 * zeroes page to simulate the local APIC and another
1184 * one for the IO-APIC.
1186 if (!smp_found_config && detect_init_APIC()) {
1187 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1188 apic_phys = __pa(apic_phys);
1190 apic_phys = mp_lapic_addr;
1192 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1193 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
1197 * Fetch the APIC ID of the BSP in case we have a
1198 * default configuration (or the MP table is broken).
1200 if (boot_cpu_physical_apicid == -1U)
1201 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
1206 * This initializes the IO-APIC and APIC hardware if this is
1210 int apic_version[MAX_APICS];
1212 int __init APIC_init_uniprocessor(void)
1215 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1217 if (!smp_found_config && !cpu_has_apic)
1221 * Complain if the BIOS pretends there is one.
1223 if (!cpu_has_apic &&
1224 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1225 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1226 boot_cpu_physical_apicid);
1227 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1231 verify_local_APIC();
1236 * Hack: In case of kdump, after a crash, kernel might be booting
1237 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1238 * might be zero if read from MP tables. Get it from LAPIC.
1240 #ifdef CONFIG_CRASH_DUMP
1241 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
1243 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1247 #ifdef CONFIG_X86_IO_APIC
1248 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1250 localise_nmi_watchdog();
1251 end_local_APIC_setup();
1252 #ifdef CONFIG_X86_IO_APIC
1253 if (smp_found_config)
1254 if (!skip_ioapic_setup && nr_ioapics)
1263 * Local APIC interrupts
1267 * This interrupt should _never_ happen with our APIC/SMP architecture
1269 void smp_spurious_interrupt(struct pt_regs *regs)
1275 * Check if this really is a spurious interrupt and ACK it
1276 * if it is a vectored one. Just in case...
1277 * Spurious interrupts should not be ACKed.
1279 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1280 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1283 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1284 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1285 "should never happen.\n", smp_processor_id());
1286 __get_cpu_var(irq_stat).irq_spurious_count++;
1291 * This interrupt should never happen with our APIC/SMP architecture
1293 void smp_error_interrupt(struct pt_regs *regs)
1295 unsigned long v, v1;
1298 /* First tickle the hardware, only then report what went on. -- REW */
1299 v = apic_read(APIC_ESR);
1300 apic_write(APIC_ESR, 0);
1301 v1 = apic_read(APIC_ESR);
1303 atomic_inc(&irq_err_count);
1305 /* Here is what the APIC error bits mean:
1308 2: Send accept error
1309 3: Receive accept error
1311 5: Send illegal vector
1312 6: Received illegal vector
1313 7: Illegal register address
1315 printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1316 smp_processor_id(), v , v1);
1321 void __init smp_intr_init(void)
1324 * IRQ0 must be given a fixed assignment and initialized,
1325 * because it's used before the IO-APIC is set up.
1327 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1330 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1331 * IPI, driven by wakeup.
1333 alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1335 /* IPI for invalidation */
1336 alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1338 /* IPI for generic function call */
1339 alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
1341 /* IPI for single call function */
1342 set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
1343 call_function_single_interrupt);
1348 * Initialize APIC interrupts
1350 void __init apic_intr_init(void)
1355 /* self generated IPI for local APIC timer */
1356 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
1358 /* IPI vectors for APIC spurious and error interrupts */
1359 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
1360 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
1362 /* thermal monitor LVT interrupt */
1363 #ifdef CONFIG_X86_MCE_P4THERMAL
1364 alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
1369 * connect_bsp_APIC - attach the APIC to the interrupt system
1371 void __init connect_bsp_APIC(void)
1375 * Do not trust the local APIC being empty at bootup.
1379 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1380 * local APIC to INT and NMI lines.
1382 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1383 "enabling APIC mode.\n");
1391 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1392 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1394 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1397 void disconnect_bsp_APIC(int virt_wire_setup)
1401 * Put the board back into PIC mode (has an effect only on
1402 * certain older boards). Note that APIC interrupts, including
1403 * IPIs, won't work beyond this point! The only exception are
1406 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1407 "entering PIC mode.\n");
1411 /* Go back to Virtual Wire compatibility mode */
1412 unsigned long value;
1414 /* For the spurious interrupt use vector F, and enable it */
1415 value = apic_read(APIC_SPIV);
1416 value &= ~APIC_VECTOR_MASK;
1417 value |= APIC_SPIV_APIC_ENABLED;
1419 apic_write(APIC_SPIV, value);
1421 if (!virt_wire_setup) {
1423 * For LVT0 make it edge triggered, active high,
1424 * external and enabled
1426 value = apic_read(APIC_LVT0);
1427 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1428 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1429 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1430 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1431 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1432 apic_write(APIC_LVT0, value);
1435 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1439 * For LVT1 make it edge triggered, active high, nmi and
1442 value = apic_read(APIC_LVT1);
1444 APIC_MODE_MASK | APIC_SEND_PENDING |
1445 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1446 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1447 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1448 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1449 apic_write(APIC_LVT1, value);
1453 unsigned int __cpuinitdata maxcpus = NR_CPUS;
1455 void __cpuinit generic_processor_info(int apicid, int version)
1459 physid_mask_t phys_cpu;
1464 if (version == 0x0) {
1465 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1466 "fixing up to 0x10. (tell your hw vendor)\n",
1470 apic_version[apicid] = version;
1472 phys_cpu = apicid_to_cpu_present(apicid);
1473 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
1475 if (num_processors >= NR_CPUS) {
1476 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1477 " Processor ignored.\n", NR_CPUS);
1481 if (num_processors >= maxcpus) {
1482 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1483 " Processor ignored.\n", maxcpus);
1488 cpus_complement(tmp_map, cpu_present_map);
1489 cpu = first_cpu(tmp_map);
1491 if (apicid == boot_cpu_physical_apicid)
1493 * x86_bios_cpu_apicid is required to have processors listed
1494 * in same order as logical cpu numbers. Hence the first
1495 * entry is BSP, and so on.
1499 if (apicid > max_physical_apicid)
1500 max_physical_apicid = apicid;
1503 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1504 * but we need to work other dependencies like SMP_SUSPEND etc
1505 * before this can be done without some confusion.
1506 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1507 * - Ashok Raj <ashok.raj@intel.com>
1509 if (max_physical_apicid >= 8) {
1510 switch (boot_cpu_data.x86_vendor) {
1511 case X86_VENDOR_INTEL:
1512 if (!APIC_XAPIC(version)) {
1516 /* If P4 and above fall through */
1517 case X86_VENDOR_AMD:
1522 /* are we being called early in kernel startup? */
1523 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1524 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1525 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1527 cpu_to_apicid[cpu] = apicid;
1528 bios_cpu_apicid[cpu] = apicid;
1530 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1531 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1534 cpu_set(cpu, cpu_possible_map);
1535 cpu_set(cpu, cpu_present_map);
1545 /* r/w apic fields */
1546 unsigned int apic_id;
1547 unsigned int apic_taskpri;
1548 unsigned int apic_ldr;
1549 unsigned int apic_dfr;
1550 unsigned int apic_spiv;
1551 unsigned int apic_lvtt;
1552 unsigned int apic_lvtpc;
1553 unsigned int apic_lvt0;
1554 unsigned int apic_lvt1;
1555 unsigned int apic_lvterr;
1556 unsigned int apic_tmict;
1557 unsigned int apic_tdcr;
1558 unsigned int apic_thmr;
1561 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1563 unsigned long flags;
1566 if (!apic_pm_state.active)
1569 maxlvt = lapic_get_maxlvt();
1571 apic_pm_state.apic_id = apic_read(APIC_ID);
1572 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1573 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1574 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1575 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1576 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1578 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1579 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1580 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1581 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1582 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1583 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1584 #ifdef CONFIG_X86_MCE_P4THERMAL
1586 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1589 local_irq_save(flags);
1590 disable_local_APIC();
1591 local_irq_restore(flags);
1595 static int lapic_resume(struct sys_device *dev)
1598 unsigned long flags;
1601 if (!apic_pm_state.active)
1604 maxlvt = lapic_get_maxlvt();
1606 local_irq_save(flags);
1609 * Make sure the APICBASE points to the right address
1611 * FIXME! This will be wrong if we ever support suspend on
1612 * SMP! We'll need to do this as part of the CPU restore!
1614 rdmsr(MSR_IA32_APICBASE, l, h);
1615 l &= ~MSR_IA32_APICBASE_BASE;
1616 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1617 wrmsr(MSR_IA32_APICBASE, l, h);
1619 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1620 apic_write(APIC_ID, apic_pm_state.apic_id);
1621 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1622 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1623 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1624 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1625 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1626 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1627 #ifdef CONFIG_X86_MCE_P4THERMAL
1629 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1632 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1633 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1634 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1635 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1636 apic_write(APIC_ESR, 0);
1637 apic_read(APIC_ESR);
1638 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1639 apic_write(APIC_ESR, 0);
1640 apic_read(APIC_ESR);
1641 local_irq_restore(flags);
1646 * This device has no shutdown method - fully functioning local APICs
1647 * are needed on every CPU up until machine_halt/restart/poweroff.
1650 static struct sysdev_class lapic_sysclass = {
1652 .resume = lapic_resume,
1653 .suspend = lapic_suspend,
1656 static struct sys_device device_lapic = {
1658 .cls = &lapic_sysclass,
1661 static void __devinit apic_pm_activate(void)
1663 apic_pm_state.active = 1;
1666 static int __init init_lapic_sysfs(void)
1672 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1674 error = sysdev_class_register(&lapic_sysclass);
1676 error = sysdev_register(&device_lapic);
1679 device_initcall(init_lapic_sysfs);
1681 #else /* CONFIG_PM */
1683 static void apic_pm_activate(void) { }
1685 #endif /* CONFIG_PM */
1688 * APIC command line parameters
1690 static int __init parse_lapic(char *arg)
1692 force_enable_local_apic = 1;
1695 early_param("lapic", parse_lapic);
1697 static int __init parse_nolapic(char *arg)
1700 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1703 early_param("nolapic", parse_nolapic);
1705 static int __init parse_disable_lapic_timer(char *arg)
1707 local_apic_timer_disabled = 1;
1710 early_param("nolapic_timer", parse_disable_lapic_timer);
1712 static int __init parse_lapic_timer_c2_ok(char *arg)
1714 local_apic_timer_c2_ok = 1;
1717 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1719 static int __init apic_set_verbosity(char *str)
1721 if (strcmp("debug", str) == 0)
1722 apic_verbosity = APIC_DEBUG;
1723 else if (strcmp("verbose", str) == 0)
1724 apic_verbosity = APIC_VERBOSE;
1727 __setup("apic=", apic_set_verbosity);
1729 static int __init lapic_insert_resource(void)
1734 /* Put local APIC into the resource map. */
1735 lapic_resource.start = apic_phys;
1736 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1737 insert_resource(&iomem_resource, &lapic_resource);
1743 * need call insert after e820_reserve_resources()
1744 * that is using request_resource
1746 late_initcall(lapic_insert_resource);