1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/processor.h>
12 #include <asm/mmu_context.h>
17 #ifdef CONFIG_X86_LOCAL_APIC
18 #include <asm/mpspec.h>
20 #include <mach_apic.h>
25 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
26 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
27 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
28 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
29 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
31 * Segments used for calling PnP BIOS have byte granularity.
32 * They code segments and data segments have fixed 64k limits,
33 * the transfer segment sizes are set at run time.
36 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
38 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
40 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
42 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
44 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
46 * The APM segments have byte granularity and their bases
47 * are set at run time. All have 64k limits.
50 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
52 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
54 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
56 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
57 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
59 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
61 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
63 /* Current gdt points %fs at the "master" per-cpu area: after this,
64 * it's on the real one. */
65 void switch_to_new_gdt(void)
67 struct desc_ptr gdt_descr;
69 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
70 gdt_descr.size = GDT_SIZE - 1;
72 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
75 static int cachesize_override __cpuinitdata = -1;
76 static int disable_x86_serial_nr __cpuinitdata = 1;
78 struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
80 static void __cpuinit default_init(struct cpuinfo_x86 *c)
82 /* Not much we can do here... */
83 /* Check if at least it has cpuid */
84 if (c->cpuid_level == -1) {
85 /* No cpuid. It must be an ancient CPU */
87 strcpy(c->x86_model_id, "486");
89 strcpy(c->x86_model_id, "386");
93 static struct cpu_dev __cpuinitdata default_cpu = {
94 .c_init = default_init,
95 .c_vendor = "Unknown",
97 static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
99 static int __init cachesize_setup(char *str)
101 get_option(&str, &cachesize_override);
104 __setup("cachesize=", cachesize_setup);
106 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
111 if (c->extended_cpuid_level < 0x80000004)
114 v = (unsigned int *) c->x86_model_id;
115 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
116 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
117 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
118 c->x86_model_id[48] = 0;
120 /* Intel chips right-justify this string for some dumb reason;
121 undo that brain damage */
122 p = q = &c->x86_model_id[0];
128 while (q <= &c->x86_model_id[48])
129 *q++ = '\0'; /* Zero-pad the rest */
136 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
138 unsigned int n, dummy, ebx, ecx, edx, l2size;
140 n = c->extended_cpuid_level;
142 if (n >= 0x80000005) {
143 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
144 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
145 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
146 c->x86_cache_size = (ecx>>24) + (edx>>24);
149 if (n < 0x80000006) /* Some chips just has a large L1. */
152 ecx = cpuid_ecx(0x80000006);
155 /* do processor-specific cache resizing */
156 if (this_cpu->c_size_cache)
157 l2size = this_cpu->c_size_cache(c, l2size);
159 /* Allow user to override all this if necessary. */
160 if (cachesize_override != -1)
161 l2size = cachesize_override;
164 return; /* Again, no L2 cache is possible */
166 c->x86_cache_size = l2size;
168 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
173 * Naming convention should be: <Name> [(<Codename>)]
174 * This table only is used unless init_<vendor>() below doesn't set it;
175 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
179 /* Look up CPU names by table lookup. */
180 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
182 struct cpu_model_info *info;
184 if (c->x86_model >= 16)
185 return NULL; /* Range check */
190 info = this_cpu->c_models;
192 while (info && info->family) {
193 if (info->family == c->x86)
194 return info->model_names[c->x86_model];
197 return NULL; /* Not found */
201 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
203 u32 eax, ebx, ecx, edx;
204 int index_msb, core_bits;
206 cpuid(1, &eax, &ebx, &ecx, &edx);
208 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
211 smp_num_siblings = (ebx & 0xff0000) >> 16;
213 if (smp_num_siblings == 1) {
214 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
215 } else if (smp_num_siblings > 1) {
217 if (smp_num_siblings > NR_CPUS) {
218 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
220 smp_num_siblings = 1;
224 index_msb = get_count_order(smp_num_siblings);
225 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
227 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
230 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
232 index_msb = get_count_order(smp_num_siblings);
234 core_bits = get_count_order(c->x86_max_cores);
236 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
237 ((1 << core_bits) - 1);
239 if (c->x86_max_cores > 1)
240 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
246 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
248 char *v = c->x86_vendor_id;
252 for (i = 0; i < X86_VENDOR_NUM; i++) {
254 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
255 (cpu_devs[i]->c_ident[1] &&
256 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
258 this_cpu = cpu_devs[i];
265 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
266 printk(KERN_ERR "CPU: Your system may be unstable.\n");
268 c->x86_vendor = X86_VENDOR_UNKNOWN;
269 this_cpu = &default_cpu;
273 static int __init x86_fxsr_setup(char *s)
275 setup_clear_cpu_cap(X86_FEATURE_FXSR);
276 setup_clear_cpu_cap(X86_FEATURE_XMM);
279 __setup("nofxsr", x86_fxsr_setup);
282 static int __init x86_sep_setup(char *s)
284 setup_clear_cpu_cap(X86_FEATURE_SEP);
287 __setup("nosep", x86_sep_setup);
290 /* Standard macro to see if a specific flag is changeable */
291 static inline int flag_is_changeable_p(u32 flag)
305 : "=&r" (f1), "=&r" (f2)
308 return ((f1^f2) & flag) != 0;
312 /* Probe for the CPUID instruction */
313 static int __cpuinit have_cpuid_p(void)
315 return flag_is_changeable_p(X86_EFLAGS_ID);
318 static void __init early_cpu_support_print(void)
321 struct cpu_dev *cpu_devx;
323 printk("KERNEL supported cpus:\n");
324 for (i = 0; i < X86_VENDOR_NUM; i++) {
325 cpu_devx = cpu_devs[i];
328 for (j = 0; j < 2; j++) {
329 if (!cpu_devx->c_ident[j])
331 printk(" %s %s\n", cpu_devx->c_vendor,
332 cpu_devx->c_ident[j]);
337 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
339 /* Get vendor name */
340 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
341 (unsigned int *)&c->x86_vendor_id[0],
342 (unsigned int *)&c->x86_vendor_id[8],
343 (unsigned int *)&c->x86_vendor_id[4]);
346 /* Intel-defined flags: level 0x00000001 */
347 if (c->cpuid_level >= 0x00000001) {
348 u32 junk, tfms, cap0, misc;
349 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
350 c->x86 = (tfms >> 8) & 0xf;
351 c->x86_model = (tfms >> 4) & 0xf;
352 c->x86_mask = tfms & 0xf;
354 c->x86 += (tfms >> 20) & 0xff;
356 c->x86_model += ((tfms >> 16) & 0xf) << 4;
357 if (cap0 & (1<<19)) {
358 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
359 c->x86_cache_alignment = c->x86_clflush_size;
364 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
369 /* Intel-defined flags: level 0x00000001 */
370 if (c->cpuid_level >= 0x00000001) {
371 u32 capability, excap;
372 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
373 c->x86_capability[0] = capability;
374 c->x86_capability[4] = excap;
377 /* AMD-defined flags: level 0x80000001 */
378 xlvl = cpuid_eax(0x80000000);
379 c->extended_cpuid_level = xlvl;
380 if ((xlvl & 0xffff0000) == 0x80000000) {
381 if (xlvl >= 0x80000001) {
382 c->x86_capability[1] = cpuid_edx(0x80000001);
383 c->x86_capability[6] = cpuid_ecx(0x80000001);
388 * Do minimum CPU detection early.
389 * Fields really needed: vendor, cpuid_level, family, model, mask,
391 * The others are not touched to avoid unwanted side effects.
393 * WARNING: this function is only called on the BP. Don't add code here
394 * that is supposed to run on all CPUs.
396 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
398 c->x86_cache_alignment = 32;
399 c->x86_clflush_size = 32;
404 c->extended_cpuid_level = 0;
406 memset(&c->x86_capability, 0, sizeof c->x86_capability);
414 if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
415 cpu_devs[c->x86_vendor]->c_early_init)
416 cpu_devs[c->x86_vendor]->c_early_init(c);
418 validate_pat_support(c);
421 void __init early_cpu_init(void)
423 struct cpu_vendor_dev *cvdev;
425 for (cvdev = __x86cpuvendor_start; cvdev < __x86cpuvendor_end; cvdev++)
426 cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
428 early_cpu_support_print();
429 early_identify_cpu(&boot_cpu_data);
433 * The NOPL instruction is supposed to exist on all CPUs with
434 * family >= 6, unfortunately, that's not true in practice because
435 * of early VIA chips and (more importantly) broken virtualizers that
436 * are not easy to detect. Hence, probe for it based on first
439 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
441 const u32 nopl_signature = 0x888c53b1; /* Random number */
442 u32 has_nopl = nopl_signature;
444 clear_cpu_cap(c, X86_FEATURE_NOPL);
447 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
449 " .section .fixup,\"ax\"\n"
456 if (has_nopl == nopl_signature)
457 set_cpu_cap(c, X86_FEATURE_NOPL);
461 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
466 c->extended_cpuid_level = 0;
474 if (c->cpuid_level >= 0x00000001) {
475 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
477 c->apicid = phys_pkg_id(c->initial_apicid, 0);
478 c->phys_proc_id = c->initial_apicid;
480 c->apicid = c->initial_apicid;
484 if (c->extended_cpuid_level >= 0x80000004)
485 get_model_name(c); /* Default name */
487 init_scattered_cpuid_features(c);
491 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
493 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
494 /* Disable processor serial number */
495 unsigned long lo, hi;
496 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
498 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
499 printk(KERN_NOTICE "CPU serial number disabled.\n");
500 clear_cpu_cap(c, X86_FEATURE_PN);
502 /* Disabling the serial number may affect the cpuid level */
503 c->cpuid_level = cpuid_eax(0);
507 static int __init x86_serial_nr_setup(char *s)
509 disable_x86_serial_nr = 0;
512 __setup("serialnumber", x86_serial_nr_setup);
517 * This does the hard work of actually picking apart the CPU stuff...
519 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
523 c->loops_per_jiffy = loops_per_jiffy;
524 c->x86_cache_size = -1;
525 c->x86_vendor = X86_VENDOR_UNKNOWN;
526 c->cpuid_level = -1; /* CPUID not detected */
527 c->x86_model = c->x86_mask = 0; /* So far unknown... */
528 c->x86_vendor_id[0] = '\0'; /* Unset */
529 c->x86_model_id[0] = '\0'; /* Unset */
530 c->x86_max_cores = 1;
531 c->x86_clflush_size = 32;
532 memset(&c->x86_capability, 0, sizeof c->x86_capability);
534 if (!have_cpuid_p()) {
536 * First of all, decide if this is a 486 or higher
537 * It's a 486 if we can modify the AC flag
539 if (flag_is_changeable_p(X86_EFLAGS_AC))
547 if (this_cpu->c_identify)
548 this_cpu->c_identify(c);
551 * Vendor-specific initialization. In this section we
552 * canonicalize the feature flags, meaning if there are
553 * features a certain CPU supports which CPUID doesn't
554 * tell us, CPUID claiming incorrect flags, or other bugs,
555 * we handle them here.
557 * At the end of this section, c->x86_capability better
558 * indicate the features this CPU genuinely supports!
560 if (this_cpu->c_init)
563 /* Disable the PN if appropriate */
564 squash_the_stupid_serial_number(c);
567 * The vendor-specific functions might have changed features. Now
568 * we do "generic changes."
571 /* If the model name is still unset, do table lookup. */
572 if (!c->x86_model_id[0]) {
574 p = table_lookup_model(c);
576 strcpy(c->x86_model_id, p);
579 sprintf(c->x86_model_id, "%02x/%02x",
580 c->x86, c->x86_model);
584 * On SMP, boot_cpu_data holds the common feature set between
585 * all CPUs; so make sure that we indicate which features are
586 * common between the CPUs. The first time this routine gets
587 * executed, c == &boot_cpu_data.
589 if (c != &boot_cpu_data) {
590 /* AND the already accumulated flags with these */
591 for (i = 0; i < NCAPINTS; i++)
592 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
595 /* Clear all flags overriden by options */
596 for (i = 0; i < NCAPINTS; i++)
597 c->x86_capability[i] &= ~cleared_cpu_caps[i];
599 /* Init Machine Check Exception if available. */
602 select_idle_routine(c);
605 void __init identify_boot_cpu(void)
607 identify_cpu(&boot_cpu_data);
612 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
614 BUG_ON(c == &boot_cpu_data);
620 static __init int setup_noclflush(char *arg)
622 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
625 __setup("noclflush", setup_noclflush);
627 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
631 if (c->x86_vendor < X86_VENDOR_NUM)
632 vendor = this_cpu->c_vendor;
633 else if (c->cpuid_level >= 0)
634 vendor = c->x86_vendor_id;
636 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
637 printk(KERN_CONT "%s ", vendor);
639 if (c->x86_model_id[0])
640 printk(KERN_CONT "%s", c->x86_model_id);
642 printk(KERN_CONT "%d86", c->x86);
644 if (c->x86_mask || c->cpuid_level >= 0)
645 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
647 printk(KERN_CONT "\n");
650 static __init int setup_disablecpuid(char *arg)
653 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
654 setup_clear_cpu_cap(bit);
659 __setup("clearcpuid=", setup_disablecpuid);
661 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
663 /* Make sure %fs is initialized properly in idle threads */
664 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
666 memset(regs, 0, sizeof(struct pt_regs));
667 regs->fs = __KERNEL_PERCPU;
672 * cpu_init() initializes state that is per-CPU. Some data is already
673 * initialized (naturally) in the bootstrap process, such as the GDT
674 * and IDT. We reload them nevertheless, this function acts as a
675 * 'CPU state barrier', nothing should get across.
677 void __cpuinit cpu_init(void)
679 int cpu = smp_processor_id();
680 struct task_struct *curr = current;
681 struct tss_struct *t = &per_cpu(init_tss, cpu);
682 struct thread_struct *thread = &curr->thread;
684 if (cpu_test_and_set(cpu, cpu_initialized)) {
685 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
686 for (;;) local_irq_enable();
689 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
691 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
692 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
694 load_idt(&idt_descr);
698 * Set up and load the per-CPU TSS and LDT
700 atomic_inc(&init_mm.mm_count);
701 curr->active_mm = &init_mm;
704 enter_lazy_tlb(&init_mm, curr);
707 set_tss_desc(cpu, t);
709 load_LDT(&init_mm.context);
711 #ifdef CONFIG_DOUBLEFAULT
712 /* Set up doublefault TSS pointer in the GDT */
713 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
717 asm volatile ("mov %0, %%gs" : : "r" (0));
719 /* Clear all 6 debug registers: */
728 * Force FPU initialization:
730 current_thread_info()->status = 0;
732 mxcsr_feature_mask_init();
735 #ifdef CONFIG_HOTPLUG_CPU
736 void __cpuinit cpu_uninit(void)
738 int cpu = raw_smp_processor_id();
739 cpu_clear(cpu, cpu_initialized);
742 per_cpu(cpu_tlbstate, cpu).state = 0;
743 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;