1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
24 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
25 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
26 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
27 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
28 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
30 * Segments used for calling PnP BIOS have byte granularity.
31 * They code segments and data segments have fixed 64k limits,
32 * the transfer segment sizes are set at run time.
35 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
37 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
39 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
41 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
43 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
45 * The APM segments have byte granularity and their bases
46 * are set at run time. All have 64k limits.
49 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
51 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
53 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
55 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
56 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
58 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
60 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
62 static int cachesize_override __cpuinitdata = -1;
63 static int disable_x86_fxsr __cpuinitdata;
64 static int disable_x86_serial_nr __cpuinitdata = 1;
65 static int disable_x86_sep __cpuinitdata;
67 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
69 extern int disable_pse;
71 static void __cpuinit default_init(struct cpuinfo_x86 * c)
73 /* Not much we can do here... */
74 /* Check if at least it has cpuid */
75 if (c->cpuid_level == -1) {
76 /* No cpuid. It must be an ancient CPU */
78 strcpy(c->x86_model_id, "486");
80 strcpy(c->x86_model_id, "386");
84 static struct cpu_dev __cpuinitdata default_cpu = {
85 .c_init = default_init,
86 .c_vendor = "Unknown",
88 static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu;
90 static int __init cachesize_setup(char *str)
92 get_option (&str, &cachesize_override);
95 __setup("cachesize=", cachesize_setup);
97 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
102 if (cpuid_eax(0x80000000) < 0x80000004)
105 v = (unsigned int *) c->x86_model_id;
106 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
107 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
108 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
109 c->x86_model_id[48] = 0;
111 /* Intel chips right-justify this string for some dumb reason;
112 undo that brain damage */
113 p = q = &c->x86_model_id[0];
119 while ( q <= &c->x86_model_id[48] )
120 *q++ = '\0'; /* Zero-pad the rest */
127 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
129 unsigned int n, dummy, ecx, edx, l2size;
131 n = cpuid_eax(0x80000000);
133 if (n >= 0x80000005) {
134 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
135 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
136 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
137 c->x86_cache_size=(ecx>>24)+(edx>>24);
140 if (n < 0x80000006) /* Some chips just has a large L1. */
143 ecx = cpuid_ecx(0x80000006);
146 /* do processor-specific cache resizing */
147 if (this_cpu->c_size_cache)
148 l2size = this_cpu->c_size_cache(c,l2size);
150 /* Allow user to override all this if necessary. */
151 if (cachesize_override != -1)
152 l2size = cachesize_override;
155 return; /* Again, no L2 cache is possible */
157 c->x86_cache_size = l2size;
159 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
163 /* Naming convention should be: <Name> [(<Codename>)] */
164 /* This table only is used unless init_<vendor>() below doesn't set it; */
165 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
167 /* Look up CPU names by table lookup. */
168 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
170 struct cpu_model_info *info;
172 if ( c->x86_model >= 16 )
173 return NULL; /* Range check */
178 info = this_cpu->c_models;
180 while (info && info->family) {
181 if (info->family == c->x86)
182 return info->model_names[c->x86_model];
185 return NULL; /* Not found */
189 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
191 char *v = c->x86_vendor_id;
195 for (i = 0; i < X86_VENDOR_NUM; i++) {
197 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
198 (cpu_devs[i]->c_ident[1] &&
199 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
202 this_cpu = cpu_devs[i];
209 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
210 printk(KERN_ERR "CPU: Your system may be unstable.\n");
212 c->x86_vendor = X86_VENDOR_UNKNOWN;
213 this_cpu = &default_cpu;
217 static int __init x86_fxsr_setup(char * s)
219 /* Tell all the other CPUs to not use it... */
220 disable_x86_fxsr = 1;
223 * ... and clear the bits early in the boot_cpu_data
224 * so that the bootup process doesn't try to do this
227 clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability);
228 clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability);
231 __setup("nofxsr", x86_fxsr_setup);
234 static int __init x86_sep_setup(char * s)
239 __setup("nosep", x86_sep_setup);
242 /* Standard macro to see if a specific flag is changeable */
243 static inline int flag_is_changeable_p(u32 flag)
257 : "=&r" (f1), "=&r" (f2)
260 return ((f1^f2) & flag) != 0;
264 /* Probe for the CPUID instruction */
265 static int __cpuinit have_cpuid_p(void)
267 return flag_is_changeable_p(X86_EFLAGS_ID);
270 void __init cpu_detect(struct cpuinfo_x86 *c)
272 /* Get vendor name */
273 cpuid(0x00000000, &c->cpuid_level,
274 (int *)&c->x86_vendor_id[0],
275 (int *)&c->x86_vendor_id[8],
276 (int *)&c->x86_vendor_id[4]);
279 if (c->cpuid_level >= 0x00000001) {
280 u32 junk, tfms, cap0, misc;
281 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
282 c->x86 = (tfms >> 8) & 15;
283 c->x86_model = (tfms >> 4) & 15;
285 c->x86 += (tfms >> 20) & 0xff;
287 c->x86_model += ((tfms >> 16) & 0xF) << 4;
288 c->x86_mask = tfms & 15;
290 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
294 /* Do minimum CPU detection early.
295 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
296 The others are not touched to avoid unwanted side effects.
298 WARNING: this function is only called on the BP. Don't add code here
299 that is supposed to run on all CPUs. */
300 static void __init early_cpu_detect(void)
302 struct cpuinfo_x86 *c = &boot_cpu_data;
304 c->x86_cache_alignment = 32;
311 get_cpu_vendor(c, 1);
313 switch (c->x86_vendor) {
317 case X86_VENDOR_INTEL:
323 static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
328 if (have_cpuid_p()) {
329 /* Get vendor name */
330 cpuid(0x00000000, &c->cpuid_level,
331 (int *)&c->x86_vendor_id[0],
332 (int *)&c->x86_vendor_id[8],
333 (int *)&c->x86_vendor_id[4]);
335 get_cpu_vendor(c, 0);
336 /* Initialize the standard set of capabilities */
337 /* Note that the vendor-specific code below might override */
339 /* Intel-defined flags: level 0x00000001 */
340 if ( c->cpuid_level >= 0x00000001 ) {
341 u32 capability, excap;
342 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
343 c->x86_capability[0] = capability;
344 c->x86_capability[4] = excap;
345 c->x86 = (tfms >> 8) & 15;
346 c->x86_model = (tfms >> 4) & 15;
348 c->x86 += (tfms >> 20) & 0xff;
350 c->x86_model += ((tfms >> 16) & 0xF) << 4;
351 c->x86_mask = tfms & 15;
353 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
355 c->apicid = (ebx >> 24) & 0xFF;
357 if (c->x86_capability[0] & (1<<19))
358 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
360 /* Have CPUID level 0 only - unheard of */
364 /* AMD-defined flags: level 0x80000001 */
365 xlvl = cpuid_eax(0x80000000);
366 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
367 if ( xlvl >= 0x80000001 ) {
368 c->x86_capability[1] = cpuid_edx(0x80000001);
369 c->x86_capability[6] = cpuid_ecx(0x80000001);
371 if ( xlvl >= 0x80000004 )
372 get_model_name(c); /* Default name */
375 init_scattered_cpuid_features(c);
379 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
383 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
385 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
386 /* Disable processor serial number */
388 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
390 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
391 printk(KERN_NOTICE "CPU serial number disabled.\n");
392 clear_bit(X86_FEATURE_PN, c->x86_capability);
394 /* Disabling the serial number may affect the cpuid level */
395 c->cpuid_level = cpuid_eax(0);
399 static int __init x86_serial_nr_setup(char *s)
401 disable_x86_serial_nr = 0;
404 __setup("serialnumber", x86_serial_nr_setup);
409 * This does the hard work of actually picking apart the CPU stuff...
411 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
415 c->loops_per_jiffy = loops_per_jiffy;
416 c->x86_cache_size = -1;
417 c->x86_vendor = X86_VENDOR_UNKNOWN;
418 c->cpuid_level = -1; /* CPUID not detected */
419 c->x86_model = c->x86_mask = 0; /* So far unknown... */
420 c->x86_vendor_id[0] = '\0'; /* Unset */
421 c->x86_model_id[0] = '\0'; /* Unset */
422 c->x86_max_cores = 1;
423 c->x86_clflush_size = 32;
424 memset(&c->x86_capability, 0, sizeof c->x86_capability);
426 if (!have_cpuid_p()) {
427 /* First of all, decide if this is a 486 or higher */
428 /* It's a 486 if we can modify the AC flag */
429 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
437 if (this_cpu->c_identify)
438 this_cpu->c_identify(c);
441 * Vendor-specific initialization. In this section we
442 * canonicalize the feature flags, meaning if there are
443 * features a certain CPU supports which CPUID doesn't
444 * tell us, CPUID claiming incorrect flags, or other bugs,
445 * we handle them here.
447 * At the end of this section, c->x86_capability better
448 * indicate the features this CPU genuinely supports!
450 if (this_cpu->c_init)
453 /* Disable the PN if appropriate */
454 squash_the_stupid_serial_number(c);
457 * The vendor-specific functions might have changed features. Now
458 * we do "generic changes."
463 clear_bit(X86_FEATURE_TSC, c->x86_capability);
466 if (disable_x86_fxsr) {
467 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
468 clear_bit(X86_FEATURE_XMM, c->x86_capability);
473 clear_bit(X86_FEATURE_SEP, c->x86_capability);
476 clear_bit(X86_FEATURE_PSE, c->x86_capability);
478 /* If the model name is still unset, do table lookup. */
479 if ( !c->x86_model_id[0] ) {
481 p = table_lookup_model(c);
483 strcpy(c->x86_model_id, p);
486 sprintf(c->x86_model_id, "%02x/%02x",
487 c->x86, c->x86_model);
491 * On SMP, boot_cpu_data holds the common feature set between
492 * all CPUs; so make sure that we indicate which features are
493 * common between the CPUs. The first time this routine gets
494 * executed, c == &boot_cpu_data.
496 if ( c != &boot_cpu_data ) {
497 /* AND the already accumulated flags with these */
498 for ( i = 0 ; i < NCAPINTS ; i++ )
499 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
502 /* Clear all flags overriden by options */
503 for (i = 0; i < NCAPINTS; i++)
504 c->x86_capability[i] ^= cleared_cpu_caps[i];
506 /* Init Machine Check Exception if available. */
509 select_idle_routine(c);
512 void __init identify_boot_cpu(void)
514 identify_cpu(&boot_cpu_data);
520 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
522 BUG_ON(c == &boot_cpu_data);
529 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
531 u32 eax, ebx, ecx, edx;
532 int index_msb, core_bits;
534 cpuid(1, &eax, &ebx, &ecx, &edx);
536 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
539 smp_num_siblings = (ebx & 0xff0000) >> 16;
541 if (smp_num_siblings == 1) {
542 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
543 } else if (smp_num_siblings > 1 ) {
545 if (smp_num_siblings > NR_CPUS) {
546 printk(KERN_WARNING "CPU: Unsupported number of the "
547 "siblings %d", smp_num_siblings);
548 smp_num_siblings = 1;
552 index_msb = get_count_order(smp_num_siblings);
553 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
555 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
558 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
560 index_msb = get_count_order(smp_num_siblings) ;
562 core_bits = get_count_order(c->x86_max_cores);
564 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
565 ((1 << core_bits) - 1);
567 if (c->x86_max_cores > 1)
568 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
574 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
578 if (c->x86_vendor < X86_VENDOR_NUM)
579 vendor = this_cpu->c_vendor;
580 else if (c->cpuid_level >= 0)
581 vendor = c->x86_vendor_id;
583 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
584 printk("%s ", vendor);
586 if (!c->x86_model_id[0])
587 printk("%d86", c->x86);
589 printk("%s", c->x86_model_id);
591 if (c->x86_mask || c->cpuid_level >= 0)
592 printk(" stepping %02x\n", c->x86_mask);
597 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
600 * We're emulating future behavior.
601 * In the future, the cpu-specific init functions will be called implicitly
602 * via the magic of initcalls.
603 * They will insert themselves into the cpu_devs structure.
604 * Then, when cpu_init() is called, we can just iterate over that array.
607 extern int intel_cpu_init(void);
608 extern int cyrix_init_cpu(void);
609 extern int nsc_init_cpu(void);
610 extern int amd_init_cpu(void);
611 extern int centaur_init_cpu(void);
612 extern int transmeta_init_cpu(void);
613 extern int nexgen_init_cpu(void);
614 extern int umc_init_cpu(void);
616 void __init early_cpu_init(void)
623 transmeta_init_cpu();
628 #ifdef CONFIG_DEBUG_PAGEALLOC
629 /* pse is not compatible with on-the-fly unmapping,
630 * disable it even if the cpus claim to support it.
632 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
637 /* Make sure %fs is initialized properly in idle threads */
638 struct pt_regs * __devinit idle_regs(struct pt_regs *regs)
640 memset(regs, 0, sizeof(struct pt_regs));
641 regs->fs = __KERNEL_PERCPU;
645 /* Current gdt points %fs at the "master" per-cpu area: after this,
646 * it's on the real one. */
647 void switch_to_new_gdt(void)
649 struct desc_ptr gdt_descr;
651 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
652 gdt_descr.size = GDT_SIZE - 1;
653 load_gdt(&gdt_descr);
654 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
658 * cpu_init() initializes state that is per-CPU. Some data is already
659 * initialized (naturally) in the bootstrap process, such as the GDT
660 * and IDT. We reload them nevertheless, this function acts as a
661 * 'CPU state barrier', nothing should get across.
663 void __cpuinit cpu_init(void)
665 int cpu = smp_processor_id();
666 struct task_struct *curr = current;
667 struct tss_struct * t = &per_cpu(init_tss, cpu);
668 struct thread_struct *thread = &curr->thread;
670 if (cpu_test_and_set(cpu, cpu_initialized)) {
671 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
672 for (;;) local_irq_enable();
675 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
677 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
678 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
679 if (tsc_disable && cpu_has_tsc) {
680 printk(KERN_NOTICE "Disabling TSC...\n");
681 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
682 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
683 set_in_cr4(X86_CR4_TSD);
686 load_idt(&idt_descr);
690 * Set up and load the per-CPU TSS and LDT
692 atomic_inc(&init_mm.mm_count);
693 curr->active_mm = &init_mm;
696 enter_lazy_tlb(&init_mm, curr);
701 load_LDT(&init_mm.context);
703 #ifdef CONFIG_DOUBLEFAULT
704 /* Set up doublefault TSS pointer in the GDT */
705 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
709 asm volatile ("mov %0, %%gs" : : "r" (0));
711 /* Clear all 6 debug registers: */
720 * Force FPU initialization:
722 current_thread_info()->status = 0;
724 mxcsr_feature_mask_init();
727 #ifdef CONFIG_HOTPLUG_CPU
728 void __cpuinit cpu_uninit(void)
730 int cpu = raw_smp_processor_id();
731 cpu_clear(cpu, cpu_initialized);
734 per_cpu(cpu_tlbstate, cpu).state = 0;
735 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;