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[linux-2.6-omap-h63xx.git] / arch / x86 / kernel / genx2apic_cluster.c
1 #include <linux/threads.h>
2 #include <linux/cpumask.h>
3 #include <linux/string.h>
4 #include <linux/kernel.h>
5 #include <linux/ctype.h>
6 #include <linux/init.h>
7 #include <asm/smp.h>
8 #include <asm/ipi.h>
9 #include <asm/genapic.h>
10
11 DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
12
13 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
14
15 static cpumask_t x2apic_target_cpus(void)
16 {
17         return cpumask_of_cpu(0);
18 }
19
20 /*
21  * for now each logical cpu is in its own vector allocation domain.
22  */
23 static cpumask_t x2apic_vector_allocation_domain(int cpu)
24 {
25         cpumask_t domain = CPU_MASK_NONE;
26         cpu_set(cpu, domain);
27         return domain;
28 }
29
30 static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
31                                    unsigned int dest)
32 {
33         unsigned long cfg;
34
35         cfg = __prepare_ICR(0, vector, dest);
36
37         /*
38          * send the IPI.
39          */
40         x2apic_icr_write(cfg, apicid);
41 }
42
43 /*
44  * for now, we send the IPI's one by one in the cpumask.
45  * TBD: Based on the cpu mask, we can send the IPI's to the cluster group
46  * at once. We have 16 cpu's in a cluster. This will minimize IPI register
47  * writes.
48  */
49 static void x2apic_send_IPI_mask(cpumask_t mask, int vector)
50 {
51         unsigned long flags;
52         unsigned long query_cpu;
53
54         local_irq_save(flags);
55         for_each_cpu_mask(query_cpu, mask) {
56                 __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_logical_apicid, query_cpu),
57                                        vector, APIC_DEST_LOGICAL);
58         }
59         local_irq_restore(flags);
60 }
61
62 static void x2apic_send_IPI_allbutself(int vector)
63 {
64         cpumask_t mask = cpu_online_map;
65
66         cpu_clear(smp_processor_id(), mask);
67
68         if (!cpus_empty(mask))
69                 x2apic_send_IPI_mask(mask, vector);
70 }
71
72 static void x2apic_send_IPI_all(int vector)
73 {
74         x2apic_send_IPI_mask(cpu_online_map, vector);
75 }
76
77 static int x2apic_apic_id_registered(void)
78 {
79         return 1;
80 }
81
82 static unsigned int x2apic_cpu_mask_to_apicid(cpumask_t cpumask)
83 {
84         int cpu;
85
86         /*
87          * We're using fixed IRQ delivery, can only return one phys APIC ID.
88          * May as well be the first.
89          */
90         cpu = first_cpu(cpumask);
91         if ((unsigned)cpu < NR_CPUS)
92                 return per_cpu(x86_cpu_to_logical_apicid, cpu);
93         else
94                 return BAD_APICID;
95 }
96
97 static unsigned int x2apic_read_id(void)
98 {
99         return apic_read(APIC_ID);
100 }
101
102 static unsigned int phys_pkg_id(int index_msb)
103 {
104         return x2apic_read_id() >> index_msb;
105 }
106
107 static void x2apic_send_IPI_self(int vector)
108 {
109         apic_write(APIC_SELF_IPI, vector);
110 }
111
112 static void init_x2apic_ldr(void)
113 {
114         int cpu = smp_processor_id();
115
116         per_cpu(x86_cpu_to_logical_apicid, cpu) = apic_read(APIC_LDR);
117         return;
118 }
119
120 struct genapic apic_x2apic_cluster = {
121         .name = "cluster x2apic",
122         .int_delivery_mode = dest_LowestPrio,
123         .int_dest_mode = (APIC_DEST_LOGICAL != 0),
124         .target_cpus = x2apic_target_cpus,
125         .vector_allocation_domain = x2apic_vector_allocation_domain,
126         .apic_id_registered = x2apic_apic_id_registered,
127         .init_apic_ldr = init_x2apic_ldr,
128         .send_IPI_all = x2apic_send_IPI_all,
129         .send_IPI_allbutself = x2apic_send_IPI_allbutself,
130         .send_IPI_mask = x2apic_send_IPI_mask,
131         .send_IPI_self = x2apic_send_IPI_self,
132         .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
133         .phys_pkg_id = phys_pkg_id,
134         .read_apic_id = x2apic_read_id,
135 };