arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpu.h>
  14 #include <linux/cpumask.h>
  15 #include <linux/string.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/module.h>
  20 #include <linux/hardirq.h>
  21 #include <linux/timer.h>
  22 #include <linux/proc_fs.h>
  23 #include <asm/current.h>
  24 #include <asm/smp.h>
  25 #include <asm/ipi.h>
  26 #include <asm/genapic.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/uv.h>
  29 #include <asm/uv/uv_mmrs.h>
  30 #include <asm/uv/uv_hub.h>
  31 #include <asm/uv/bios.h>
  32
  33 DEFINE_PER_CPU(int, x2apic_extra_bits);
  34
  35 static enum uv_system_type uv_system_type;
  36
  37 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  38 {
  39         if (!strcmp(oem_id, "SGI")) {
  40                 if (!strcmp(oem_table_id, "UVL"))
  41                         uv_system_type = UV_LEGACY_APIC;
  42                 else if (!strcmp(oem_table_id, "UVX"))
  43                         uv_system_type = UV_X2APIC;
  44                 else if (!strcmp(oem_table_id, "UVH")) {
  45                         uv_system_type = UV_NON_UNIQUE_APIC;
  46                         return 1;
  47                 }
  48         }
  49         return 0;
  50 }
  51
  52 enum uv_system_type get_uv_system_type(void)
  53 {
  54         return uv_system_type;
  55 }
  56
  57 int is_uv_system(void)
  58 {
  59         return uv_system_type != UV_NONE;
  60 }
  61 EXPORT_SYMBOL_GPL(is_uv_system);
  62
  63 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  64 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  65
  66 struct uv_blade_info *uv_blade_info;
  67 EXPORT_SYMBOL_GPL(uv_blade_info);
  68
  69 short *uv_node_to_blade;
  70 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  71
  72 short *uv_cpu_to_blade;
  73 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  74
  75 short uv_possible_blades;
  76 EXPORT_SYMBOL_GPL(uv_possible_blades);
  77
  78 unsigned long sn_rtc_cycles_per_second;
  79 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  80
  81 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  82
  83 static const struct cpumask *uv_target_cpus(void)
  84 {
  85         return cpumask_of(0);
  86 }
  87
  88 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
  89 {
  90         cpumask_clear(retmask);
  91         cpumask_set_cpu(cpu, retmask);
  92 }
  93
  94 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  95 {
  96         unsigned long val;
  97         int pnode;
  98
  99         pnode = uv_apicid_to_pnode(phys_apicid);
 100         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 101             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 102             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 103             APIC_DM_INIT;
 104         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 105         mdelay(10);
 106
 107         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 108             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 109             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 110             APIC_DM_STARTUP;
 111         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 112         return 0;
 113 }
 114
 115 static void uv_send_IPI_one(int cpu, int vector)
 116 {
 117         unsigned long val, apicid, lapicid;
 118         int pnode;
 119
 120         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 121         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
 122         pnode = uv_apicid_to_pnode(apicid);
 123         val =
 124             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
 125                                               UVH_IPI_INT_APIC_ID_SHFT) |
 126             (vector << UVH_IPI_INT_VECTOR_SHFT);
 127         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 128 }
 129
 130 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 131 {
 132         unsigned int cpu;
 133
 134         for_each_cpu(cpu, mask)
 135                 uv_send_IPI_one(cpu, vector);
 136 }
 137
 138 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 139 {
 140         unsigned int cpu;
 141         unsigned int this_cpu = smp_processor_id();
 142
 143         for_each_cpu(cpu, mask)
 144                 if (cpu != this_cpu)
 145                         uv_send_IPI_one(cpu, vector);
 146 }
 147
 148 static void uv_send_IPI_allbutself(int vector)
 149 {
 150         unsigned int cpu;
 151         unsigned int this_cpu = smp_processor_id();
 152
 153         for_each_online_cpu(cpu)
 154                 if (cpu != this_cpu)
 155                         uv_send_IPI_one(cpu, vector);
 156 }
 157
 158 static void uv_send_IPI_all(int vector)
 159 {
 160         uv_send_IPI_mask(cpu_online_mask, vector);
 161 }
 162
 163 static int uv_apic_id_registered(void)
 164 {
 165         return 1;
 166 }
 167
 168 static void uv_init_apic_ldr(void)
 169 {
 170 }
 171
 172 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 173 {
 174         int cpu;
 175
 176         /*
 177          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 178          * May as well be the first.
 179          */
 180         cpu = cpumask_first(cpumask);
 181         if ((unsigned)cpu < nr_cpu_ids)
 182                 return per_cpu(x86_cpu_to_apicid, cpu);
 183         else
 184                 return BAD_APICID;
 185 }
 186
 187 static unsigned int uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 188                                               const struct cpumask *andmask)
 189 {
 190         int cpu;
 191
 192         /*
 193          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 194          * May as well be the first.
 195          */
 196         for_each_cpu_and(cpu, cpumask, andmask)
 197                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 198                         break;
 199         if (cpu < nr_cpu_ids)
 200                 return per_cpu(x86_cpu_to_apicid, cpu);
 201         return BAD_APICID;
 202 }
 203
 204 static unsigned int get_apic_id(unsigned long x)
 205 {
 206         unsigned int id;
 207
 208         WARN_ON(preemptible() && num_online_cpus() > 1);
 209         id = x | __get_cpu_var(x2apic_extra_bits);
 210
 211         return id;
 212 }
 213
 214 static unsigned long set_apic_id(unsigned int id)
 215 {
 216         unsigned long x;
 217
 218         /* maskout x2apic_extra_bits ? */
 219         x = id;
 220         return x;
 221 }
 222
 223 static unsigned int uv_read_apic_id(void)
 224 {
 225
 226         return get_apic_id(apic_read(APIC_ID));
 227 }
 228
 229 static unsigned int phys_pkg_id(int index_msb)
 230 {
 231         return uv_read_apic_id() >> index_msb;
 232 }
 233
 234 static void uv_send_IPI_self(int vector)
 235 {
 236         apic_write(APIC_SELF_IPI, vector);
 237 }
 238
 239 struct genapic apic_x2apic_uv_x = {
 240         .name = "UV large system",
 241         .acpi_madt_oem_check = uv_acpi_madt_oem_check,
 242         .int_delivery_mode = dest_Fixed,
 243         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 244         .target_cpus = uv_target_cpus,
 245         .vector_allocation_domain = uv_vector_allocation_domain,
 246         .apic_id_registered = uv_apic_id_registered,
 247         .init_apic_ldr = uv_init_apic_ldr,
 248         .send_IPI_all = uv_send_IPI_all,
 249         .send_IPI_allbutself = uv_send_IPI_allbutself,
 250         .send_IPI_mask = uv_send_IPI_mask,
 251         .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
 252         .send_IPI_self = uv_send_IPI_self,
 253         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 254         .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
 255         .phys_pkg_id = phys_pkg_id,
 256         .get_apic_id = get_apic_id,
 257         .set_apic_id = set_apic_id,
 258         .apic_id_mask = (0xFFFFFFFFu),
 259 };
 260
 261 static __cpuinit void set_x2apic_extra_bits(int pnode)
 262 {
 263         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 264 }
 265
 266 /*
 267  * Called on boot cpu.
 268  */
 269 static __init int boot_pnode_to_blade(int pnode)
 270 {
 271         int blade;
 272
 273         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 274                 if (pnode == uv_blade_info[blade].pnode)
 275                         return blade;
 276         BUG();
 277 }
 278
 279 struct redir_addr {
 280         unsigned long redirect;
 281         unsigned long alias;
 282 };
 283
 284 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 285
 286 static __initdata struct redir_addr redir_addrs[] = {
 287         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 288         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 289         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 290 };
 291
 292 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 293 {
 294         union uvh_si_alias0_overlay_config_u alias;
 295         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 296         int i;
 297
 298         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 299                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 300                 if (alias.s.base == 0) {
 301                         *size = (1UL << alias.s.m_alias);
 302                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 303                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 304                         return;
 305                 }
 306         }
 307         BUG();
 308 }
 309
 310 static __init void map_low_mmrs(void)
 311 {
 312         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 313         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 314 }
 315
 316 enum map_type {map_wb, map_uc};
 317
 318 static __init void map_high(char *id, unsigned long base, int shift,
 319                             int max_pnode, enum map_type map_type)
 320 {
 321         unsigned long bytes, paddr;
 322
 323         paddr = base << shift;
 324         bytes = (1UL << shift) * (max_pnode + 1);
 325         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 326                                                 paddr + bytes);
 327         if (map_type == map_uc)
 328                 init_extra_mapping_uc(paddr, bytes);
 329         else
 330                 init_extra_mapping_wb(paddr, bytes);
 331
 332 }
 333 static __init void map_gru_high(int max_pnode)
 334 {
 335         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 336         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 337
 338         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 339         if (gru.s.enable)
 340                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
 341 }
 342
 343 static __init void map_config_high(int max_pnode)
 344 {
 345         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 346         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 347
 348         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 349         if (cfg.s.enable)
 350                 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
 351 }
 352
 353 static __init void map_mmr_high(int max_pnode)
 354 {
 355         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 356         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 357
 358         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 359         if (mmr.s.enable)
 360                 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
 361 }
 362
 363 static __init void map_mmioh_high(int max_pnode)
 364 {
 365         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 366         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 367
 368         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 369         if (mmioh.s.enable)
 370                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
 371 }
 372
 373 static __init void uv_rtc_init(void)
 374 {
 375         long status;
 376         u64 ticks_per_sec;
 377
 378         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 379                                         &ticks_per_sec);
 380         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 381                 printk(KERN_WARNING
 382                         "unable to determine platform RTC clock frequency, "
 383                         "guessing.\n");
 384                 /* BIOS gives wrong value for clock freq. so guess */
 385                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 386         } else
 387                 sn_rtc_cycles_per_second = ticks_per_sec;
 388 }
 389
 390 /*
 391  * percpu heartbeat timer
 392  */
 393 static void uv_heartbeat(unsigned long ignored)
 394 {
 395         struct timer_list *timer = &uv_hub_info->scir.timer;
 396         unsigned char bits = uv_hub_info->scir.state;
 397
 398         /* flip heartbeat bit */
 399         bits ^= SCIR_CPU_HEARTBEAT;
 400
 401         /* is this cpu idle? */
 402         if (idle_cpu(raw_smp_processor_id()))
 403                 bits &= ~SCIR_CPU_ACTIVITY;
 404         else
 405                 bits |= SCIR_CPU_ACTIVITY;
 406
 407         /* update system controller interface reg */
 408         uv_set_scir_bits(bits);
 409
 410         /* enable next timer period */
 411         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 412 }
 413
 414 static void __cpuinit uv_heartbeat_enable(int cpu)
 415 {
 416         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 417                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 418
 419                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 420                 setup_timer(timer, uv_heartbeat, cpu);
 421                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 422                 add_timer_on(timer, cpu);
 423                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 424         }
 425
 426         /* check boot cpu */
 427         if (!uv_cpu_hub_info(0)->scir.enabled)
 428                 uv_heartbeat_enable(0);
 429 }
 430
 431 #ifdef CONFIG_HOTPLUG_CPU
 432 static void __cpuinit uv_heartbeat_disable(int cpu)
 433 {
 434         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 435                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 436                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 437         }
 438         uv_set_cpu_scir_bits(cpu, 0xff);
 439 }
 440
 441 /*
 442  * cpu hotplug notifier
 443  */
 444 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 445                                        unsigned long action, void *hcpu)
 446 {
 447         long cpu = (long)hcpu;
 448
 449         switch (action) {
 450         case CPU_ONLINE:
 451                 uv_heartbeat_enable(cpu);
 452                 break;
 453         case CPU_DOWN_PREPARE:
 454                 uv_heartbeat_disable(cpu);
 455                 break;
 456         default:
 457                 break;
 458         }
 459         return NOTIFY_OK;
 460 }
 461
 462 static __init void uv_scir_register_cpu_notifier(void)
 463 {
 464         hotcpu_notifier(uv_scir_cpu_notify, 0);
 465 }
 466
 467 #else /* !CONFIG_HOTPLUG_CPU */
 468
 469 static __init void uv_scir_register_cpu_notifier(void)
 470 {
 471 }
 472
 473 static __init int uv_init_heartbeat(void)
 474 {
 475         int cpu;
 476
 477         if (is_uv_system())
 478                 for_each_online_cpu(cpu)
 479                         uv_heartbeat_enable(cpu);
 480         return 0;
 481 }
 482
 483 late_initcall(uv_init_heartbeat);
 484
 485 #endif /* !CONFIG_HOTPLUG_CPU */
 486
 487 /*
 488  * Called on each cpu to initialize the per_cpu UV data area.
 489  *      ZZZ hotplug not supported yet
 490  */
 491 void __cpuinit uv_cpu_init(void)
 492 {
 493         /* CPU 0 initilization will be done via uv_system_init. */
 494         if (!uv_blade_info)
 495                 return;
 496
 497         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 498
 499         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 500                 set_x2apic_extra_bits(uv_hub_info->pnode);
 501 }
 502
 503
 504 void __init uv_system_init(void)
 505 {
 506         union uvh_si_addr_map_config_u m_n_config;
 507         union uvh_node_id_u node_id;
 508         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 509         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 510         int max_pnode = 0;
 511         unsigned long mmr_base, present;
 512
 513         map_low_mmrs();
 514
 515         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 516         m_val = m_n_config.s.m_skt;
 517         n_val = m_n_config.s.n_skt;
 518         mmr_base =
 519             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 520             ~UV_MMR_ENABLE;
 521         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 522
 523         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 524                 uv_possible_blades +=
 525                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 526         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 527
 528         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 529         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 530
 531         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 532
 533         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 534         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 535         memset(uv_node_to_blade, 255, bytes);
 536
 537         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 538         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 539         memset(uv_cpu_to_blade, 255, bytes);
 540
 541         blade = 0;
 542         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 543                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 544                 for (j = 0; j < 64; j++) {
 545                         if (!test_bit(j, &present))
 546                                 continue;
 547                         uv_blade_info[blade].pnode = (i * 64 + j);
 548                         uv_blade_info[blade].nr_possible_cpus = 0;
 549                         uv_blade_info[blade].nr_online_cpus = 0;
 550                         blade++;
 551                 }
 552         }
 553
 554         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 555         gnode_upper = (((unsigned long)node_id.s.node_id) &
 556                        ~((1 << n_val) - 1)) << m_val;
 557
 558         uv_bios_init();
 559         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 560                             &sn_coherency_id, &sn_region_size);
 561         uv_rtc_init();
 562
 563         for_each_present_cpu(cpu) {
 564                 nid = cpu_to_node(cpu);
 565                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 566                 blade = boot_pnode_to_blade(pnode);
 567                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 568                 uv_blade_info[blade].nr_possible_cpus++;
 569
 570                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 571                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 572                 uv_cpu_hub_info(cpu)->m_val = m_val;
 573                 uv_cpu_hub_info(cpu)->n_val = m_val;
 574                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 575                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 576                 uv_cpu_hub_info(cpu)->pnode = pnode;
 577                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 578                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 579                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 580                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 581                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 582                 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
 583                 uv_node_to_blade[nid] = blade;
 584                 uv_cpu_to_blade[cpu] = blade;
 585                 max_pnode = max(pnode, max_pnode);
 586
 587                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 588                         "lcpu %d, blade %d\n",
 589                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 590                         lcpu, blade);
 591         }
 592
 593         map_gru_high(max_pnode);
 594         map_mmr_high(max_pnode);
 595         map_config_high(max_pnode);
 596         map_mmioh_high(max_pnode);
 597
 598         uv_cpu_init();
 599         uv_scir_register_cpu_notifier();
 600         proc_mkdir("sgi_uv", NULL);
 601 }