1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/delay.h>
4 #include <linux/errno.h>
5 #include <linux/hpet.h>
6 #include <linux/init.h>
7 #include <linux/sysdev.h>
10 #include <asm/fixmap.h>
12 #include <asm/i8253.h>
15 #define HPET_MASK CLOCKSOURCE_MASK(32)
20 #define FSEC_PER_NSEC 1000000L
23 * HPET address is set in acpi/boot.c, when an ACPI entry exists
25 unsigned long hpet_address;
26 static void __iomem *hpet_virt_address;
28 unsigned long hpet_readl(unsigned long a)
30 return readl(hpet_virt_address + a);
33 static inline void hpet_writel(unsigned long d, unsigned long a)
35 writel(d, hpet_virt_address + a);
39 #include <asm/pgtable.h>
42 static inline void hpet_set_mapping(void)
44 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
46 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
50 static inline void hpet_clear_mapping(void)
52 iounmap(hpet_virt_address);
53 hpet_virt_address = NULL;
57 * HPET command line enable / disable
59 static int boot_hpet_disable;
62 static int __init hpet_setup(char* str)
65 if (!strncmp("disable", str, 7))
66 boot_hpet_disable = 1;
67 if (!strncmp("force", str, 5))
72 __setup("hpet=", hpet_setup);
74 static int __init disable_hpet(char *str)
76 boot_hpet_disable = 1;
79 __setup("nohpet", disable_hpet);
81 static inline int is_hpet_capable(void)
83 return (!boot_hpet_disable && hpet_address);
87 * HPET timer interrupt enable / disable
89 static int hpet_legacy_int_enabled;
92 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
94 int is_hpet_enabled(void)
96 return is_hpet_capable() && hpet_legacy_int_enabled;
98 EXPORT_SYMBOL_GPL(is_hpet_enabled);
101 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
102 * timer 0 and timer 1 in case of RTC emulation.
105 static void hpet_reserve_platform_timers(unsigned long id)
107 struct hpet __iomem *hpet = hpet_virt_address;
108 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
109 unsigned int nrtimers, i;
112 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
114 memset(&hd, 0, sizeof (hd));
115 hd.hd_phys_address = hpet_address;
116 hd.hd_address = hpet;
117 hd.hd_nirqs = nrtimers;
118 hpet_reserve_timer(&hd, 0);
120 #ifdef CONFIG_HPET_EMULATE_RTC
121 hpet_reserve_timer(&hd, 1);
125 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
126 * is wrong for i8259!) not the output IRQ. Many BIOS writers
127 * don't bother configuring *any* comparator interrupts.
129 hd.hd_irq[0] = HPET_LEGACY_8254;
130 hd.hd_irq[1] = HPET_LEGACY_RTC;
132 for (i = 2; i < nrtimers; timer++, i++) {
133 hd.hd_irq[i] = (readl(&timer->hpet_config) & Tn_INT_ROUTE_CNF_MASK) >>
134 Tn_INT_ROUTE_CNF_SHIFT;
141 static void hpet_reserve_platform_timers(unsigned long id) { }
147 static unsigned long hpet_period;
149 static void hpet_legacy_set_mode(enum clock_event_mode mode,
150 struct clock_event_device *evt);
151 static int hpet_legacy_next_event(unsigned long delta,
152 struct clock_event_device *evt);
155 * The hpet clock event device
157 static struct clock_event_device hpet_clockevent = {
159 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
160 .set_mode = hpet_legacy_set_mode,
161 .set_next_event = hpet_legacy_next_event,
167 static void hpet_start_counter(void)
169 unsigned long cfg = hpet_readl(HPET_CFG);
171 cfg &= ~HPET_CFG_ENABLE;
172 hpet_writel(cfg, HPET_CFG);
173 hpet_writel(0, HPET_COUNTER);
174 hpet_writel(0, HPET_COUNTER + 4);
175 cfg |= HPET_CFG_ENABLE;
176 hpet_writel(cfg, HPET_CFG);
179 static void hpet_resume_device(void)
184 static void hpet_restart_counter(void)
186 hpet_resume_device();
187 hpet_start_counter();
190 static void hpet_enable_legacy_int(void)
192 unsigned long cfg = hpet_readl(HPET_CFG);
194 cfg |= HPET_CFG_LEGACY;
195 hpet_writel(cfg, HPET_CFG);
196 hpet_legacy_int_enabled = 1;
199 static void hpet_legacy_clockevent_register(void)
201 /* Start HPET legacy interrupts */
202 hpet_enable_legacy_int();
205 * The mult factor is defined as (include/linux/clockchips.h)
206 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
207 * hpet_period is in units of femtoseconds (per cycle), so
208 * mult/2^shift = cyc/ns = 10^6/hpet_period
209 * mult = (10^6 * 2^shift)/hpet_period
210 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
212 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
213 hpet_period, hpet_clockevent.shift);
214 /* Calculate the min / max delta */
215 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
217 /* 5 usec minimum reprogramming delta. */
218 hpet_clockevent.min_delta_ns = 5000;
221 * Start hpet with the boot cpu mask and make it
222 * global after the IO_APIC has been initialized.
224 hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
225 clockevents_register_device(&hpet_clockevent);
226 global_clock_event = &hpet_clockevent;
227 printk(KERN_DEBUG "hpet clockevent registered\n");
230 static void hpet_legacy_set_mode(enum clock_event_mode mode,
231 struct clock_event_device *evt)
233 unsigned long cfg, cmp, now;
237 case CLOCK_EVT_MODE_PERIODIC:
238 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
239 delta >>= hpet_clockevent.shift;
240 now = hpet_readl(HPET_COUNTER);
241 cmp = now + (unsigned long) delta;
242 cfg = hpet_readl(HPET_T0_CFG);
243 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
244 HPET_TN_SETVAL | HPET_TN_32BIT;
245 hpet_writel(cfg, HPET_T0_CFG);
247 * The first write after writing TN_SETVAL to the
248 * config register sets the counter value, the second
249 * write sets the period.
251 hpet_writel(cmp, HPET_T0_CMP);
253 hpet_writel((unsigned long) delta, HPET_T0_CMP);
256 case CLOCK_EVT_MODE_ONESHOT:
257 cfg = hpet_readl(HPET_T0_CFG);
258 cfg &= ~HPET_TN_PERIODIC;
259 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
260 hpet_writel(cfg, HPET_T0_CFG);
263 case CLOCK_EVT_MODE_UNUSED:
264 case CLOCK_EVT_MODE_SHUTDOWN:
265 cfg = hpet_readl(HPET_T0_CFG);
266 cfg &= ~HPET_TN_ENABLE;
267 hpet_writel(cfg, HPET_T0_CFG);
270 case CLOCK_EVT_MODE_RESUME:
271 hpet_enable_legacy_int();
276 static int hpet_legacy_next_event(unsigned long delta,
277 struct clock_event_device *evt)
281 cnt = hpet_readl(HPET_COUNTER);
283 hpet_writel(cnt, HPET_T0_CMP);
286 * We need to read back the CMP register to make sure that
287 * what we wrote hit the chip before we compare it to the
290 WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt);
292 return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
296 * Clock source related code
298 static cycle_t read_hpet(void)
300 return (cycle_t)hpet_readl(HPET_COUNTER);
304 static cycle_t __vsyscall_fn vread_hpet(void)
306 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
310 static struct clocksource clocksource_hpet = {
316 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
317 .resume = hpet_restart_counter,
323 static int hpet_clocksource_register(void)
328 /* Start the counter */
329 hpet_start_counter();
331 /* Verify whether hpet counter works */
336 * We don't know the TSC frequency yet, but waiting for
337 * 200000 TSC cycles is safe:
344 } while ((now - start) < 200000UL);
346 if (t1 == read_hpet()) {
348 "HPET counter not counting. HPET disabled\n");
353 * The definition of mult is (include/linux/clocksource.h)
354 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
355 * so we first need to convert hpet_period to ns/cyc units:
356 * mult/2^shift = ns/cyc = hpet_period/10^6
357 * mult = (hpet_period * 2^shift)/10^6
358 * mult = (hpet_period << shift)/FSEC_PER_NSEC
360 clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
362 clocksource_register(&clocksource_hpet);
368 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
370 int __init hpet_enable(void)
375 if (!is_hpet_capable())
381 * Read the period and check for a sane value:
383 hpet_period = hpet_readl(HPET_PERIOD);
386 * AMD SB700 based systems with spread spectrum enabled use a
387 * SMM based HPET emulation to provide proper frequency
388 * setting. The SMM code is initialized with the first HPET
389 * register access and takes some time to complete. During
390 * this time the config register reads 0xffffffff. We check
391 * for max. 1000 loops whether the config register reads a non
392 * 0xffffffff value to make sure that HPET is up and running
393 * before we go further. A counting loop is safe, as the HPET
394 * access takes thousands of CPU cycles. On non SB700 based
395 * machines this check is only done once and has no side
398 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
401 "HPET config register value = 0xFFFFFFFF. "
407 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
411 * Read the HPET ID register to retrieve the IRQ routing
412 * information and the number of channels
414 id = hpet_readl(HPET_ID);
416 #ifdef CONFIG_HPET_EMULATE_RTC
418 * The legacy routing mode needs at least two channels, tick timer
419 * and the rtc emulation channel.
421 if (!(id & HPET_ID_NUMBER))
425 if (hpet_clocksource_register())
428 if (id & HPET_ID_LEGSUP) {
429 hpet_legacy_clockevent_register();
435 hpet_clear_mapping();
436 boot_hpet_disable = 1;
441 * Needs to be late, as the reserve_timer code calls kalloc !
443 * Not a problem on i386 as hpet_enable is called from late_time_init,
444 * but on x86_64 it is necessary !
446 static __init int hpet_late_init(void)
448 if (boot_hpet_disable)
452 if (!force_hpet_address)
455 hpet_address = force_hpet_address;
457 if (!hpet_virt_address)
461 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
465 fs_initcall(hpet_late_init);
467 void hpet_disable(void)
469 if (is_hpet_capable()) {
470 unsigned long cfg = hpet_readl(HPET_CFG);
472 if (hpet_legacy_int_enabled) {
473 cfg &= ~HPET_CFG_LEGACY;
474 hpet_legacy_int_enabled = 0;
476 cfg &= ~HPET_CFG_ENABLE;
477 hpet_writel(cfg, HPET_CFG);
481 #ifdef CONFIG_HPET_EMULATE_RTC
483 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
484 * is enabled, we support RTC interrupt functionality in software.
485 * RTC has 3 kinds of interrupts:
486 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
488 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
489 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
490 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
491 * (1) and (2) above are implemented using polling at a frequency of
492 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
493 * overhead. (DEFAULT_RTC_INT_FREQ)
494 * For (3), we use interrupts at 64Hz or user specified periodic
495 * frequency, whichever is higher.
497 #include <linux/mc146818rtc.h>
498 #include <linux/rtc.h>
501 #define DEFAULT_RTC_INT_FREQ 64
502 #define DEFAULT_RTC_SHIFT 6
503 #define RTC_NUM_INTS 1
505 static unsigned long hpet_rtc_flags;
506 static int hpet_prev_update_sec;
507 static struct rtc_time hpet_alarm_time;
508 static unsigned long hpet_pie_count;
509 static unsigned long hpet_t1_cmp;
510 static unsigned long hpet_default_delta;
511 static unsigned long hpet_pie_delta;
512 static unsigned long hpet_pie_limit;
514 static rtc_irq_handler irq_handler;
517 * Registers a IRQ handler.
519 int hpet_register_irq_handler(rtc_irq_handler handler)
521 if (!is_hpet_enabled())
526 irq_handler = handler;
530 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
533 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
536 void hpet_unregister_irq_handler(rtc_irq_handler handler)
538 if (!is_hpet_enabled())
544 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
547 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
548 * is not supported by all HPET implementations for timer 1.
550 * hpet_rtc_timer_init() is called when the rtc is initialized.
552 int hpet_rtc_timer_init(void)
554 unsigned long cfg, cnt, delta, flags;
556 if (!is_hpet_enabled())
559 if (!hpet_default_delta) {
562 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
563 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
564 hpet_default_delta = (unsigned long) clc;
567 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
568 delta = hpet_default_delta;
570 delta = hpet_pie_delta;
572 local_irq_save(flags);
574 cnt = delta + hpet_readl(HPET_COUNTER);
575 hpet_writel(cnt, HPET_T1_CMP);
578 cfg = hpet_readl(HPET_T1_CFG);
579 cfg &= ~HPET_TN_PERIODIC;
580 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
581 hpet_writel(cfg, HPET_T1_CFG);
583 local_irq_restore(flags);
587 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
590 * The functions below are called from rtc driver.
591 * Return 0 if HPET is not being used.
592 * Otherwise do the necessary changes and return 1.
594 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
596 if (!is_hpet_enabled())
599 hpet_rtc_flags &= ~bit_mask;
602 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
604 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
606 unsigned long oldbits = hpet_rtc_flags;
608 if (!is_hpet_enabled())
611 hpet_rtc_flags |= bit_mask;
613 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
614 hpet_prev_update_sec = -1;
617 hpet_rtc_timer_init();
621 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
623 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
626 if (!is_hpet_enabled())
629 hpet_alarm_time.tm_hour = hrs;
630 hpet_alarm_time.tm_min = min;
631 hpet_alarm_time.tm_sec = sec;
635 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
637 int hpet_set_periodic_freq(unsigned long freq)
641 if (!is_hpet_enabled())
644 if (freq <= DEFAULT_RTC_INT_FREQ)
645 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
647 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
649 clc >>= hpet_clockevent.shift;
650 hpet_pie_delta = (unsigned long) clc;
654 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
656 int hpet_rtc_dropped_irq(void)
658 return is_hpet_enabled();
660 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
662 static void hpet_rtc_timer_reinit(void)
664 unsigned long cfg, delta;
667 if (unlikely(!hpet_rtc_flags)) {
668 cfg = hpet_readl(HPET_T1_CFG);
669 cfg &= ~HPET_TN_ENABLE;
670 hpet_writel(cfg, HPET_T1_CFG);
674 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
675 delta = hpet_default_delta;
677 delta = hpet_pie_delta;
680 * Increment the comparator value until we are ahead of the
684 hpet_t1_cmp += delta;
685 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
687 } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
690 if (hpet_rtc_flags & RTC_PIE)
691 hpet_pie_count += lost_ints;
692 if (printk_ratelimit())
693 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
698 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
700 struct rtc_time curr_time;
701 unsigned long rtc_int_flag = 0;
703 hpet_rtc_timer_reinit();
704 memset(&curr_time, 0, sizeof(struct rtc_time));
706 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
707 get_rtc_time(&curr_time);
709 if (hpet_rtc_flags & RTC_UIE &&
710 curr_time.tm_sec != hpet_prev_update_sec) {
711 if (hpet_prev_update_sec >= 0)
712 rtc_int_flag = RTC_UF;
713 hpet_prev_update_sec = curr_time.tm_sec;
716 if (hpet_rtc_flags & RTC_PIE &&
717 ++hpet_pie_count >= hpet_pie_limit) {
718 rtc_int_flag |= RTC_PF;
722 if (hpet_rtc_flags & RTC_AIE &&
723 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
724 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
725 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
726 rtc_int_flag |= RTC_AF;
729 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
731 irq_handler(rtc_int_flag, dev_id);
735 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);