2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 static int __init parse_noapic(char *str)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic);
113 * This is performance-critical, we want to do it O(1)
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
119 struct irq_pin_list {
121 struct irq_pin_list *next;
124 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
126 struct irq_pin_list *pin;
129 node = cpu_to_node(cpu);
131 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
132 printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node);
138 struct irq_pin_list *irq_2_pin;
139 cpumask_var_t domain;
140 cpumask_var_t old_domain;
141 unsigned move_cleanup_count;
143 u8 move_in_progress : 1;
144 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
145 u8 move_desc_pending : 1;
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx[] = {
153 static struct irq_cfg irq_cfgx[NR_IRQS] = {
155 [0] = { .vector = IRQ0_VECTOR, },
156 [1] = { .vector = IRQ1_VECTOR, },
157 [2] = { .vector = IRQ2_VECTOR, },
158 [3] = { .vector = IRQ3_VECTOR, },
159 [4] = { .vector = IRQ4_VECTOR, },
160 [5] = { .vector = IRQ5_VECTOR, },
161 [6] = { .vector = IRQ6_VECTOR, },
162 [7] = { .vector = IRQ7_VECTOR, },
163 [8] = { .vector = IRQ8_VECTOR, },
164 [9] = { .vector = IRQ9_VECTOR, },
165 [10] = { .vector = IRQ10_VECTOR, },
166 [11] = { .vector = IRQ11_VECTOR, },
167 [12] = { .vector = IRQ12_VECTOR, },
168 [13] = { .vector = IRQ13_VECTOR, },
169 [14] = { .vector = IRQ14_VECTOR, },
170 [15] = { .vector = IRQ15_VECTOR, },
173 void __init arch_early_irq_init(void)
176 struct irq_desc *desc;
181 count = ARRAY_SIZE(irq_cfgx);
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
186 alloc_bootmem_cpumask_var(&cfg[i].domain);
187 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
188 if (i < NR_IRQS_LEGACY)
189 cpumask_setall(cfg[i].domain);
193 #ifdef CONFIG_SPARSE_IRQ
194 static struct irq_cfg *irq_cfg(unsigned int irq)
196 struct irq_cfg *cfg = NULL;
197 struct irq_desc *desc;
199 desc = irq_to_desc(irq);
201 cfg = desc->chip_data;
206 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
211 node = cpu_to_node(cpu);
213 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
215 /* FIXME: needs alloc_cpumask_var_node() */
216 if (!alloc_cpumask_var(&cfg->domain, GFP_ATOMIC)) {
219 } else if (!alloc_cpumask_var(&cfg->old_domain, GFP_ATOMIC)) {
220 free_cpumask_var(cfg->domain);
224 cpumask_clear(cfg->domain);
225 cpumask_clear(cfg->old_domain);
228 printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node);
233 void arch_init_chip_data(struct irq_desc *desc, int cpu)
237 cfg = desc->chip_data;
239 desc->chip_data = get_one_free_irq_cfg(cpu);
240 if (!desc->chip_data) {
241 printk(KERN_ERR "can not alloc irq_cfg\n");
247 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
250 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
252 struct irq_pin_list *old_entry, *head, *tail, *entry;
254 cfg->irq_2_pin = NULL;
255 old_entry = old_cfg->irq_2_pin;
259 entry = get_one_free_irq_2_pin(cpu);
263 entry->apic = old_entry->apic;
264 entry->pin = old_entry->pin;
267 old_entry = old_entry->next;
269 entry = get_one_free_irq_2_pin(cpu);
277 /* still use the old one */
280 entry->apic = old_entry->apic;
281 entry->pin = old_entry->pin;
284 old_entry = old_entry->next;
288 cfg->irq_2_pin = head;
291 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
293 struct irq_pin_list *entry, *next;
295 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
298 entry = old_cfg->irq_2_pin;
305 old_cfg->irq_2_pin = NULL;
308 void arch_init_copy_chip_data(struct irq_desc *old_desc,
309 struct irq_desc *desc, int cpu)
312 struct irq_cfg *old_cfg;
314 cfg = get_one_free_irq_cfg(cpu);
319 desc->chip_data = cfg;
321 old_cfg = old_desc->chip_data;
323 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
325 init_copy_irq_2_pin(old_cfg, cfg, cpu);
328 static void free_irq_cfg(struct irq_cfg *old_cfg)
333 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
335 struct irq_cfg *old_cfg, *cfg;
337 old_cfg = old_desc->chip_data;
338 cfg = desc->chip_data;
344 free_irq_2_pin(old_cfg, cfg);
345 free_irq_cfg(old_cfg);
346 old_desc->chip_data = NULL;
350 static void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask)
352 struct irq_cfg *cfg = desc->chip_data;
354 if (!cfg->move_in_progress) {
355 /* it means that domain is not changed */
356 if (!cpus_intersects(desc->affinity, mask))
357 cfg->move_desc_pending = 1;
363 static struct irq_cfg *irq_cfg(unsigned int irq)
365 return irq < nr_irqs ? irq_cfgx + irq : NULL;
370 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
372 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
379 unsigned int unused[3];
383 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
385 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
386 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
389 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
391 struct io_apic __iomem *io_apic = io_apic_base(apic);
392 writel(reg, &io_apic->index);
393 return readl(&io_apic->data);
396 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
398 struct io_apic __iomem *io_apic = io_apic_base(apic);
399 writel(reg, &io_apic->index);
400 writel(value, &io_apic->data);
404 * Re-write a value: to be used for read-modify-write
405 * cycles where the read already set up the index register.
407 * Older SiS APIC requires we rewrite the index register
409 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
411 struct io_apic __iomem *io_apic = io_apic_base(apic);
414 writel(reg, &io_apic->index);
415 writel(value, &io_apic->data);
418 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
420 struct irq_pin_list *entry;
423 spin_lock_irqsave(&ioapic_lock, flags);
424 entry = cfg->irq_2_pin;
432 reg = io_apic_read(entry->apic, 0x10 + pin*2);
433 /* Is the remote IRR bit set? */
434 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
435 spin_unlock_irqrestore(&ioapic_lock, flags);
442 spin_unlock_irqrestore(&ioapic_lock, flags);
448 struct { u32 w1, w2; };
449 struct IO_APIC_route_entry entry;
452 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
454 union entry_union eu;
456 spin_lock_irqsave(&ioapic_lock, flags);
457 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
458 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
459 spin_unlock_irqrestore(&ioapic_lock, flags);
464 * When we write a new IO APIC routing entry, we need to write the high
465 * word first! If the mask bit in the low word is clear, we will enable
466 * the interrupt, and we need to make sure the entry is fully populated
467 * before that happens.
470 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
472 union entry_union eu;
474 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
475 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
478 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
481 spin_lock_irqsave(&ioapic_lock, flags);
482 __ioapic_write_entry(apic, pin, e);
483 spin_unlock_irqrestore(&ioapic_lock, flags);
487 * When we mask an IO APIC routing entry, we need to write the low
488 * word first, in order to set the mask bit before we change the
491 static void ioapic_mask_entry(int apic, int pin)
494 union entry_union eu = { .entry.mask = 1 };
496 spin_lock_irqsave(&ioapic_lock, flags);
497 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
498 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
499 spin_unlock_irqrestore(&ioapic_lock, flags);
503 static void send_cleanup_vector(struct irq_cfg *cfg)
505 cpumask_var_t cleanup_mask;
507 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
509 cfg->move_cleanup_count = 0;
510 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
511 cfg->move_cleanup_count++;
512 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
513 send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
515 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
516 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
517 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
518 free_cpumask_var(cleanup_mask);
520 cfg->move_in_progress = 0;
523 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
526 struct irq_pin_list *entry;
527 u8 vector = cfg->vector;
529 entry = cfg->irq_2_pin;
538 #ifdef CONFIG_INTR_REMAP
540 * With interrupt-remapping, destination information comes
541 * from interrupt-remapping table entry.
543 if (!irq_remapped(irq))
544 io_apic_write(apic, 0x11 + pin*2, dest);
546 io_apic_write(apic, 0x11 + pin*2, dest);
548 reg = io_apic_read(apic, 0x10 + pin*2);
549 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
551 io_apic_modify(apic, 0x10 + pin*2, reg);
559 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
562 * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid
563 * of that, or returns BAD_APICID and leaves desc->affinity untouched.
566 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
571 if (!cpumask_intersects(mask, cpu_online_mask))
575 cfg = desc->chip_data;
576 if (assign_irq_vector(irq, cfg, mask))
579 cpumask_and(&desc->affinity, cfg->domain, mask);
580 set_extra_move_desc(desc, mask);
581 return cpu_mask_to_apicid_and(&desc->affinity, cpu_online_mask);
585 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
593 cfg = desc->chip_data;
595 spin_lock_irqsave(&ioapic_lock, flags);
596 dest = set_desc_affinity(desc, mask);
597 if (dest != BAD_APICID) {
598 /* Only the high 8 bits are valid. */
599 dest = SET_APIC_LOGICAL_ID(dest);
600 __target_IO_APIC_irq(irq, dest, cfg);
602 spin_unlock_irqrestore(&ioapic_lock, flags);
606 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
608 struct irq_desc *desc;
610 desc = irq_to_desc(irq);
612 set_ioapic_affinity_irq_desc(desc, mask);
614 #endif /* CONFIG_SMP */
617 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
618 * shared ISA-space IRQs, so we have to support them. We are super
619 * fast in the common case, and fast for shared ISA-space IRQs.
621 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
623 struct irq_pin_list *entry;
625 entry = cfg->irq_2_pin;
627 entry = get_one_free_irq_2_pin(cpu);
629 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
633 cfg->irq_2_pin = entry;
639 while (entry->next) {
640 /* not again, please */
641 if (entry->apic == apic && entry->pin == pin)
647 entry->next = get_one_free_irq_2_pin(cpu);
654 * Reroute an IRQ to a different pin.
656 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
657 int oldapic, int oldpin,
658 int newapic, int newpin)
660 struct irq_pin_list *entry = cfg->irq_2_pin;
664 if (entry->apic == oldapic && entry->pin == oldpin) {
665 entry->apic = newapic;
668 /* every one is different, right? */
674 /* why? call replace before add? */
676 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
679 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
680 int mask_and, int mask_or,
681 void (*final)(struct irq_pin_list *entry))
684 struct irq_pin_list *entry;
686 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
689 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
692 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
698 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
700 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
704 void io_apic_sync(struct irq_pin_list *entry)
707 * Synchronize the IO-APIC and the CPU by doing
708 * a dummy read from the IO-APIC
710 struct io_apic __iomem *io_apic;
711 io_apic = io_apic_base(entry->apic);
712 readl(&io_apic->data);
715 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
717 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
719 #else /* CONFIG_X86_32 */
720 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
722 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
725 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
727 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
728 IO_APIC_REDIR_MASKED, NULL);
731 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
733 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
734 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
736 #endif /* CONFIG_X86_32 */
738 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
740 struct irq_cfg *cfg = desc->chip_data;
745 spin_lock_irqsave(&ioapic_lock, flags);
746 __mask_IO_APIC_irq(cfg);
747 spin_unlock_irqrestore(&ioapic_lock, flags);
750 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
752 struct irq_cfg *cfg = desc->chip_data;
755 spin_lock_irqsave(&ioapic_lock, flags);
756 __unmask_IO_APIC_irq(cfg);
757 spin_unlock_irqrestore(&ioapic_lock, flags);
760 static void mask_IO_APIC_irq(unsigned int irq)
762 struct irq_desc *desc = irq_to_desc(irq);
764 mask_IO_APIC_irq_desc(desc);
766 static void unmask_IO_APIC_irq(unsigned int irq)
768 struct irq_desc *desc = irq_to_desc(irq);
770 unmask_IO_APIC_irq_desc(desc);
773 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
775 struct IO_APIC_route_entry entry;
777 /* Check delivery_mode to be sure we're not clearing an SMI pin */
778 entry = ioapic_read_entry(apic, pin);
779 if (entry.delivery_mode == dest_SMI)
782 * Disable it in the IO-APIC irq-routing table:
784 ioapic_mask_entry(apic, pin);
787 static void clear_IO_APIC (void)
791 for (apic = 0; apic < nr_ioapics; apic++)
792 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
793 clear_IO_APIC_pin(apic, pin);
796 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
797 void send_IPI_self(int vector)
804 apic_wait_icr_idle();
805 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
807 * Send the IPI. The write to APIC_ICR fires this off.
809 apic_write(APIC_ICR, cfg);
811 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
815 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
816 * specific CPU-side IRQs.
820 static int pirq_entries [MAX_PIRQS];
821 static int pirqs_enabled;
823 static int __init ioapic_pirq_setup(char *str)
826 int ints[MAX_PIRQS+1];
828 get_options(str, ARRAY_SIZE(ints), ints);
830 for (i = 0; i < MAX_PIRQS; i++)
831 pirq_entries[i] = -1;
834 apic_printk(APIC_VERBOSE, KERN_INFO
835 "PIRQ redirection, working around broken MP-BIOS.\n");
837 if (ints[0] < MAX_PIRQS)
840 for (i = 0; i < max; i++) {
841 apic_printk(APIC_VERBOSE, KERN_DEBUG
842 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
844 * PIRQs are mapped upside down, usually.
846 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
851 __setup("pirq=", ioapic_pirq_setup);
852 #endif /* CONFIG_X86_32 */
854 #ifdef CONFIG_INTR_REMAP
855 /* I/O APIC RTE contents at the OS boot up */
856 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
859 * Saves and masks all the unmasked IO-APIC RTE's
861 int save_mask_IO_APIC_setup(void)
863 union IO_APIC_reg_01 reg_01;
868 * The number of IO-APIC IRQ registers (== #pins):
870 for (apic = 0; apic < nr_ioapics; apic++) {
871 spin_lock_irqsave(&ioapic_lock, flags);
872 reg_01.raw = io_apic_read(apic, 1);
873 spin_unlock_irqrestore(&ioapic_lock, flags);
874 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
877 for (apic = 0; apic < nr_ioapics; apic++) {
878 early_ioapic_entries[apic] =
879 kzalloc(sizeof(struct IO_APIC_route_entry) *
880 nr_ioapic_registers[apic], GFP_KERNEL);
881 if (!early_ioapic_entries[apic])
885 for (apic = 0; apic < nr_ioapics; apic++)
886 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
887 struct IO_APIC_route_entry entry;
889 entry = early_ioapic_entries[apic][pin] =
890 ioapic_read_entry(apic, pin);
893 ioapic_write_entry(apic, pin, entry);
901 kfree(early_ioapic_entries[apic--]);
902 memset(early_ioapic_entries, 0,
903 ARRAY_SIZE(early_ioapic_entries));
908 void restore_IO_APIC_setup(void)
912 for (apic = 0; apic < nr_ioapics; apic++) {
913 if (!early_ioapic_entries[apic])
915 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
916 ioapic_write_entry(apic, pin,
917 early_ioapic_entries[apic][pin]);
918 kfree(early_ioapic_entries[apic]);
919 early_ioapic_entries[apic] = NULL;
923 void reinit_intr_remapped_IO_APIC(int intr_remapping)
926 * for now plain restore of previous settings.
927 * TBD: In the case of OS enabling interrupt-remapping,
928 * IO-APIC RTE's need to be setup to point to interrupt-remapping
929 * table entries. for now, do a plain restore, and wait for
930 * the setup_IO_APIC_irqs() to do proper initialization.
932 restore_IO_APIC_setup();
937 * Find the IRQ entry number of a certain pin.
939 static int find_irq_entry(int apic, int pin, int type)
943 for (i = 0; i < mp_irq_entries; i++)
944 if (mp_irqs[i].mp_irqtype == type &&
945 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
946 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
947 mp_irqs[i].mp_dstirq == pin)
954 * Find the pin to which IRQ[irq] (ISA) is connected
956 static int __init find_isa_irq_pin(int irq, int type)
960 for (i = 0; i < mp_irq_entries; i++) {
961 int lbus = mp_irqs[i].mp_srcbus;
963 if (test_bit(lbus, mp_bus_not_pci) &&
964 (mp_irqs[i].mp_irqtype == type) &&
965 (mp_irqs[i].mp_srcbusirq == irq))
967 return mp_irqs[i].mp_dstirq;
972 static int __init find_isa_irq_apic(int irq, int type)
976 for (i = 0; i < mp_irq_entries; i++) {
977 int lbus = mp_irqs[i].mp_srcbus;
979 if (test_bit(lbus, mp_bus_not_pci) &&
980 (mp_irqs[i].mp_irqtype == type) &&
981 (mp_irqs[i].mp_srcbusirq == irq))
984 if (i < mp_irq_entries) {
986 for(apic = 0; apic < nr_ioapics; apic++) {
987 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
996 * Find a specific PCI IRQ entry.
997 * Not an __init, possibly needed by modules
999 static int pin_2_irq(int idx, int apic, int pin);
1001 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1003 int apic, i, best_guess = -1;
1005 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1007 if (test_bit(bus, mp_bus_not_pci)) {
1008 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1011 for (i = 0; i < mp_irq_entries; i++) {
1012 int lbus = mp_irqs[i].mp_srcbus;
1014 for (apic = 0; apic < nr_ioapics; apic++)
1015 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
1016 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
1019 if (!test_bit(lbus, mp_bus_not_pci) &&
1020 !mp_irqs[i].mp_irqtype &&
1022 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
1023 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
1025 if (!(apic || IO_APIC_IRQ(irq)))
1028 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
1031 * Use the first all-but-pin matching entry as a
1032 * best-guess fuzzy result for broken mptables.
1041 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1043 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1045 * EISA Edge/Level control register, ELCR
1047 static int EISA_ELCR(unsigned int irq)
1049 if (irq < NR_IRQS_LEGACY) {
1050 unsigned int port = 0x4d0 + (irq >> 3);
1051 return (inb(port) >> (irq & 7)) & 1;
1053 apic_printk(APIC_VERBOSE, KERN_INFO
1054 "Broken MPtable reports ISA irq %d\n", irq);
1060 /* ISA interrupts are always polarity zero edge triggered,
1061 * when listed as conforming in the MP table. */
1063 #define default_ISA_trigger(idx) (0)
1064 #define default_ISA_polarity(idx) (0)
1066 /* EISA interrupts are always polarity zero and can be edge or level
1067 * trigger depending on the ELCR value. If an interrupt is listed as
1068 * EISA conforming in the MP table, that means its trigger type must
1069 * be read in from the ELCR */
1071 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1072 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1074 /* PCI interrupts are always polarity one level triggered,
1075 * when listed as conforming in the MP table. */
1077 #define default_PCI_trigger(idx) (1)
1078 #define default_PCI_polarity(idx) (1)
1080 /* MCA interrupts are always polarity zero level triggered,
1081 * when listed as conforming in the MP table. */
1083 #define default_MCA_trigger(idx) (1)
1084 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1086 static int MPBIOS_polarity(int idx)
1088 int bus = mp_irqs[idx].mp_srcbus;
1092 * Determine IRQ line polarity (high active or low active):
1094 switch (mp_irqs[idx].mp_irqflag & 3)
1096 case 0: /* conforms, ie. bus-type dependent polarity */
1097 if (test_bit(bus, mp_bus_not_pci))
1098 polarity = default_ISA_polarity(idx);
1100 polarity = default_PCI_polarity(idx);
1102 case 1: /* high active */
1107 case 2: /* reserved */
1109 printk(KERN_WARNING "broken BIOS!!\n");
1113 case 3: /* low active */
1118 default: /* invalid */
1120 printk(KERN_WARNING "broken BIOS!!\n");
1128 static int MPBIOS_trigger(int idx)
1130 int bus = mp_irqs[idx].mp_srcbus;
1134 * Determine IRQ trigger mode (edge or level sensitive):
1136 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1138 case 0: /* conforms, ie. bus-type dependent */
1139 if (test_bit(bus, mp_bus_not_pci))
1140 trigger = default_ISA_trigger(idx);
1142 trigger = default_PCI_trigger(idx);
1143 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1144 switch (mp_bus_id_to_type[bus]) {
1145 case MP_BUS_ISA: /* ISA pin */
1147 /* set before the switch */
1150 case MP_BUS_EISA: /* EISA pin */
1152 trigger = default_EISA_trigger(idx);
1155 case MP_BUS_PCI: /* PCI pin */
1157 /* set before the switch */
1160 case MP_BUS_MCA: /* MCA pin */
1162 trigger = default_MCA_trigger(idx);
1167 printk(KERN_WARNING "broken BIOS!!\n");
1179 case 2: /* reserved */
1181 printk(KERN_WARNING "broken BIOS!!\n");
1190 default: /* invalid */
1192 printk(KERN_WARNING "broken BIOS!!\n");
1200 static inline int irq_polarity(int idx)
1202 return MPBIOS_polarity(idx);
1205 static inline int irq_trigger(int idx)
1207 return MPBIOS_trigger(idx);
1210 int (*ioapic_renumber_irq)(int ioapic, int irq);
1211 static int pin_2_irq(int idx, int apic, int pin)
1214 int bus = mp_irqs[idx].mp_srcbus;
1217 * Debugging check, we are in big trouble if this message pops up!
1219 if (mp_irqs[idx].mp_dstirq != pin)
1220 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1222 if (test_bit(bus, mp_bus_not_pci)) {
1223 irq = mp_irqs[idx].mp_srcbusirq;
1226 * PCI IRQs are mapped in order
1230 irq += nr_ioapic_registers[i++];
1233 * For MPS mode, so far only needed by ES7000 platform
1235 if (ioapic_renumber_irq)
1236 irq = ioapic_renumber_irq(apic, irq);
1239 #ifdef CONFIG_X86_32
1241 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1243 if ((pin >= 16) && (pin <= 23)) {
1244 if (pirq_entries[pin-16] != -1) {
1245 if (!pirq_entries[pin-16]) {
1246 apic_printk(APIC_VERBOSE, KERN_DEBUG
1247 "disabling PIRQ%d\n", pin-16);
1249 irq = pirq_entries[pin-16];
1250 apic_printk(APIC_VERBOSE, KERN_DEBUG
1251 "using PIRQ%d -> IRQ %d\n",
1261 void lock_vector_lock(void)
1263 /* Used to the online set of cpus does not change
1264 * during assign_irq_vector.
1266 spin_lock(&vector_lock);
1269 void unlock_vector_lock(void)
1271 spin_unlock(&vector_lock);
1275 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1278 * NOTE! The local APIC isn't very good at handling
1279 * multiple interrupts at the same interrupt level.
1280 * As the interrupt level is determined by taking the
1281 * vector number and shifting that right by 4, we
1282 * want to spread these out a bit so that they don't
1283 * all fall in the same interrupt level.
1285 * Also, we've got to be careful not to trash gate
1286 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1288 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1289 unsigned int old_vector;
1291 cpumask_var_t tmp_mask;
1293 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1296 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1299 old_vector = cfg->vector;
1301 cpumask_and(tmp_mask, mask, cpu_online_mask);
1302 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1303 if (!cpumask_empty(tmp_mask)) {
1304 free_cpumask_var(tmp_mask);
1309 /* Only try and allocate irqs on cpus that are present */
1311 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1315 vector_allocation_domain(cpu, tmp_mask);
1317 vector = current_vector;
1318 offset = current_offset;
1321 if (vector >= first_system_vector) {
1322 /* If out of vectors on large boxen, must share them. */
1323 offset = (offset + 1) % 8;
1324 vector = FIRST_DEVICE_VECTOR + offset;
1326 if (unlikely(current_vector == vector))
1328 #ifdef CONFIG_X86_64
1329 if (vector == IA32_SYSCALL_VECTOR)
1332 if (vector == SYSCALL_VECTOR)
1335 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1336 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1339 current_vector = vector;
1340 current_offset = offset;
1342 cfg->move_in_progress = 1;
1343 cpumask_copy(cfg->old_domain, cfg->domain);
1345 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1346 per_cpu(vector_irq, new_cpu)[vector] = irq;
1347 cfg->vector = vector;
1348 cpumask_copy(cfg->domain, tmp_mask);
1352 free_cpumask_var(tmp_mask);
1357 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1360 unsigned long flags;
1362 spin_lock_irqsave(&vector_lock, flags);
1363 err = __assign_irq_vector(irq, cfg, mask);
1364 spin_unlock_irqrestore(&vector_lock, flags);
1368 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1372 BUG_ON(!cfg->vector);
1374 vector = cfg->vector;
1375 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1376 per_cpu(vector_irq, cpu)[vector] = -1;
1379 cpumask_clear(cfg->domain);
1381 if (likely(!cfg->move_in_progress))
1383 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1384 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1386 if (per_cpu(vector_irq, cpu)[vector] != irq)
1388 per_cpu(vector_irq, cpu)[vector] = -1;
1392 cfg->move_in_progress = 0;
1395 void __setup_vector_irq(int cpu)
1397 /* Initialize vector_irq on a new cpu */
1398 /* This function must be called with vector_lock held */
1400 struct irq_cfg *cfg;
1401 struct irq_desc *desc;
1403 /* Mark the inuse vectors */
1404 for_each_irq_desc(irq, desc) {
1407 cfg = desc->chip_data;
1408 if (!cpumask_test_cpu(cpu, cfg->domain))
1410 vector = cfg->vector;
1411 per_cpu(vector_irq, cpu)[vector] = irq;
1413 /* Mark the free vectors */
1414 for (vector = 0; vector < NR_VECTORS; ++vector) {
1415 irq = per_cpu(vector_irq, cpu)[vector];
1420 if (!cpumask_test_cpu(cpu, cfg->domain))
1421 per_cpu(vector_irq, cpu)[vector] = -1;
1425 static struct irq_chip ioapic_chip;
1426 #ifdef CONFIG_INTR_REMAP
1427 static struct irq_chip ir_ioapic_chip;
1430 #define IOAPIC_AUTO -1
1431 #define IOAPIC_EDGE 0
1432 #define IOAPIC_LEVEL 1
1434 #ifdef CONFIG_X86_32
1435 static inline int IO_APIC_irq_trigger(int irq)
1439 for (apic = 0; apic < nr_ioapics; apic++) {
1440 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1441 idx = find_irq_entry(apic, pin, mp_INT);
1442 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1443 return irq_trigger(idx);
1447 * nonexistent IRQs are edge default
1452 static inline int IO_APIC_irq_trigger(int irq)
1458 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1461 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1462 trigger == IOAPIC_LEVEL)
1463 desc->status |= IRQ_LEVEL;
1465 desc->status &= ~IRQ_LEVEL;
1467 #ifdef CONFIG_INTR_REMAP
1468 if (irq_remapped(irq)) {
1469 desc->status |= IRQ_MOVE_PCNTXT;
1471 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1475 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1476 handle_edge_irq, "edge");
1480 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1481 trigger == IOAPIC_LEVEL)
1482 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1486 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1487 handle_edge_irq, "edge");
1490 static int setup_ioapic_entry(int apic, int irq,
1491 struct IO_APIC_route_entry *entry,
1492 unsigned int destination, int trigger,
1493 int polarity, int vector)
1496 * add it to the IO-APIC irq-routing table:
1498 memset(entry,0,sizeof(*entry));
1500 #ifdef CONFIG_INTR_REMAP
1501 if (intr_remapping_enabled) {
1502 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1504 struct IR_IO_APIC_route_entry *ir_entry =
1505 (struct IR_IO_APIC_route_entry *) entry;
1509 panic("No mapping iommu for ioapic %d\n", apic);
1511 index = alloc_irte(iommu, irq, 1);
1513 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1515 memset(&irte, 0, sizeof(irte));
1518 irte.dst_mode = INT_DEST_MODE;
1519 irte.trigger_mode = trigger;
1520 irte.dlvry_mode = INT_DELIVERY_MODE;
1521 irte.vector = vector;
1522 irte.dest_id = IRTE_DEST(destination);
1524 modify_irte(irq, &irte);
1526 ir_entry->index2 = (index >> 15) & 0x1;
1528 ir_entry->format = 1;
1529 ir_entry->index = (index & 0x7fff);
1533 entry->delivery_mode = INT_DELIVERY_MODE;
1534 entry->dest_mode = INT_DEST_MODE;
1535 entry->dest = destination;
1538 entry->mask = 0; /* enable IRQ */
1539 entry->trigger = trigger;
1540 entry->polarity = polarity;
1541 entry->vector = vector;
1543 /* Mask level triggered irqs.
1544 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1551 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc,
1552 int trigger, int polarity)
1554 struct irq_cfg *cfg;
1555 struct IO_APIC_route_entry entry;
1558 if (!IO_APIC_IRQ(irq))
1561 cfg = desc->chip_data;
1563 if (assign_irq_vector(irq, cfg, TARGET_CPUS))
1566 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
1568 apic_printk(APIC_VERBOSE,KERN_DEBUG
1569 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1570 "IRQ %d Mode:%i Active:%i)\n",
1571 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1572 irq, trigger, polarity);
1575 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1576 dest, trigger, polarity, cfg->vector)) {
1577 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1578 mp_ioapics[apic].mp_apicid, pin);
1579 __clear_irq_vector(irq, cfg);
1583 ioapic_register_intr(irq, desc, trigger);
1584 if (irq < NR_IRQS_LEGACY)
1585 disable_8259A_irq(irq);
1587 ioapic_write_entry(apic, pin, entry);
1590 static void __init setup_IO_APIC_irqs(void)
1592 int apic, pin, idx, irq;
1594 struct irq_desc *desc;
1595 struct irq_cfg *cfg;
1596 int cpu = boot_cpu_id;
1598 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1600 for (apic = 0; apic < nr_ioapics; apic++) {
1601 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1603 idx = find_irq_entry(apic, pin, mp_INT);
1607 apic_printk(APIC_VERBOSE,
1608 KERN_DEBUG " %d-%d",
1609 mp_ioapics[apic].mp_apicid,
1612 apic_printk(APIC_VERBOSE, " %d-%d",
1613 mp_ioapics[apic].mp_apicid,
1618 apic_printk(APIC_VERBOSE,
1619 " (apicid-pin) not connected\n");
1623 irq = pin_2_irq(idx, apic, pin);
1624 #ifdef CONFIG_X86_32
1625 if (multi_timer_check(apic, irq))
1628 desc = irq_to_desc_alloc_cpu(irq, cpu);
1630 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1633 cfg = desc->chip_data;
1634 add_pin_to_irq_cpu(cfg, cpu, apic, pin);
1636 setup_IO_APIC_irq(apic, pin, irq, desc,
1637 irq_trigger(idx), irq_polarity(idx));
1642 apic_printk(APIC_VERBOSE,
1643 " (apicid-pin) not connected\n");
1647 * Set up the timer pin, possibly with the 8259A-master behind.
1649 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1652 struct IO_APIC_route_entry entry;
1654 #ifdef CONFIG_INTR_REMAP
1655 if (intr_remapping_enabled)
1659 memset(&entry, 0, sizeof(entry));
1662 * We use logical delivery to get the timer IRQ
1665 entry.dest_mode = INT_DEST_MODE;
1666 entry.mask = 1; /* mask IRQ now */
1667 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1668 entry.delivery_mode = INT_DELIVERY_MODE;
1671 entry.vector = vector;
1674 * The timer IRQ doesn't have to know that behind the
1675 * scene we may have a 8259A-master in AEOI mode ...
1677 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1680 * Add it to the IO-APIC irq-routing table:
1682 ioapic_write_entry(apic, pin, entry);
1686 __apicdebuginit(void) print_IO_APIC(void)
1689 union IO_APIC_reg_00 reg_00;
1690 union IO_APIC_reg_01 reg_01;
1691 union IO_APIC_reg_02 reg_02;
1692 union IO_APIC_reg_03 reg_03;
1693 unsigned long flags;
1694 struct irq_cfg *cfg;
1695 struct irq_desc *desc;
1698 if (apic_verbosity == APIC_QUIET)
1701 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1702 for (i = 0; i < nr_ioapics; i++)
1703 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1704 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1707 * We are a bit conservative about what we expect. We have to
1708 * know about every hardware change ASAP.
1710 printk(KERN_INFO "testing the IO APIC.......................\n");
1712 for (apic = 0; apic < nr_ioapics; apic++) {
1714 spin_lock_irqsave(&ioapic_lock, flags);
1715 reg_00.raw = io_apic_read(apic, 0);
1716 reg_01.raw = io_apic_read(apic, 1);
1717 if (reg_01.bits.version >= 0x10)
1718 reg_02.raw = io_apic_read(apic, 2);
1719 if (reg_01.bits.version >= 0x20)
1720 reg_03.raw = io_apic_read(apic, 3);
1721 spin_unlock_irqrestore(&ioapic_lock, flags);
1724 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1725 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1726 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1727 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1728 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1730 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1731 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1733 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1734 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1737 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1738 * but the value of reg_02 is read as the previous read register
1739 * value, so ignore it if reg_02 == reg_01.
1741 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1742 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1743 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1747 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1748 * or reg_03, but the value of reg_0[23] is read as the previous read
1749 * register value, so ignore it if reg_03 == reg_0[12].
1751 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1752 reg_03.raw != reg_01.raw) {
1753 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1754 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1757 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1759 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1760 " Stat Dmod Deli Vect: \n");
1762 for (i = 0; i <= reg_01.bits.entries; i++) {
1763 struct IO_APIC_route_entry entry;
1765 entry = ioapic_read_entry(apic, i);
1767 printk(KERN_DEBUG " %02x %03X ",
1772 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1777 entry.delivery_status,
1779 entry.delivery_mode,
1784 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1785 for_each_irq_desc(irq, desc) {
1786 struct irq_pin_list *entry;
1790 cfg = desc->chip_data;
1791 entry = cfg->irq_2_pin;
1794 printk(KERN_DEBUG "IRQ%d ", irq);
1796 printk("-> %d:%d", entry->apic, entry->pin);
1799 entry = entry->next;
1804 printk(KERN_INFO ".................................... done.\n");
1809 __apicdebuginit(void) print_APIC_bitfield(int base)
1814 if (apic_verbosity == APIC_QUIET)
1817 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1818 for (i = 0; i < 8; i++) {
1819 v = apic_read(base + i*0x10);
1820 for (j = 0; j < 32; j++) {
1830 __apicdebuginit(void) print_local_APIC(void *dummy)
1832 unsigned int v, ver, maxlvt;
1835 if (apic_verbosity == APIC_QUIET)
1838 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1839 smp_processor_id(), hard_smp_processor_id());
1840 v = apic_read(APIC_ID);
1841 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1842 v = apic_read(APIC_LVR);
1843 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1844 ver = GET_APIC_VERSION(v);
1845 maxlvt = lapic_get_maxlvt();
1847 v = apic_read(APIC_TASKPRI);
1848 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1850 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1851 if (!APIC_XAPIC(ver)) {
1852 v = apic_read(APIC_ARBPRI);
1853 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1854 v & APIC_ARBPRI_MASK);
1856 v = apic_read(APIC_PROCPRI);
1857 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1861 * Remote read supported only in the 82489DX and local APIC for
1862 * Pentium processors.
1864 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1865 v = apic_read(APIC_RRR);
1866 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1869 v = apic_read(APIC_LDR);
1870 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1871 if (!x2apic_enabled()) {
1872 v = apic_read(APIC_DFR);
1873 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1875 v = apic_read(APIC_SPIV);
1876 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1878 printk(KERN_DEBUG "... APIC ISR field:\n");
1879 print_APIC_bitfield(APIC_ISR);
1880 printk(KERN_DEBUG "... APIC TMR field:\n");
1881 print_APIC_bitfield(APIC_TMR);
1882 printk(KERN_DEBUG "... APIC IRR field:\n");
1883 print_APIC_bitfield(APIC_IRR);
1885 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1886 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1887 apic_write(APIC_ESR, 0);
1889 v = apic_read(APIC_ESR);
1890 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1893 icr = apic_icr_read();
1894 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1895 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1897 v = apic_read(APIC_LVTT);
1898 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1900 if (maxlvt > 3) { /* PC is LVT#4. */
1901 v = apic_read(APIC_LVTPC);
1902 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1904 v = apic_read(APIC_LVT0);
1905 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1906 v = apic_read(APIC_LVT1);
1907 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1909 if (maxlvt > 2) { /* ERR is LVT#3. */
1910 v = apic_read(APIC_LVTERR);
1911 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1914 v = apic_read(APIC_TMICT);
1915 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1916 v = apic_read(APIC_TMCCT);
1917 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1918 v = apic_read(APIC_TDCR);
1919 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1923 __apicdebuginit(void) print_all_local_APICs(void)
1928 for_each_online_cpu(cpu)
1929 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1933 __apicdebuginit(void) print_PIC(void)
1936 unsigned long flags;
1938 if (apic_verbosity == APIC_QUIET)
1941 printk(KERN_DEBUG "\nprinting PIC contents\n");
1943 spin_lock_irqsave(&i8259A_lock, flags);
1945 v = inb(0xa1) << 8 | inb(0x21);
1946 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1948 v = inb(0xa0) << 8 | inb(0x20);
1949 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1953 v = inb(0xa0) << 8 | inb(0x20);
1957 spin_unlock_irqrestore(&i8259A_lock, flags);
1959 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1961 v = inb(0x4d1) << 8 | inb(0x4d0);
1962 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1965 __apicdebuginit(int) print_all_ICs(void)
1968 print_all_local_APICs();
1974 fs_initcall(print_all_ICs);
1977 /* Where if anywhere is the i8259 connect in external int mode */
1978 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1980 void __init enable_IO_APIC(void)
1982 union IO_APIC_reg_01 reg_01;
1983 int i8259_apic, i8259_pin;
1985 unsigned long flags;
1987 #ifdef CONFIG_X86_32
1990 for (i = 0; i < MAX_PIRQS; i++)
1991 pirq_entries[i] = -1;
1995 * The number of IO-APIC IRQ registers (== #pins):
1997 for (apic = 0; apic < nr_ioapics; apic++) {
1998 spin_lock_irqsave(&ioapic_lock, flags);
1999 reg_01.raw = io_apic_read(apic, 1);
2000 spin_unlock_irqrestore(&ioapic_lock, flags);
2001 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2003 for(apic = 0; apic < nr_ioapics; apic++) {
2005 /* See if any of the pins is in ExtINT mode */
2006 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2007 struct IO_APIC_route_entry entry;
2008 entry = ioapic_read_entry(apic, pin);
2010 /* If the interrupt line is enabled and in ExtInt mode
2011 * I have found the pin where the i8259 is connected.
2013 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2014 ioapic_i8259.apic = apic;
2015 ioapic_i8259.pin = pin;
2021 /* Look to see what if the MP table has reported the ExtINT */
2022 /* If we could not find the appropriate pin by looking at the ioapic
2023 * the i8259 probably is not connected the ioapic but give the
2024 * mptable a chance anyway.
2026 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2027 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2028 /* Trust the MP table if nothing is setup in the hardware */
2029 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2030 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2031 ioapic_i8259.pin = i8259_pin;
2032 ioapic_i8259.apic = i8259_apic;
2034 /* Complain if the MP table and the hardware disagree */
2035 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2036 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2038 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2042 * Do not trust the IO-APIC being empty at bootup
2048 * Not an __init, needed by the reboot code
2050 void disable_IO_APIC(void)
2053 * Clear the IO-APIC before rebooting:
2058 * If the i8259 is routed through an IOAPIC
2059 * Put that IOAPIC in virtual wire mode
2060 * so legacy interrupts can be delivered.
2062 if (ioapic_i8259.pin != -1) {
2063 struct IO_APIC_route_entry entry;
2065 memset(&entry, 0, sizeof(entry));
2066 entry.mask = 0; /* Enabled */
2067 entry.trigger = 0; /* Edge */
2069 entry.polarity = 0; /* High */
2070 entry.delivery_status = 0;
2071 entry.dest_mode = 0; /* Physical */
2072 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2074 entry.dest = read_apic_id();
2077 * Add it to the IO-APIC irq-routing table:
2079 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2082 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2085 #ifdef CONFIG_X86_32
2087 * function to set the IO-APIC physical IDs based on the
2088 * values stored in the MPC table.
2090 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2093 static void __init setup_ioapic_ids_from_mpc(void)
2095 union IO_APIC_reg_00 reg_00;
2096 physid_mask_t phys_id_present_map;
2099 unsigned char old_id;
2100 unsigned long flags;
2102 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2106 * Don't check I/O APIC IDs for xAPIC systems. They have
2107 * no meaning without the serial APIC bus.
2109 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2110 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2113 * This is broken; anything with a real cpu count has to
2114 * circumvent this idiocy regardless.
2116 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2119 * Set the IOAPIC ID to the value stored in the MPC table.
2121 for (apic = 0; apic < nr_ioapics; apic++) {
2123 /* Read the register 0 value */
2124 spin_lock_irqsave(&ioapic_lock, flags);
2125 reg_00.raw = io_apic_read(apic, 0);
2126 spin_unlock_irqrestore(&ioapic_lock, flags);
2128 old_id = mp_ioapics[apic].mp_apicid;
2130 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
2131 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2132 apic, mp_ioapics[apic].mp_apicid);
2133 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2135 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
2139 * Sanity check, is the ID really free? Every APIC in a
2140 * system must have a unique ID or we get lots of nice
2141 * 'stuck on smp_invalidate_needed IPI wait' messages.
2143 if (check_apicid_used(phys_id_present_map,
2144 mp_ioapics[apic].mp_apicid)) {
2145 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2146 apic, mp_ioapics[apic].mp_apicid);
2147 for (i = 0; i < get_physical_broadcast(); i++)
2148 if (!physid_isset(i, phys_id_present_map))
2150 if (i >= get_physical_broadcast())
2151 panic("Max APIC ID exceeded!\n");
2152 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2154 physid_set(i, phys_id_present_map);
2155 mp_ioapics[apic].mp_apicid = i;
2158 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
2159 apic_printk(APIC_VERBOSE, "Setting %d in the "
2160 "phys_id_present_map\n",
2161 mp_ioapics[apic].mp_apicid);
2162 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2167 * We need to adjust the IRQ routing table
2168 * if the ID changed.
2170 if (old_id != mp_ioapics[apic].mp_apicid)
2171 for (i = 0; i < mp_irq_entries; i++)
2172 if (mp_irqs[i].mp_dstapic == old_id)
2173 mp_irqs[i].mp_dstapic
2174 = mp_ioapics[apic].mp_apicid;
2177 * Read the right value from the MPC table and
2178 * write it into the ID register.
2180 apic_printk(APIC_VERBOSE, KERN_INFO
2181 "...changing IO-APIC physical APIC ID to %d ...",
2182 mp_ioapics[apic].mp_apicid);
2184 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
2185 spin_lock_irqsave(&ioapic_lock, flags);
2186 io_apic_write(apic, 0, reg_00.raw);
2187 spin_unlock_irqrestore(&ioapic_lock, flags);
2192 spin_lock_irqsave(&ioapic_lock, flags);
2193 reg_00.raw = io_apic_read(apic, 0);
2194 spin_unlock_irqrestore(&ioapic_lock, flags);
2195 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
2196 printk("could not set ID!\n");
2198 apic_printk(APIC_VERBOSE, " ok.\n");
2203 int no_timer_check __initdata;
2205 static int __init notimercheck(char *s)
2210 __setup("no_timer_check", notimercheck);
2213 * There is a nasty bug in some older SMP boards, their mptable lies
2214 * about the timer IRQ. We do the following to work around the situation:
2216 * - timer IRQ defaults to IO-APIC IRQ
2217 * - if this function detects that timer IRQs are defunct, then we fall
2218 * back to ISA timer IRQs
2220 static int __init timer_irq_works(void)
2222 unsigned long t1 = jiffies;
2223 unsigned long flags;
2228 local_save_flags(flags);
2230 /* Let ten ticks pass... */
2231 mdelay((10 * 1000) / HZ);
2232 local_irq_restore(flags);
2235 * Expect a few ticks at least, to be sure some possible
2236 * glue logic does not lock up after one or two first
2237 * ticks in a non-ExtINT mode. Also the local APIC
2238 * might have cached one ExtINT interrupt. Finally, at
2239 * least one tick may be lost due to delays.
2243 if (time_after(jiffies, t1 + 4))
2249 * In the SMP+IOAPIC case it might happen that there are an unspecified
2250 * number of pending IRQ events unhandled. These cases are very rare,
2251 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2252 * better to do it this way as thus we do not have to be aware of
2253 * 'pending' interrupts in the IRQ path, except at this point.
2256 * Edge triggered needs to resend any interrupt
2257 * that was delayed but this is now handled in the device
2262 * Starting up a edge-triggered IO-APIC interrupt is
2263 * nasty - we need to make sure that we get the edge.
2264 * If it is already asserted for some reason, we need
2265 * return 1 to indicate that is was pending.
2267 * This is not complete - we should be able to fake
2268 * an edge even if it isn't on the 8259A...
2271 static unsigned int startup_ioapic_irq(unsigned int irq)
2273 int was_pending = 0;
2274 unsigned long flags;
2275 struct irq_cfg *cfg;
2277 spin_lock_irqsave(&ioapic_lock, flags);
2278 if (irq < NR_IRQS_LEGACY) {
2279 disable_8259A_irq(irq);
2280 if (i8259A_irq_pending(irq))
2284 __unmask_IO_APIC_irq(cfg);
2285 spin_unlock_irqrestore(&ioapic_lock, flags);
2290 #ifdef CONFIG_X86_64
2291 static int ioapic_retrigger_irq(unsigned int irq)
2294 struct irq_cfg *cfg = irq_cfg(irq);
2295 unsigned long flags;
2297 spin_lock_irqsave(&vector_lock, flags);
2298 send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2299 spin_unlock_irqrestore(&vector_lock, flags);
2304 static int ioapic_retrigger_irq(unsigned int irq)
2306 send_IPI_self(irq_cfg(irq)->vector);
2313 * Level and edge triggered IO-APIC interrupts need different handling,
2314 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2315 * handled with the level-triggered descriptor, but that one has slightly
2316 * more overhead. Level-triggered interrupts cannot be handled with the
2317 * edge-triggered handler, without risking IRQ storms and other ugly
2323 #ifdef CONFIG_INTR_REMAP
2324 static void ir_irq_migration(struct work_struct *work);
2326 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2329 * Migrate the IO-APIC irq in the presence of intr-remapping.
2331 * For edge triggered, irq migration is a simple atomic update(of vector
2332 * and cpu destination) of IRTE and flush the hardware cache.
2334 * For level triggered, we need to modify the io-apic RTE aswell with the update
2335 * vector information, along with modifying IRTE with vector and destination.
2336 * So irq migration for level triggered is little bit more complex compared to
2337 * edge triggered migration. But the good news is, we use the same algorithm
2338 * for level triggered migration as we have today, only difference being,
2339 * we now initiate the irq migration from process context instead of the
2340 * interrupt context.
2342 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2343 * suppression) to the IO-APIC, level triggered irq migration will also be
2344 * as simple as edge triggered migration and we can do the irq migration
2345 * with a simple atomic update to IO-APIC RTE.
2348 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2350 struct irq_cfg *cfg;
2352 int modify_ioapic_rte;
2354 unsigned long flags;
2357 if (!cpumask_intersects(mask, cpu_online_mask))
2361 if (get_irte(irq, &irte))
2364 cfg = desc->chip_data;
2365 if (assign_irq_vector(irq, cfg, mask))
2368 set_extra_move_desc(desc, mask);
2370 dest = cpu_mask_to_apicid_and(cfg->domain, mask);
2372 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2373 if (modify_ioapic_rte) {
2374 spin_lock_irqsave(&ioapic_lock, flags);
2375 __target_IO_APIC_irq(irq, dest, cfg);
2376 spin_unlock_irqrestore(&ioapic_lock, flags);
2379 irte.vector = cfg->vector;
2380 irte.dest_id = IRTE_DEST(dest);
2383 * Modified the IRTE and flushes the Interrupt entry cache.
2385 modify_irte(irq, &irte);
2387 if (cfg->move_in_progress)
2388 send_cleanup_vector(cfg);
2390 cpumask_copy(&desc->affinity, mask);
2393 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2396 struct irq_cfg *cfg = desc->chip_data;
2398 mask_IO_APIC_irq_desc(desc);
2400 if (io_apic_level_ack_pending(cfg)) {
2402 * Interrupt in progress. Migrating irq now will change the
2403 * vector information in the IO-APIC RTE and that will confuse
2404 * the EOI broadcast performed by cpu.
2405 * So, delay the irq migration to the next instance.
2407 schedule_delayed_work(&ir_migration_work, 1);
2411 /* everthing is clear. we have right of way */
2412 migrate_ioapic_irq_desc(desc, &desc->pending_mask);
2415 desc->status &= ~IRQ_MOVE_PENDING;
2416 cpumask_clear(&desc->pending_mask);
2419 unmask_IO_APIC_irq_desc(desc);
2424 static void ir_irq_migration(struct work_struct *work)
2427 struct irq_desc *desc;
2429 for_each_irq_desc(irq, desc) {
2433 if (desc->status & IRQ_MOVE_PENDING) {
2434 unsigned long flags;
2436 spin_lock_irqsave(&desc->lock, flags);
2437 if (!desc->chip->set_affinity ||
2438 !(desc->status & IRQ_MOVE_PENDING)) {
2439 desc->status &= ~IRQ_MOVE_PENDING;
2440 spin_unlock_irqrestore(&desc->lock, flags);
2444 desc->chip->set_affinity(irq, &desc->pending_mask);
2445 spin_unlock_irqrestore(&desc->lock, flags);
2451 * Migrates the IRQ destination in the process context.
2453 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2454 const struct cpumask *mask)
2456 if (desc->status & IRQ_LEVEL) {
2457 desc->status |= IRQ_MOVE_PENDING;
2458 cpumask_copy(&desc->pending_mask, mask);
2459 migrate_irq_remapped_level_desc(desc);
2463 migrate_ioapic_irq_desc(desc, mask);
2465 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2466 const struct cpumask *mask)
2468 struct irq_desc *desc = irq_to_desc(irq);
2470 set_ir_ioapic_affinity_irq_desc(desc, mask);
2474 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2476 unsigned vector, me;
2478 #ifdef CONFIG_X86_64
2483 me = smp_processor_id();
2484 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2486 struct irq_desc *desc;
2487 struct irq_cfg *cfg;
2488 irq = __get_cpu_var(vector_irq)[vector];
2493 desc = irq_to_desc(irq);
2498 spin_lock(&desc->lock);
2499 if (!cfg->move_cleanup_count)
2502 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2505 __get_cpu_var(vector_irq)[vector] = -1;
2506 cfg->move_cleanup_count--;
2508 spin_unlock(&desc->lock);
2514 static void irq_complete_move(struct irq_desc **descp)
2516 struct irq_desc *desc = *descp;
2517 struct irq_cfg *cfg = desc->chip_data;
2518 unsigned vector, me;
2520 if (likely(!cfg->move_in_progress)) {
2521 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2522 if (likely(!cfg->move_desc_pending))
2525 /* domain is not change, but affinity is changed */
2526 me = smp_processor_id();
2527 if (cpu_isset(me, desc->affinity)) {
2528 *descp = desc = move_irq_desc(desc, me);
2529 /* get the new one */
2530 cfg = desc->chip_data;
2531 cfg->move_desc_pending = 0;
2537 vector = ~get_irq_regs()->orig_ax;
2538 me = smp_processor_id();
2539 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2540 *descp = desc = move_irq_desc(desc, me);
2541 /* get the new one */
2542 cfg = desc->chip_data;
2545 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2546 send_cleanup_vector(cfg);
2549 static inline void irq_complete_move(struct irq_desc **descp) {}
2552 #ifdef CONFIG_INTR_REMAP
2553 static void ack_x2apic_level(unsigned int irq)
2558 static void ack_x2apic_edge(unsigned int irq)
2565 static void ack_apic_edge(unsigned int irq)
2567 struct irq_desc *desc = irq_to_desc(irq);
2569 irq_complete_move(&desc);
2570 move_native_irq(irq);
2574 atomic_t irq_mis_count;
2576 static void ack_apic_level(unsigned int irq)
2578 struct irq_desc *desc = irq_to_desc(irq);
2580 #ifdef CONFIG_X86_32
2584 struct irq_cfg *cfg;
2585 int do_unmask_irq = 0;
2587 irq_complete_move(&desc);
2588 #ifdef CONFIG_GENERIC_PENDING_IRQ
2589 /* If we are moving the irq we need to mask it */
2590 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2592 mask_IO_APIC_irq_desc(desc);
2596 #ifdef CONFIG_X86_32
2598 * It appears there is an erratum which affects at least version 0x11
2599 * of I/O APIC (that's the 82093AA and cores integrated into various
2600 * chipsets). Under certain conditions a level-triggered interrupt is
2601 * erroneously delivered as edge-triggered one but the respective IRR
2602 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2603 * message but it will never arrive and further interrupts are blocked
2604 * from the source. The exact reason is so far unknown, but the
2605 * phenomenon was observed when two consecutive interrupt requests
2606 * from a given source get delivered to the same CPU and the source is
2607 * temporarily disabled in between.
2609 * A workaround is to simulate an EOI message manually. We achieve it
2610 * by setting the trigger mode to edge and then to level when the edge
2611 * trigger mode gets detected in the TMR of a local APIC for a
2612 * level-triggered interrupt. We mask the source for the time of the
2613 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2614 * The idea is from Manfred Spraul. --macro
2616 cfg = desc->chip_data;
2619 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2623 * We must acknowledge the irq before we move it or the acknowledge will
2624 * not propagate properly.
2628 /* Now we can move and renable the irq */
2629 if (unlikely(do_unmask_irq)) {
2630 /* Only migrate the irq if the ack has been received.
2632 * On rare occasions the broadcast level triggered ack gets
2633 * delayed going to ioapics, and if we reprogram the
2634 * vector while Remote IRR is still set the irq will never
2637 * To prevent this scenario we read the Remote IRR bit
2638 * of the ioapic. This has two effects.
2639 * - On any sane system the read of the ioapic will
2640 * flush writes (and acks) going to the ioapic from
2642 * - We get to see if the ACK has actually been delivered.
2644 * Based on failed experiments of reprogramming the
2645 * ioapic entry from outside of irq context starting
2646 * with masking the ioapic entry and then polling until
2647 * Remote IRR was clear before reprogramming the
2648 * ioapic I don't trust the Remote IRR bit to be
2649 * completey accurate.
2651 * However there appears to be no other way to plug
2652 * this race, so if the Remote IRR bit is not
2653 * accurate and is causing problems then it is a hardware bug
2654 * and you can go talk to the chipset vendor about it.
2656 cfg = desc->chip_data;
2657 if (!io_apic_level_ack_pending(cfg))
2658 move_masked_irq(irq);
2659 unmask_IO_APIC_irq_desc(desc);
2662 #ifdef CONFIG_X86_32
2663 if (!(v & (1 << (i & 0x1f)))) {
2664 atomic_inc(&irq_mis_count);
2665 spin_lock(&ioapic_lock);
2666 __mask_and_edge_IO_APIC_irq(cfg);
2667 __unmask_and_level_IO_APIC_irq(cfg);
2668 spin_unlock(&ioapic_lock);
2673 static struct irq_chip ioapic_chip __read_mostly = {
2675 .startup = startup_ioapic_irq,
2676 .mask = mask_IO_APIC_irq,
2677 .unmask = unmask_IO_APIC_irq,
2678 .ack = ack_apic_edge,
2679 .eoi = ack_apic_level,
2681 .set_affinity = set_ioapic_affinity_irq,
2683 .retrigger = ioapic_retrigger_irq,
2686 #ifdef CONFIG_INTR_REMAP
2687 static struct irq_chip ir_ioapic_chip __read_mostly = {
2688 .name = "IR-IO-APIC",
2689 .startup = startup_ioapic_irq,
2690 .mask = mask_IO_APIC_irq,
2691 .unmask = unmask_IO_APIC_irq,
2692 .ack = ack_x2apic_edge,
2693 .eoi = ack_x2apic_level,
2695 .set_affinity = set_ir_ioapic_affinity_irq,
2697 .retrigger = ioapic_retrigger_irq,
2701 static inline void init_IO_APIC_traps(void)
2704 struct irq_desc *desc;
2705 struct irq_cfg *cfg;
2708 * NOTE! The local APIC isn't very good at handling
2709 * multiple interrupts at the same interrupt level.
2710 * As the interrupt level is determined by taking the
2711 * vector number and shifting that right by 4, we
2712 * want to spread these out a bit so that they don't
2713 * all fall in the same interrupt level.
2715 * Also, we've got to be careful not to trash gate
2716 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2718 for_each_irq_desc(irq, desc) {
2722 cfg = desc->chip_data;
2723 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2725 * Hmm.. We don't have an entry for this,
2726 * so default to an old-fashioned 8259
2727 * interrupt if we can..
2729 if (irq < NR_IRQS_LEGACY)
2730 make_8259A_irq(irq);
2732 /* Strange. Oh, well.. */
2733 desc->chip = &no_irq_chip;
2739 * The local APIC irq-chip implementation:
2742 static void mask_lapic_irq(unsigned int irq)
2746 v = apic_read(APIC_LVT0);
2747 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2750 static void unmask_lapic_irq(unsigned int irq)
2754 v = apic_read(APIC_LVT0);
2755 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2758 static void ack_lapic_irq(unsigned int irq)
2763 static struct irq_chip lapic_chip __read_mostly = {
2764 .name = "local-APIC",
2765 .mask = mask_lapic_irq,
2766 .unmask = unmask_lapic_irq,
2767 .ack = ack_lapic_irq,
2770 static void lapic_register_intr(int irq, struct irq_desc *desc)
2772 desc->status &= ~IRQ_LEVEL;
2773 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2777 static void __init setup_nmi(void)
2780 * Dirty trick to enable the NMI watchdog ...
2781 * We put the 8259A master into AEOI mode and
2782 * unmask on all local APICs LVT0 as NMI.
2784 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2785 * is from Maciej W. Rozycki - so we do not have to EOI from
2786 * the NMI handler or the timer interrupt.
2788 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2790 enable_NMI_through_LVT0();
2792 apic_printk(APIC_VERBOSE, " done.\n");
2796 * This looks a bit hackish but it's about the only one way of sending
2797 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2798 * not support the ExtINT mode, unfortunately. We need to send these
2799 * cycles as some i82489DX-based boards have glue logic that keeps the
2800 * 8259A interrupt line asserted until INTA. --macro
2802 static inline void __init unlock_ExtINT_logic(void)
2805 struct IO_APIC_route_entry entry0, entry1;
2806 unsigned char save_control, save_freq_select;
2808 pin = find_isa_irq_pin(8, mp_INT);
2813 apic = find_isa_irq_apic(8, mp_INT);
2819 entry0 = ioapic_read_entry(apic, pin);
2820 clear_IO_APIC_pin(apic, pin);
2822 memset(&entry1, 0, sizeof(entry1));
2824 entry1.dest_mode = 0; /* physical delivery */
2825 entry1.mask = 0; /* unmask IRQ now */
2826 entry1.dest = hard_smp_processor_id();
2827 entry1.delivery_mode = dest_ExtINT;
2828 entry1.polarity = entry0.polarity;
2832 ioapic_write_entry(apic, pin, entry1);
2834 save_control = CMOS_READ(RTC_CONTROL);
2835 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2836 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2838 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2843 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2847 CMOS_WRITE(save_control, RTC_CONTROL);
2848 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2849 clear_IO_APIC_pin(apic, pin);
2851 ioapic_write_entry(apic, pin, entry0);
2854 static int disable_timer_pin_1 __initdata;
2855 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2856 static int __init disable_timer_pin_setup(char *arg)
2858 disable_timer_pin_1 = 1;
2861 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2863 int timer_through_8259 __initdata;
2866 * This code may look a bit paranoid, but it's supposed to cooperate with
2867 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2868 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2869 * fanatically on his truly buggy board.
2871 * FIXME: really need to revamp this for all platforms.
2873 static inline void __init check_timer(void)
2875 struct irq_desc *desc = irq_to_desc(0);
2876 struct irq_cfg *cfg = desc->chip_data;
2877 int cpu = boot_cpu_id;
2878 int apic1, pin1, apic2, pin2;
2879 unsigned long flags;
2883 local_irq_save(flags);
2885 ver = apic_read(APIC_LVR);
2886 ver = GET_APIC_VERSION(ver);
2889 * get/set the timer IRQ vector:
2891 disable_8259A_irq(0);
2892 assign_irq_vector(0, cfg, TARGET_CPUS);
2895 * As IRQ0 is to be enabled in the 8259A, the virtual
2896 * wire has to be disabled in the local APIC. Also
2897 * timer interrupts need to be acknowledged manually in
2898 * the 8259A for the i82489DX when using the NMI
2899 * watchdog as that APIC treats NMIs as level-triggered.
2900 * The AEOI mode will finish them in the 8259A
2903 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2905 #ifdef CONFIG_X86_32
2906 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2909 pin1 = find_isa_irq_pin(0, mp_INT);
2910 apic1 = find_isa_irq_apic(0, mp_INT);
2911 pin2 = ioapic_i8259.pin;
2912 apic2 = ioapic_i8259.apic;
2914 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2915 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2916 cfg->vector, apic1, pin1, apic2, pin2);
2919 * Some BIOS writers are clueless and report the ExtINTA
2920 * I/O APIC input from the cascaded 8259A as the timer
2921 * interrupt input. So just in case, if only one pin
2922 * was found above, try it both directly and through the
2926 #ifdef CONFIG_INTR_REMAP
2927 if (intr_remapping_enabled)
2928 panic("BIOS bug: timer not connected to IO-APIC");
2933 } else if (pin2 == -1) {
2940 * Ok, does IRQ0 through the IOAPIC work?
2943 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2944 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2946 unmask_IO_APIC_irq_desc(desc);
2947 if (timer_irq_works()) {
2948 if (nmi_watchdog == NMI_IO_APIC) {
2950 enable_8259A_irq(0);
2952 if (disable_timer_pin_1 > 0)
2953 clear_IO_APIC_pin(0, pin1);
2956 #ifdef CONFIG_INTR_REMAP
2957 if (intr_remapping_enabled)
2958 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2960 clear_IO_APIC_pin(apic1, pin1);
2962 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2963 "8254 timer not connected to IO-APIC\n");
2965 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2966 "(IRQ0) through the 8259A ...\n");
2967 apic_printk(APIC_QUIET, KERN_INFO
2968 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2970 * legacy devices should be connected to IO APIC #0
2972 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2973 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2974 unmask_IO_APIC_irq_desc(desc);
2975 enable_8259A_irq(0);
2976 if (timer_irq_works()) {
2977 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2978 timer_through_8259 = 1;
2979 if (nmi_watchdog == NMI_IO_APIC) {
2980 disable_8259A_irq(0);
2982 enable_8259A_irq(0);
2987 * Cleanup, just in case ...
2989 disable_8259A_irq(0);
2990 clear_IO_APIC_pin(apic2, pin2);
2991 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2994 if (nmi_watchdog == NMI_IO_APIC) {
2995 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2996 "through the IO-APIC - disabling NMI Watchdog!\n");
2997 nmi_watchdog = NMI_NONE;
2999 #ifdef CONFIG_X86_32
3003 apic_printk(APIC_QUIET, KERN_INFO
3004 "...trying to set up timer as Virtual Wire IRQ...\n");
3006 lapic_register_intr(0, desc);
3007 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3008 enable_8259A_irq(0);
3010 if (timer_irq_works()) {
3011 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3014 disable_8259A_irq(0);
3015 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3016 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3018 apic_printk(APIC_QUIET, KERN_INFO
3019 "...trying to set up timer as ExtINT IRQ...\n");
3023 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3025 unlock_ExtINT_logic();
3027 if (timer_irq_works()) {
3028 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3031 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3032 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3033 "report. Then try booting with the 'noapic' option.\n");
3035 local_irq_restore(flags);
3039 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3040 * to devices. However there may be an I/O APIC pin available for
3041 * this interrupt regardless. The pin may be left unconnected, but
3042 * typically it will be reused as an ExtINT cascade interrupt for
3043 * the master 8259A. In the MPS case such a pin will normally be
3044 * reported as an ExtINT interrupt in the MP table. With ACPI
3045 * there is no provision for ExtINT interrupts, and in the absence
3046 * of an override it would be treated as an ordinary ISA I/O APIC
3047 * interrupt, that is edge-triggered and unmasked by default. We
3048 * used to do this, but it caused problems on some systems because
3049 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3050 * the same ExtINT cascade interrupt to drive the local APIC of the
3051 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3052 * the I/O APIC in all cases now. No actual device should request
3053 * it anyway. --macro
3055 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3057 void __init setup_IO_APIC(void)
3060 #ifdef CONFIG_X86_32
3064 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3068 io_apic_irqs = ~PIC_IRQS;
3070 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3072 * Set up IO-APIC IRQ routing.
3074 #ifdef CONFIG_X86_32
3076 setup_ioapic_ids_from_mpc();
3079 setup_IO_APIC_irqs();
3080 init_IO_APIC_traps();
3085 * Called after all the initialization is done. If we didnt find any
3086 * APIC bugs then we can allow the modify fast path
3089 static int __init io_apic_bug_finalize(void)
3091 if (sis_apic_bug == -1)
3096 late_initcall(io_apic_bug_finalize);
3098 struct sysfs_ioapic_data {
3099 struct sys_device dev;
3100 struct IO_APIC_route_entry entry[0];
3102 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3104 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3106 struct IO_APIC_route_entry *entry;
3107 struct sysfs_ioapic_data *data;
3110 data = container_of(dev, struct sysfs_ioapic_data, dev);
3111 entry = data->entry;
3112 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3113 *entry = ioapic_read_entry(dev->id, i);
3118 static int ioapic_resume(struct sys_device *dev)
3120 struct IO_APIC_route_entry *entry;
3121 struct sysfs_ioapic_data *data;
3122 unsigned long flags;
3123 union IO_APIC_reg_00 reg_00;
3126 data = container_of(dev, struct sysfs_ioapic_data, dev);
3127 entry = data->entry;
3129 spin_lock_irqsave(&ioapic_lock, flags);
3130 reg_00.raw = io_apic_read(dev->id, 0);
3131 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
3132 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
3133 io_apic_write(dev->id, 0, reg_00.raw);
3135 spin_unlock_irqrestore(&ioapic_lock, flags);
3136 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3137 ioapic_write_entry(dev->id, i, entry[i]);
3142 static struct sysdev_class ioapic_sysdev_class = {
3144 .suspend = ioapic_suspend,
3145 .resume = ioapic_resume,
3148 static int __init ioapic_init_sysfs(void)
3150 struct sys_device * dev;
3153 error = sysdev_class_register(&ioapic_sysdev_class);
3157 for (i = 0; i < nr_ioapics; i++ ) {
3158 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3159 * sizeof(struct IO_APIC_route_entry);
3160 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3161 if (!mp_ioapic_data[i]) {
3162 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3165 dev = &mp_ioapic_data[i]->dev;
3167 dev->cls = &ioapic_sysdev_class;
3168 error = sysdev_register(dev);
3170 kfree(mp_ioapic_data[i]);
3171 mp_ioapic_data[i] = NULL;
3172 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3180 device_initcall(ioapic_init_sysfs);
3183 * Dynamic irq allocate and deallocation
3185 unsigned int create_irq_nr(unsigned int irq_want)
3187 /* Allocate an unused irq */
3190 unsigned long flags;
3191 struct irq_cfg *cfg_new = NULL;
3192 int cpu = boot_cpu_id;
3193 struct irq_desc *desc_new = NULL;
3196 spin_lock_irqsave(&vector_lock, flags);
3197 for (new = irq_want; new < NR_IRQS; new++) {
3198 if (platform_legacy_irq(new))
3201 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3203 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3206 cfg_new = desc_new->chip_data;
3208 if (cfg_new->vector != 0)
3210 if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0)
3214 spin_unlock_irqrestore(&vector_lock, flags);
3217 dynamic_irq_init(irq);
3218 /* restore it, in case dynamic_irq_init clear it */
3220 desc_new->chip_data = cfg_new;
3225 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3226 int create_irq(void)
3228 unsigned int irq_want;
3231 irq_want = nr_irqs_gsi;
3232 irq = create_irq_nr(irq_want);
3240 void destroy_irq(unsigned int irq)
3242 unsigned long flags;
3243 struct irq_cfg *cfg;
3244 struct irq_desc *desc;
3246 /* store it, in case dynamic_irq_cleanup clear it */
3247 desc = irq_to_desc(irq);
3248 cfg = desc->chip_data;
3249 dynamic_irq_cleanup(irq);
3250 /* connect back irq_cfg */
3252 desc->chip_data = cfg;
3254 #ifdef CONFIG_INTR_REMAP
3257 spin_lock_irqsave(&vector_lock, flags);
3258 __clear_irq_vector(irq, cfg);
3259 spin_unlock_irqrestore(&vector_lock, flags);
3263 * MSI message composition
3265 #ifdef CONFIG_PCI_MSI
3266 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3268 struct irq_cfg *cfg;
3273 err = assign_irq_vector(irq, cfg, TARGET_CPUS);
3277 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
3279 #ifdef CONFIG_INTR_REMAP
3280 if (irq_remapped(irq)) {
3285 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3286 BUG_ON(ir_index == -1);
3288 memset (&irte, 0, sizeof(irte));
3291 irte.dst_mode = INT_DEST_MODE;
3292 irte.trigger_mode = 0; /* edge */
3293 irte.dlvry_mode = INT_DELIVERY_MODE;
3294 irte.vector = cfg->vector;
3295 irte.dest_id = IRTE_DEST(dest);
3297 modify_irte(irq, &irte);
3299 msg->address_hi = MSI_ADDR_BASE_HI;
3300 msg->data = sub_handle;
3301 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3303 MSI_ADDR_IR_INDEX1(ir_index) |
3304 MSI_ADDR_IR_INDEX2(ir_index);
3308 msg->address_hi = MSI_ADDR_BASE_HI;
3311 ((INT_DEST_MODE == 0) ?
3312 MSI_ADDR_DEST_MODE_PHYSICAL:
3313 MSI_ADDR_DEST_MODE_LOGICAL) |
3314 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3315 MSI_ADDR_REDIRECTION_CPU:
3316 MSI_ADDR_REDIRECTION_LOWPRI) |
3317 MSI_ADDR_DEST_ID(dest);
3320 MSI_DATA_TRIGGER_EDGE |
3321 MSI_DATA_LEVEL_ASSERT |
3322 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3323 MSI_DATA_DELIVERY_FIXED:
3324 MSI_DATA_DELIVERY_LOWPRI) |
3325 MSI_DATA_VECTOR(cfg->vector);
3331 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3333 struct irq_desc *desc = irq_to_desc(irq);
3334 struct irq_cfg *cfg;
3338 dest = set_desc_affinity(desc, mask);
3339 if (dest == BAD_APICID)
3342 cfg = desc->chip_data;
3344 read_msi_msg_desc(desc, &msg);
3346 msg.data &= ~MSI_DATA_VECTOR_MASK;
3347 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3348 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3349 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3351 write_msi_msg_desc(desc, &msg);
3353 #ifdef CONFIG_INTR_REMAP
3355 * Migrate the MSI irq to another cpumask. This migration is
3356 * done in the process context using interrupt-remapping hardware.
3359 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3361 struct irq_desc *desc = irq_to_desc(irq);
3362 struct irq_cfg *cfg;
3366 if (get_irte(irq, &irte))
3369 dest = set_desc_affinity(desc, mask);
3370 if (dest == BAD_APICID)
3373 irte.vector = cfg->vector;
3374 irte.dest_id = IRTE_DEST(dest);
3377 * atomically update the IRTE with the new destination and vector.
3379 modify_irte(irq, &irte);
3382 * After this point, all the interrupts will start arriving
3383 * at the new destination. So, time to cleanup the previous
3384 * vector allocation.
3386 if (cfg->move_in_progress)
3387 send_cleanup_vector(cfg);
3391 #endif /* CONFIG_SMP */
3394 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3395 * which implement the MSI or MSI-X Capability Structure.
3397 static struct irq_chip msi_chip = {
3399 .unmask = unmask_msi_irq,
3400 .mask = mask_msi_irq,
3401 .ack = ack_apic_edge,
3403 .set_affinity = set_msi_irq_affinity,
3405 .retrigger = ioapic_retrigger_irq,
3408 #ifdef CONFIG_INTR_REMAP
3409 static struct irq_chip msi_ir_chip = {
3410 .name = "IR-PCI-MSI",
3411 .unmask = unmask_msi_irq,
3412 .mask = mask_msi_irq,
3413 .ack = ack_x2apic_edge,
3415 .set_affinity = ir_set_msi_irq_affinity,
3417 .retrigger = ioapic_retrigger_irq,
3421 * Map the PCI dev to the corresponding remapping hardware unit
3422 * and allocate 'nvec' consecutive interrupt-remapping table entries
3425 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3427 struct intel_iommu *iommu;
3430 iommu = map_dev_to_ir(dev);
3433 "Unable to map PCI %s to iommu\n", pci_name(dev));
3437 index = alloc_irte(iommu, irq, nvec);
3440 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3448 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3453 ret = msi_compose_msg(dev, irq, &msg);
3457 set_irq_msi(irq, msidesc);
3458 write_msi_msg(irq, &msg);
3460 #ifdef CONFIG_INTR_REMAP
3461 if (irq_remapped(irq)) {
3462 struct irq_desc *desc = irq_to_desc(irq);
3464 * irq migration in process context
3466 desc->status |= IRQ_MOVE_PCNTXT;
3467 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3470 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3472 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3477 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc)
3481 unsigned int irq_want;
3483 irq_want = nr_irqs_gsi;
3484 irq = create_irq_nr(irq_want);
3488 #ifdef CONFIG_INTR_REMAP
3489 if (!intr_remapping_enabled)
3492 ret = msi_alloc_irte(dev, irq, 1);
3497 ret = setup_msi_irq(dev, msidesc, irq);
3504 #ifdef CONFIG_INTR_REMAP
3511 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3514 int ret, sub_handle;
3515 struct msi_desc *msidesc;
3516 unsigned int irq_want;
3518 #ifdef CONFIG_INTR_REMAP
3519 struct intel_iommu *iommu = 0;
3523 irq_want = nr_irqs_gsi;
3525 list_for_each_entry(msidesc, &dev->msi_list, list) {
3526 irq = create_irq_nr(irq_want);
3530 #ifdef CONFIG_INTR_REMAP
3531 if (!intr_remapping_enabled)
3536 * allocate the consecutive block of IRTE's
3539 index = msi_alloc_irte(dev, irq, nvec);
3545 iommu = map_dev_to_ir(dev);
3551 * setup the mapping between the irq and the IRTE
3552 * base index, the sub_handle pointing to the
3553 * appropriate interrupt remap table entry.
3555 set_irte_irq(irq, iommu, index, sub_handle);
3559 ret = setup_msi_irq(dev, msidesc, irq);
3571 void arch_teardown_msi_irq(unsigned int irq)
3578 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3580 struct irq_desc *desc = irq_to_desc(irq);
3581 struct irq_cfg *cfg;
3585 dest = set_desc_affinity(desc, mask);
3586 if (dest == BAD_APICID)
3589 cfg = desc->chip_data;
3591 dmar_msi_read(irq, &msg);
3593 msg.data &= ~MSI_DATA_VECTOR_MASK;
3594 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3595 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3596 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3598 dmar_msi_write(irq, &msg);
3601 #endif /* CONFIG_SMP */
3603 struct irq_chip dmar_msi_type = {
3605 .unmask = dmar_msi_unmask,
3606 .mask = dmar_msi_mask,
3607 .ack = ack_apic_edge,
3609 .set_affinity = dmar_msi_set_affinity,
3611 .retrigger = ioapic_retrigger_irq,
3614 int arch_setup_dmar_msi(unsigned int irq)
3619 ret = msi_compose_msg(NULL, irq, &msg);
3622 dmar_msi_write(irq, &msg);
3623 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3629 #ifdef CONFIG_HPET_TIMER
3632 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3634 struct irq_desc *desc = irq_to_desc(irq);
3635 struct irq_cfg *cfg;
3639 dest = set_desc_affinity(desc, mask);
3640 if (dest == BAD_APICID)
3643 cfg = desc->chip_data;
3645 hpet_msi_read(irq, &msg);
3647 msg.data &= ~MSI_DATA_VECTOR_MASK;
3648 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3649 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3650 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3652 hpet_msi_write(irq, &msg);
3655 #endif /* CONFIG_SMP */
3657 struct irq_chip hpet_msi_type = {
3659 .unmask = hpet_msi_unmask,
3660 .mask = hpet_msi_mask,
3661 .ack = ack_apic_edge,
3663 .set_affinity = hpet_msi_set_affinity,
3665 .retrigger = ioapic_retrigger_irq,
3668 int arch_setup_hpet_msi(unsigned int irq)
3673 ret = msi_compose_msg(NULL, irq, &msg);
3677 hpet_msi_write(irq, &msg);
3678 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3685 #endif /* CONFIG_PCI_MSI */
3687 * Hypertransport interrupt support
3689 #ifdef CONFIG_HT_IRQ
3693 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3695 struct ht_irq_msg msg;
3696 fetch_ht_irq_msg(irq, &msg);
3698 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3699 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3701 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3702 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3704 write_ht_irq_msg(irq, &msg);
3707 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3709 struct irq_desc *desc = irq_to_desc(irq);
3710 struct irq_cfg *cfg;
3713 dest = set_desc_affinity(desc, mask);
3714 if (dest == BAD_APICID)
3717 cfg = desc->chip_data;
3719 target_ht_irq(irq, dest, cfg->vector);
3724 static struct irq_chip ht_irq_chip = {
3726 .mask = mask_ht_irq,
3727 .unmask = unmask_ht_irq,
3728 .ack = ack_apic_edge,
3730 .set_affinity = set_ht_irq_affinity,
3732 .retrigger = ioapic_retrigger_irq,
3735 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3737 struct irq_cfg *cfg;
3741 err = assign_irq_vector(irq, cfg, TARGET_CPUS);
3743 struct ht_irq_msg msg;
3746 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
3748 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3752 HT_IRQ_LOW_DEST_ID(dest) |
3753 HT_IRQ_LOW_VECTOR(cfg->vector) |
3754 ((INT_DEST_MODE == 0) ?
3755 HT_IRQ_LOW_DM_PHYSICAL :
3756 HT_IRQ_LOW_DM_LOGICAL) |
3757 HT_IRQ_LOW_RQEOI_EDGE |
3758 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3759 HT_IRQ_LOW_MT_FIXED :
3760 HT_IRQ_LOW_MT_ARBITRATED) |
3761 HT_IRQ_LOW_IRQ_MASKED;
3763 write_ht_irq_msg(irq, &msg);
3765 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3766 handle_edge_irq, "edge");
3768 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3772 #endif /* CONFIG_HT_IRQ */
3774 #ifdef CONFIG_X86_64
3776 * Re-target the irq to the specified CPU and enable the specified MMR located
3777 * on the specified blade to allow the sending of MSIs to the specified CPU.
3779 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3780 unsigned long mmr_offset)
3782 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3783 struct irq_cfg *cfg;
3785 unsigned long mmr_value;
3786 struct uv_IO_APIC_route_entry *entry;
3787 unsigned long flags;
3792 err = assign_irq_vector(irq, cfg, eligible_cpu);
3796 spin_lock_irqsave(&vector_lock, flags);
3797 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3799 spin_unlock_irqrestore(&vector_lock, flags);
3802 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3803 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3805 entry->vector = cfg->vector;
3806 entry->delivery_mode = INT_DELIVERY_MODE;
3807 entry->dest_mode = INT_DEST_MODE;
3808 entry->polarity = 0;
3811 entry->dest = cpu_mask_to_apicid(eligible_cpu);
3813 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3814 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3820 * Disable the specified MMR located on the specified blade so that MSIs are
3821 * longer allowed to be sent.
3823 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3825 unsigned long mmr_value;
3826 struct uv_IO_APIC_route_entry *entry;
3830 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3831 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3835 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3836 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3838 #endif /* CONFIG_X86_64 */
3840 int __init io_apic_get_redir_entries (int ioapic)
3842 union IO_APIC_reg_01 reg_01;
3843 unsigned long flags;
3845 spin_lock_irqsave(&ioapic_lock, flags);
3846 reg_01.raw = io_apic_read(ioapic, 1);
3847 spin_unlock_irqrestore(&ioapic_lock, flags);
3849 return reg_01.bits.entries;
3852 void __init probe_nr_irqs_gsi(void)
3857 for (idx = 0; idx < nr_ioapics; idx++)
3858 nr += io_apic_get_redir_entries(idx) + 1;
3860 if (nr > nr_irqs_gsi)
3864 /* --------------------------------------------------------------------------
3865 ACPI-based IOAPIC Configuration
3866 -------------------------------------------------------------------------- */
3870 #ifdef CONFIG_X86_32
3871 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3873 union IO_APIC_reg_00 reg_00;
3874 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3876 unsigned long flags;
3880 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3881 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3882 * supports up to 16 on one shared APIC bus.
3884 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3885 * advantage of new APIC bus architecture.
3888 if (physids_empty(apic_id_map))
3889 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3891 spin_lock_irqsave(&ioapic_lock, flags);
3892 reg_00.raw = io_apic_read(ioapic, 0);
3893 spin_unlock_irqrestore(&ioapic_lock, flags);
3895 if (apic_id >= get_physical_broadcast()) {
3896 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3897 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3898 apic_id = reg_00.bits.ID;
3902 * Every APIC in a system must have a unique ID or we get lots of nice
3903 * 'stuck on smp_invalidate_needed IPI wait' messages.
3905 if (check_apicid_used(apic_id_map, apic_id)) {
3907 for (i = 0; i < get_physical_broadcast(); i++) {
3908 if (!check_apicid_used(apic_id_map, i))
3912 if (i == get_physical_broadcast())
3913 panic("Max apic_id exceeded!\n");
3915 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3916 "trying %d\n", ioapic, apic_id, i);
3921 tmp = apicid_to_cpu_present(apic_id);
3922 physids_or(apic_id_map, apic_id_map, tmp);
3924 if (reg_00.bits.ID != apic_id) {
3925 reg_00.bits.ID = apic_id;
3927 spin_lock_irqsave(&ioapic_lock, flags);
3928 io_apic_write(ioapic, 0, reg_00.raw);
3929 reg_00.raw = io_apic_read(ioapic, 0);
3930 spin_unlock_irqrestore(&ioapic_lock, flags);
3933 if (reg_00.bits.ID != apic_id) {
3934 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3939 apic_printk(APIC_VERBOSE, KERN_INFO
3940 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3945 int __init io_apic_get_version(int ioapic)
3947 union IO_APIC_reg_01 reg_01;
3948 unsigned long flags;
3950 spin_lock_irqsave(&ioapic_lock, flags);
3951 reg_01.raw = io_apic_read(ioapic, 1);
3952 spin_unlock_irqrestore(&ioapic_lock, flags);
3954 return reg_01.bits.version;
3958 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3960 struct irq_desc *desc;
3961 struct irq_cfg *cfg;
3962 int cpu = boot_cpu_id;
3964 if (!IO_APIC_IRQ(irq)) {
3965 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3970 desc = irq_to_desc_alloc_cpu(irq, cpu);
3972 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3977 * IRQs < 16 are already in the irq_2_pin[] map
3979 if (irq >= NR_IRQS_LEGACY) {
3980 cfg = desc->chip_data;
3981 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3984 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3990 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3994 if (skip_ioapic_setup)
3997 for (i = 0; i < mp_irq_entries; i++)
3998 if (mp_irqs[i].mp_irqtype == mp_INT &&
3999 mp_irqs[i].mp_srcbusirq == bus_irq)
4001 if (i >= mp_irq_entries)
4004 *trigger = irq_trigger(i);
4005 *polarity = irq_polarity(i);
4009 #endif /* CONFIG_ACPI */
4012 * This function currently is only a helper for the i386 smp boot process where
4013 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4014 * so mask in all cases should simply be TARGET_CPUS
4017 void __init setup_ioapic_dest(void)
4019 int pin, ioapic, irq, irq_entry;
4020 struct irq_desc *desc;
4021 struct irq_cfg *cfg;
4022 const struct cpumask *mask;
4024 if (skip_ioapic_setup == 1)
4027 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4028 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4029 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4030 if (irq_entry == -1)
4032 irq = pin_2_irq(irq_entry, ioapic, pin);
4034 /* setup_IO_APIC_irqs could fail to get vector for some device
4035 * when you have too many devices, because at that time only boot
4038 desc = irq_to_desc(irq);
4039 cfg = desc->chip_data;
4041 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4042 irq_trigger(irq_entry),
4043 irq_polarity(irq_entry));
4049 * Honour affinities which have been set in early boot
4052 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4053 mask = &desc->affinity;
4057 #ifdef CONFIG_INTR_REMAP
4058 if (intr_remapping_enabled)
4059 set_ir_ioapic_affinity_irq_desc(desc, mask);
4062 set_ioapic_affinity_irq_desc(desc, mask);
4069 #define IOAPIC_RESOURCE_NAME_SIZE 11
4071 static struct resource *ioapic_resources;
4073 static struct resource * __init ioapic_setup_resources(void)
4076 struct resource *res;
4080 if (nr_ioapics <= 0)
4083 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4086 mem = alloc_bootmem(n);
4090 mem += sizeof(struct resource) * nr_ioapics;
4092 for (i = 0; i < nr_ioapics; i++) {
4094 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4095 sprintf(mem, "IOAPIC %u", i);
4096 mem += IOAPIC_RESOURCE_NAME_SIZE;
4100 ioapic_resources = res;
4105 void __init ioapic_init_mappings(void)
4107 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4108 struct resource *ioapic_res;
4111 ioapic_res = ioapic_setup_resources();
4112 for (i = 0; i < nr_ioapics; i++) {
4113 if (smp_found_config) {
4114 ioapic_phys = mp_ioapics[i].mp_apicaddr;
4115 #ifdef CONFIG_X86_32
4118 "WARNING: bogus zero IO-APIC "
4119 "address found in MPTABLE, "
4120 "disabling IO/APIC support!\n");
4121 smp_found_config = 0;
4122 skip_ioapic_setup = 1;
4123 goto fake_ioapic_page;
4127 #ifdef CONFIG_X86_32
4130 ioapic_phys = (unsigned long)
4131 alloc_bootmem_pages(PAGE_SIZE);
4132 ioapic_phys = __pa(ioapic_phys);
4134 set_fixmap_nocache(idx, ioapic_phys);
4135 apic_printk(APIC_VERBOSE,
4136 "mapped IOAPIC to %08lx (%08lx)\n",
4137 __fix_to_virt(idx), ioapic_phys);
4140 if (ioapic_res != NULL) {
4141 ioapic_res->start = ioapic_phys;
4142 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4148 static int __init ioapic_insert_resources(void)
4151 struct resource *r = ioapic_resources;
4155 "IO APIC resources could be not be allocated.\n");
4159 for (i = 0; i < nr_ioapics; i++) {
4160 insert_resource(&iomem_resource, r);
4167 /* Insert the IO APIC resources after PCI initialization has occured to handle
4168 * IO APICS that are mapped in on a BAR in PCI space. */
4169 late_initcall(ioapic_insert_resources);