3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
43 #define APIC_BUS_CYCLE_NS 1
45 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
46 #define apic_debug(fmt, arg...)
48 #define APIC_LVT_NUM 6
49 /* 14 is the version for Xeon and Pentium 8.4.8*/
50 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
51 #define LAPIC_MMIO_LENGTH (1 << 12)
52 /* followed define is not in apicdef.h */
53 #define APIC_SHORT_MASK 0xc0000
54 #define APIC_DEST_NOSHORT 0x0
55 #define APIC_DEST_MASK 0x800
56 #define MAX_APIC_VECTOR 256
58 #define VEC_POS(v) ((v) & (32 - 1))
59 #define REG_POS(v) (((v) >> 5) << 4)
61 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
63 return *((u32 *) (apic->regs + reg_off));
66 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
68 *((u32 *) (apic->regs + reg_off)) = val;
71 static inline int apic_test_and_set_vector(int vec, void *bitmap)
73 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
76 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
78 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
81 static inline void apic_set_vector(int vec, void *bitmap)
83 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86 static inline void apic_clear_vector(int vec, void *bitmap)
88 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91 static inline int apic_hw_enabled(struct kvm_lapic *apic)
93 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
96 static inline int apic_sw_enabled(struct kvm_lapic *apic)
98 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
101 static inline int apic_enabled(struct kvm_lapic *apic)
103 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
107 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
110 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
111 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
113 static inline int kvm_apic_id(struct kvm_lapic *apic)
115 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
118 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
120 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
123 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
125 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
128 static inline int apic_lvtt_period(struct kvm_lapic *apic)
130 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
133 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
134 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
135 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
136 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
137 LINT_MASK, LINT_MASK, /* LVT0-1 */
138 LVT_MASK /* LVTERR */
141 static int find_highest_vector(void *bitmap)
144 int word_offset = MAX_APIC_VECTOR >> 5;
146 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
149 if (likely(!word_offset && !word[0]))
152 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
155 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
157 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
160 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
162 apic_clear_vector(vec, apic->regs + APIC_IRR);
165 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
169 result = find_highest_vector(apic->regs + APIC_IRR);
170 ASSERT(result == -1 || result >= 16);
175 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
177 struct kvm_lapic *apic = vcpu->arch.apic;
182 highest_irr = apic_find_highest_irr(apic);
186 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
188 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
190 struct kvm_lapic *apic = vcpu->arch.apic;
192 if (!apic_test_and_set_irr(vec, apic)) {
193 /* a new pending irq is set in IRR */
195 apic_set_vector(vec, apic->regs + APIC_TMR);
197 apic_clear_vector(vec, apic->regs + APIC_TMR);
198 kvm_vcpu_kick(apic->vcpu);
204 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
208 result = find_highest_vector(apic->regs + APIC_ISR);
209 ASSERT(result == -1 || result >= 16);
214 static void apic_update_ppr(struct kvm_lapic *apic)
219 tpr = apic_get_reg(apic, APIC_TASKPRI);
220 isr = apic_find_highest_isr(apic);
221 isrv = (isr != -1) ? isr : 0;
223 if ((tpr & 0xf0) >= (isrv & 0xf0))
228 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
229 apic, ppr, isr, isrv);
231 apic_set_reg(apic, APIC_PROCPRI, ppr);
234 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
236 apic_set_reg(apic, APIC_TASKPRI, tpr);
237 apic_update_ppr(apic);
240 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
242 return kvm_apic_id(apic) == dest;
245 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
250 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
252 switch (apic_get_reg(apic, APIC_DFR)) {
254 if (logical_id & mda)
257 case APIC_DFR_CLUSTER:
258 if (((logical_id >> 4) == (mda >> 0x4))
259 && (logical_id & mda & 0xf))
263 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
264 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
271 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
272 int short_hand, int dest, int dest_mode)
275 struct kvm_lapic *target = vcpu->arch.apic;
277 apic_debug("target %p, source %p, dest 0x%x, "
278 "dest_mode 0x%x, short_hand 0x%x",
279 target, source, dest, dest_mode, short_hand);
282 switch (short_hand) {
283 case APIC_DEST_NOSHORT:
284 if (dest_mode == 0) {
286 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
290 result = kvm_apic_match_logical_addr(target, dest);
293 if (target == source)
296 case APIC_DEST_ALLINC:
299 case APIC_DEST_ALLBUT:
300 if (target != source)
304 printk(KERN_WARNING "Bad dest shorthand value %x\n",
313 * Add a pending IRQ into lapic.
314 * Return 1 if successfully added and 0 if discarded.
316 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
317 int vector, int level, int trig_mode)
319 int orig_irr, result = 0;
320 struct kvm_vcpu *vcpu = apic->vcpu;
322 switch (delivery_mode) {
325 /* FIXME add logic for vcpu on reset */
326 if (unlikely(!apic_enabled(apic)))
329 orig_irr = apic_test_and_set_irr(vector, apic);
330 if (orig_irr && trig_mode) {
331 apic_debug("level trig mode repeatedly for vector %d",
337 apic_debug("level trig mode for vector %d", vector);
338 apic_set_vector(vector, apic->regs + APIC_TMR);
340 apic_clear_vector(vector, apic->regs + APIC_TMR);
344 result = (orig_irr == 0);
348 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
352 printk(KERN_DEBUG "Ignoring guest SMI\n");
356 kvm_inject_nmi(vcpu);
361 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
363 "INIT on a runnable vcpu %d\n",
365 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
368 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
373 case APIC_DM_STARTUP:
374 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
375 vcpu->vcpu_id, vector);
376 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
377 vcpu->arch.sipi_vector = vector;
378 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
385 * Should only be called by kvm_apic_local_deliver() with LVT0,
386 * before NMI watchdog was enabled. Already handled by
387 * kvm_apic_accept_pic_intr().
392 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
399 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
400 unsigned long bitmap)
404 struct kvm_lapic *apic = NULL;
406 last = kvm->arch.round_robin_prev_vcpu;
410 if (++next == KVM_MAX_VCPUS)
412 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
414 apic = kvm->vcpus[next]->arch.apic;
415 if (apic && apic_enabled(apic))
418 } while (next != last);
419 kvm->arch.round_robin_prev_vcpu = next;
422 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
427 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
428 unsigned long bitmap)
430 struct kvm_lapic *apic;
432 apic = kvm_apic_round_robin(kvm, vector, bitmap);
438 static void apic_set_eoi(struct kvm_lapic *apic)
440 int vector = apic_find_highest_isr(apic);
443 * Not every write EOI will has corresponding ISR,
444 * one example is when Kernel check timer on setup_IO_APIC
449 apic_clear_vector(vector, apic->regs + APIC_ISR);
450 apic_update_ppr(apic);
452 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
453 trigger_mode = IOAPIC_LEVEL_TRIG;
455 trigger_mode = IOAPIC_EDGE_TRIG;
456 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
459 static void apic_send_ipi(struct kvm_lapic *apic)
461 u32 icr_low = apic_get_reg(apic, APIC_ICR);
462 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
464 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
465 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
466 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
467 unsigned int level = icr_low & APIC_INT_ASSERT;
468 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
469 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
470 unsigned int vector = icr_low & APIC_VECTOR_MASK;
472 struct kvm_vcpu *target;
473 struct kvm_vcpu *vcpu;
474 unsigned long lpr_map = 0;
477 apic_debug("icr_high 0x%x, icr_low 0x%x, "
478 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
479 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
480 icr_high, icr_low, short_hand, dest,
481 trig_mode, level, dest_mode, delivery_mode, vector);
483 for (i = 0; i < KVM_MAX_VCPUS; i++) {
484 vcpu = apic->vcpu->kvm->vcpus[i];
488 if (vcpu->arch.apic &&
489 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
490 if (delivery_mode == APIC_DM_LOWEST)
491 set_bit(vcpu->vcpu_id, &lpr_map);
493 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
494 vector, level, trig_mode);
498 if (delivery_mode == APIC_DM_LOWEST) {
499 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
501 __apic_accept_irq(target->arch.apic, delivery_mode,
502 vector, level, trig_mode);
506 static u32 apic_get_tmcct(struct kvm_lapic *apic)
512 ASSERT(apic != NULL);
514 now = apic->timer.dev.base->get_time();
515 tmcct = apic_get_reg(apic, APIC_TMICT);
517 /* if initial count is 0, current count should also be 0 */
521 if (unlikely(ktime_to_ns(now) <=
522 ktime_to_ns(apic->timer.last_update))) {
524 passed = ktime_add(( {
527 (apic->timer.last_update).tv64}; }
529 apic_debug("time elapsed\n");
531 passed = ktime_sub(now, apic->timer.last_update);
533 counter_passed = div64_u64(ktime_to_ns(passed),
534 (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
536 if (counter_passed > tmcct) {
537 if (unlikely(!apic_lvtt_period(apic))) {
538 /* one-shot timers stick at 0 until reset */
542 * periodic timers reset to APIC_TMICT when they
543 * hit 0. The while loop simulates this happening N
544 * times. (counter_passed %= tmcct) would also work,
545 * but might be slower or not work on 32-bit??
547 while (counter_passed > tmcct)
548 counter_passed -= tmcct;
549 tmcct -= counter_passed;
552 tmcct -= counter_passed;
558 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
560 struct kvm_vcpu *vcpu = apic->vcpu;
561 struct kvm_run *run = vcpu->run;
563 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
564 run->tpr_access.rip = kvm_rip_read(vcpu);
565 run->tpr_access.is_write = write;
568 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
570 if (apic->vcpu->arch.tpr_access_reporting)
571 __report_tpr_access(apic, write);
574 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
578 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
580 if (offset >= LAPIC_MMIO_LENGTH)
585 printk(KERN_WARNING "Access APIC ARBPRI register "
586 "which is for P6\n");
589 case APIC_TMCCT: /* Timer CCR */
590 val = apic_get_tmcct(apic);
594 report_tpr_access(apic, false);
597 apic_update_ppr(apic);
598 val = apic_get_reg(apic, offset);
605 static void apic_mmio_read(struct kvm_io_device *this,
606 gpa_t address, int len, void *data)
608 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
609 unsigned int offset = address - apic->base_address;
610 unsigned char alignment = offset & 0xf;
613 if ((alignment + len) > 4) {
614 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
615 (unsigned long)address, len);
618 result = __apic_read(apic, offset & ~0xf);
624 memcpy(data, (char *)&result + alignment, len);
627 printk(KERN_ERR "Local APIC read with len = %x, "
628 "should be 1,2, or 4 instead\n", len);
633 static void update_divide_count(struct kvm_lapic *apic)
635 u32 tmp1, tmp2, tdcr;
637 tdcr = apic_get_reg(apic, APIC_TDCR);
639 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
640 apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
642 apic_debug("timer divide count is 0x%x\n",
643 apic->timer.divide_count);
646 static void start_apic_timer(struct kvm_lapic *apic)
648 ktime_t now = apic->timer.dev.base->get_time();
650 apic->timer.last_update = now;
652 apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
653 APIC_BUS_CYCLE_NS * apic->timer.divide_count;
654 atomic_set(&apic->timer.pending, 0);
656 if (!apic->timer.period)
659 hrtimer_start(&apic->timer.dev,
660 ktime_add_ns(now, apic->timer.period),
663 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
665 "timer initial count 0x%x, period %lldns, "
666 "expire @ 0x%016" PRIx64 ".\n", __func__,
667 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
668 apic_get_reg(apic, APIC_TMICT),
670 ktime_to_ns(ktime_add_ns(now,
671 apic->timer.period)));
674 static void apic_mmio_write(struct kvm_io_device *this,
675 gpa_t address, int len, const void *data)
677 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
678 unsigned int offset = address - apic->base_address;
679 unsigned char alignment = offset & 0xf;
683 * APIC register must be aligned on 128-bits boundary.
684 * 32/64/128 bits registers must be accessed thru 32 bits.
687 if (len != 4 || alignment) {
688 /* Don't shout loud, $infamous_os would cause only noise. */
689 apic_debug("apic write: bad size=%d %lx\n",
696 /* too common printing */
697 if (offset != APIC_EOI)
698 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
699 "0x%x\n", __func__, offset, len, val);
703 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
706 case APIC_ID: /* Local APIC ID */
707 apic_set_reg(apic, APIC_ID, val);
711 report_tpr_access(apic, true);
712 apic_set_tpr(apic, val & 0xff);
720 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
724 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
728 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
729 if (!(val & APIC_SPIV_APIC_ENABLED)) {
733 for (i = 0; i < APIC_LVT_NUM; i++) {
734 lvt_val = apic_get_reg(apic,
735 APIC_LVTT + 0x10 * i);
736 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
737 lvt_val | APIC_LVT_MASKED);
739 atomic_set(&apic->timer.pending, 0);
745 /* No delay here, so we always clear the pending bit */
746 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
751 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
755 if (val == APIC_DM_NMI)
756 apic_debug("Receive NMI setting on APIC_LVT0 "
757 "for cpu %d\n", apic->vcpu->vcpu_id);
763 /* TODO: Check vector */
764 if (!apic_sw_enabled(apic))
765 val |= APIC_LVT_MASKED;
767 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
768 apic_set_reg(apic, offset, val);
773 hrtimer_cancel(&apic->timer.dev);
774 apic_set_reg(apic, APIC_TMICT, val);
775 start_apic_timer(apic);
780 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
781 apic_set_reg(apic, APIC_TDCR, val);
782 update_divide_count(apic);
786 apic_debug("Local APIC Write to read-only register %x\n",
793 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
796 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
800 if (apic_hw_enabled(apic) &&
801 (addr >= apic->base_address) &&
802 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
808 void kvm_free_lapic(struct kvm_vcpu *vcpu)
810 if (!vcpu->arch.apic)
813 hrtimer_cancel(&vcpu->arch.apic->timer.dev);
815 if (vcpu->arch.apic->regs_page)
816 __free_page(vcpu->arch.apic->regs_page);
818 kfree(vcpu->arch.apic);
822 *----------------------------------------------------------------------
824 *----------------------------------------------------------------------
827 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
829 struct kvm_lapic *apic = vcpu->arch.apic;
833 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
834 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
836 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
838 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
840 struct kvm_lapic *apic = vcpu->arch.apic;
845 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
847 return (tpr & 0xf0) >> 4;
849 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
851 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
853 struct kvm_lapic *apic = vcpu->arch.apic;
856 value |= MSR_IA32_APICBASE_BSP;
857 vcpu->arch.apic_base = value;
860 if (apic->vcpu->vcpu_id)
861 value &= ~MSR_IA32_APICBASE_BSP;
863 vcpu->arch.apic_base = value;
864 apic->base_address = apic->vcpu->arch.apic_base &
865 MSR_IA32_APICBASE_BASE;
867 /* with FSB delivery interrupt, we can restart APIC functionality */
868 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
869 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
873 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
875 return vcpu->arch.apic_base;
877 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
879 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
881 struct kvm_lapic *apic;
884 apic_debug("%s\n", __func__);
887 apic = vcpu->arch.apic;
888 ASSERT(apic != NULL);
890 /* Stop the timer in case it's a reset to an active apic */
891 hrtimer_cancel(&apic->timer.dev);
893 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
894 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
896 for (i = 0; i < APIC_LVT_NUM; i++)
897 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
898 apic_set_reg(apic, APIC_LVT0,
899 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
901 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
902 apic_set_reg(apic, APIC_SPIV, 0xff);
903 apic_set_reg(apic, APIC_TASKPRI, 0);
904 apic_set_reg(apic, APIC_LDR, 0);
905 apic_set_reg(apic, APIC_ESR, 0);
906 apic_set_reg(apic, APIC_ICR, 0);
907 apic_set_reg(apic, APIC_ICR2, 0);
908 apic_set_reg(apic, APIC_TDCR, 0);
909 apic_set_reg(apic, APIC_TMICT, 0);
910 for (i = 0; i < 8; i++) {
911 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
912 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
913 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
915 update_divide_count(apic);
916 atomic_set(&apic->timer.pending, 0);
917 if (vcpu->vcpu_id == 0)
918 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
919 apic_update_ppr(apic);
921 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
922 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
923 vcpu, kvm_apic_id(apic),
924 vcpu->arch.apic_base, apic->base_address);
926 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
928 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
930 struct kvm_lapic *apic = vcpu->arch.apic;
935 ret = apic_enabled(apic);
939 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
942 *----------------------------------------------------------------------
944 *----------------------------------------------------------------------
947 /* TODO: make sure __apic_timer_fn runs in current pCPU */
948 static int __apic_timer_fn(struct kvm_lapic *apic)
951 wait_queue_head_t *q = &apic->vcpu->wq;
953 if(!atomic_inc_and_test(&apic->timer.pending))
954 set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests);
955 if (waitqueue_active(q))
956 wake_up_interruptible(q);
958 if (apic_lvtt_period(apic)) {
960 hrtimer_add_expires_ns(&apic->timer.dev, apic->timer.period);
965 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
967 struct kvm_lapic *lapic = vcpu->arch.apic;
969 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
970 return atomic_read(&lapic->timer.pending);
975 int kvm_apic_local_deliver(struct kvm_vcpu *vcpu, int lvt_type)
977 struct kvm_lapic *apic = vcpu->arch.apic;
978 int vector, mode, trig_mode;
981 if (apic && apic_enabled(apic)) {
982 reg = apic_get_reg(apic, lvt_type);
983 vector = reg & APIC_VECTOR_MASK;
984 mode = reg & APIC_MODE_MASK;
985 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
986 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
991 static inline int __inject_apic_timer_irq(struct kvm_lapic *apic)
993 return kvm_apic_local_deliver(apic->vcpu, APIC_LVTT);
996 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
998 struct kvm_lapic *apic;
999 int restart_timer = 0;
1001 apic = container_of(data, struct kvm_lapic, timer.dev);
1003 restart_timer = __apic_timer_fn(apic);
1006 return HRTIMER_RESTART;
1008 return HRTIMER_NORESTART;
1011 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1013 struct kvm_lapic *apic;
1015 ASSERT(vcpu != NULL);
1016 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1018 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1022 vcpu->arch.apic = apic;
1024 apic->regs_page = alloc_page(GFP_KERNEL);
1025 if (apic->regs_page == NULL) {
1026 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1028 goto nomem_free_apic;
1030 apic->regs = page_address(apic->regs_page);
1031 memset(apic->regs, 0, PAGE_SIZE);
1034 hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1035 apic->timer.dev.function = apic_timer_fn;
1036 apic->base_address = APIC_DEFAULT_PHYS_BASE;
1037 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1039 kvm_lapic_reset(vcpu);
1040 apic->dev.read = apic_mmio_read;
1041 apic->dev.write = apic_mmio_write;
1042 apic->dev.in_range = apic_mmio_range;
1043 apic->dev.private = apic;
1051 EXPORT_SYMBOL_GPL(kvm_create_lapic);
1053 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1055 struct kvm_lapic *apic = vcpu->arch.apic;
1058 if (!apic || !apic_enabled(apic))
1061 apic_update_ppr(apic);
1062 highest_irr = apic_find_highest_irr(apic);
1063 if ((highest_irr == -1) ||
1064 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1069 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1071 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1074 if (vcpu->vcpu_id == 0) {
1075 if (!apic_hw_enabled(vcpu->arch.apic))
1077 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1078 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1084 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1086 struct kvm_lapic *apic = vcpu->arch.apic;
1088 if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1089 atomic_read(&apic->timer.pending) > 0) {
1090 if (__inject_apic_timer_irq(apic))
1091 atomic_dec(&apic->timer.pending);
1095 void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1097 struct kvm_lapic *apic = vcpu->arch.apic;
1099 if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1100 apic->timer.last_update = ktime_add_ns(
1101 apic->timer.last_update,
1102 apic->timer.period);
1105 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1107 int vector = kvm_apic_has_interrupt(vcpu);
1108 struct kvm_lapic *apic = vcpu->arch.apic;
1113 apic_set_vector(vector, apic->regs + APIC_ISR);
1114 apic_update_ppr(apic);
1115 apic_clear_irr(vector, apic);
1119 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1121 struct kvm_lapic *apic = vcpu->arch.apic;
1123 apic->base_address = vcpu->arch.apic_base &
1124 MSR_IA32_APICBASE_BASE;
1125 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1126 apic_update_ppr(apic);
1127 hrtimer_cancel(&apic->timer.dev);
1128 update_divide_count(apic);
1129 start_apic_timer(apic);
1132 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1134 struct kvm_lapic *apic = vcpu->arch.apic;
1135 struct hrtimer *timer;
1140 timer = &apic->timer.dev;
1141 if (hrtimer_cancel(timer))
1142 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1145 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1150 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1153 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1154 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1155 kunmap_atomic(vapic, KM_USER0);
1157 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1160 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1163 int max_irr, max_isr;
1164 struct kvm_lapic *apic;
1167 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1170 apic = vcpu->arch.apic;
1171 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1172 max_irr = apic_find_highest_irr(apic);
1175 max_isr = apic_find_highest_isr(apic);
1178 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1180 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1181 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1182 kunmap_atomic(vapic, KM_USER0);
1185 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1187 if (!irqchip_in_kernel(vcpu->kvm))
1190 vcpu->arch.apic->vapic_addr = vapic_addr;