arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 MODULE_AUTHOR("Qumranet");
  31 MODULE_LICENSE("GPL");
  32
  33 #define IOPM_ALLOC_ORDER 2
  34 #define MSRPM_ALLOC_ORDER 1
  35
  36 #define DB_VECTOR 1
  37 #define UD_VECTOR 6
  38 #define GP_VECTOR 13
  39
  40 #define DR7_GD_MASK (1 << 13)
  41 #define DR6_BD_MASK (1 << 13)
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_DEATURE_SVML (1 << 2)
  49
  50 static void kvm_reput_irq(struct vcpu_svm *svm);
  51
  52 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  53 {
  54         return container_of(vcpu, struct vcpu_svm, vcpu);
  55 }
  56
  57 unsigned long iopm_base;
  58 unsigned long msrpm_base;
  59
  60 struct kvm_ldttss_desc {
  61         u16 limit0;
  62         u16 base0;
  63         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  64         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  65         u32 base3;
  66         u32 zero1;
  67 } __attribute__((packed));
  68
  69 struct svm_cpu_data {
  70         int cpu;
  71
  72         u64 asid_generation;
  73         u32 max_asid;
  74         u32 next_asid;
  75         struct kvm_ldttss_desc *tss_desc;
  76
  77         struct page *save_area;
  78 };
  79
  80 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  81 static uint32_t svm_features;
  82
  83 struct svm_init_data {
  84         int cpu;
  85         int r;
  86 };
  87
  88 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  89
  90 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
  91 #define MSRS_RANGE_SIZE 2048
  92 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
  93
  94 #define MAX_INST_SIZE 15
  95
  96 static inline u32 svm_has(u32 feat)
  97 {
  98         return svm_features & feat;
  99 }
 100
 101 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 102 {
 103         int word_index = __ffs(vcpu->arch.irq_summary);
 104         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 105         int irq = word_index * BITS_PER_LONG + bit_index;
 106
 107         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 108         if (!vcpu->arch.irq_pending[word_index])
 109                 clear_bit(word_index, &vcpu->arch.irq_summary);
 110         return irq;
 111 }
 112
 113 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 114 {
 115         set_bit(irq, vcpu->arch.irq_pending);
 116         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 117 }
 118
 119 static inline void clgi(void)
 120 {
 121         asm volatile (SVM_CLGI);
 122 }
 123
 124 static inline void stgi(void)
 125 {
 126         asm volatile (SVM_STGI);
 127 }
 128
 129 static inline void invlpga(unsigned long addr, u32 asid)
 130 {
 131         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 132 }
 133
 134 static inline unsigned long kvm_read_cr2(void)
 135 {
 136         unsigned long cr2;
 137
 138         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 139         return cr2;
 140 }
 141
 142 static inline void kvm_write_cr2(unsigned long val)
 143 {
 144         asm volatile ("mov %0, %%cr2" :: "r" (val));
 145 }
 146
 147 static inline unsigned long read_dr6(void)
 148 {
 149         unsigned long dr6;
 150
 151         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 152         return dr6;
 153 }
 154
 155 static inline void write_dr6(unsigned long val)
 156 {
 157         asm volatile ("mov %0, %%dr6" :: "r" (val));
 158 }
 159
 160 static inline unsigned long read_dr7(void)
 161 {
 162         unsigned long dr7;
 163
 164         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 165         return dr7;
 166 }
 167
 168 static inline void write_dr7(unsigned long val)
 169 {
 170         asm volatile ("mov %0, %%dr7" :: "r" (val));
 171 }
 172
 173 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 174 {
 175         to_svm(vcpu)->asid_generation--;
 176 }
 177
 178 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 179 {
 180         force_new_asid(vcpu);
 181 }
 182
 183 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 184 {
 185         if (!(efer & EFER_LMA))
 186                 efer &= ~EFER_LME;
 187
 188         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 189         vcpu->arch.shadow_efer = efer;
 190 }
 191
 192 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 193                                 bool has_error_code, u32 error_code)
 194 {
 195         struct vcpu_svm *svm = to_svm(vcpu);
 196
 197         svm->vmcb->control.event_inj = nr
 198                 | SVM_EVTINJ_VALID
 199                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 200                 | SVM_EVTINJ_TYPE_EXEPT;
 201         svm->vmcb->control.event_inj_err = error_code;
 202 }
 203
 204 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 205 {
 206         struct vcpu_svm *svm = to_svm(vcpu);
 207
 208         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 209 }
 210
 211 static int is_external_interrupt(u32 info)
 212 {
 213         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 214         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 215 }
 216
 217 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 218 {
 219         struct vcpu_svm *svm = to_svm(vcpu);
 220
 221         if (!svm->next_rip) {
 222                 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
 223                 return;
 224         }
 225         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 226                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 227                        __FUNCTION__,
 228                        svm->vmcb->save.rip,
 229                        svm->next_rip);
 230
 231         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 232         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 233
 234         vcpu->arch.interrupt_window_open = 1;
 235 }
 236
 237 static int has_svm(void)
 238 {
 239         uint32_t eax, ebx, ecx, edx;
 240
 241         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 242                 printk(KERN_INFO "has_svm: not amd\n");
 243                 return 0;
 244         }
 245
 246         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 247         if (eax < SVM_CPUID_FUNC) {
 248                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 249                 return 0;
 250         }
 251
 252         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 253         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 254                 printk(KERN_DEBUG "has_svm: svm not available\n");
 255                 return 0;
 256         }
 257         return 1;
 258 }
 259
 260 static void svm_hardware_disable(void *garbage)
 261 {
 262         struct svm_cpu_data *svm_data
 263                 = per_cpu(svm_data, raw_smp_processor_id());
 264
 265         if (svm_data) {
 266                 uint64_t efer;
 267
 268                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 269                 rdmsrl(MSR_EFER, efer);
 270                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 271                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 272                 __free_page(svm_data->save_area);
 273                 kfree(svm_data);
 274         }
 275 }
 276
 277 static void svm_hardware_enable(void *garbage)
 278 {
 279
 280         struct svm_cpu_data *svm_data;
 281         uint64_t efer;
 282 #ifdef CONFIG_X86_64
 283         struct desc_ptr gdt_descr;
 284 #else
 285         struct desc_ptr gdt_descr;
 286 #endif
 287         struct desc_struct *gdt;
 288         int me = raw_smp_processor_id();
 289
 290         if (!has_svm()) {
 291                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 292                 return;
 293         }
 294         svm_data = per_cpu(svm_data, me);
 295
 296         if (!svm_data) {
 297                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 298                        me);
 299                 return;
 300         }
 301
 302         svm_data->asid_generation = 1;
 303         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 304         svm_data->next_asid = svm_data->max_asid + 1;
 305         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 306
 307         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 308         gdt = (struct desc_struct *)gdt_descr.address;
 309         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 310
 311         rdmsrl(MSR_EFER, efer);
 312         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 313
 314         wrmsrl(MSR_VM_HSAVE_PA,
 315                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 316 }
 317
 318 static int svm_cpu_init(int cpu)
 319 {
 320         struct svm_cpu_data *svm_data;
 321         int r;
 322
 323         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 324         if (!svm_data)
 325                 return -ENOMEM;
 326         svm_data->cpu = cpu;
 327         svm_data->save_area = alloc_page(GFP_KERNEL);
 328         r = -ENOMEM;
 329         if (!svm_data->save_area)
 330                 goto err_1;
 331
 332         per_cpu(svm_data, cpu) = svm_data;
 333
 334         return 0;
 335
 336 err_1:
 337         kfree(svm_data);
 338         return r;
 339
 340 }
 341
 342 static void set_msr_interception(u32 *msrpm, unsigned msr,
 343                                  int read, int write)
 344 {
 345         int i;
 346
 347         for (i = 0; i < NUM_MSR_MAPS; i++) {
 348                 if (msr >= msrpm_ranges[i] &&
 349                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 350                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 351                                           msrpm_ranges[i]) * 2;
 352
 353                         u32 *base = msrpm + (msr_offset / 32);
 354                         u32 msr_shift = msr_offset % 32;
 355                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 356                         *base = (*base & ~(0x3 << msr_shift)) |
 357                                 (mask << msr_shift);
 358                         return;
 359                 }
 360         }
 361         BUG();
 362 }
 363
 364 static __init int svm_hardware_setup(void)
 365 {
 366         int cpu;
 367         struct page *iopm_pages;
 368         struct page *msrpm_pages;
 369         void *iopm_va, *msrpm_va;
 370         int r;
 371
 372         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 373
 374         if (!iopm_pages)
 375                 return -ENOMEM;
 376
 377         iopm_va = page_address(iopm_pages);
 378         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 379         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 380         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 381
 382
 383         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 384
 385         r = -ENOMEM;
 386         if (!msrpm_pages)
 387                 goto err_1;
 388
 389         msrpm_va = page_address(msrpm_pages);
 390         memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 391         msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
 392
 393 #ifdef CONFIG_X86_64
 394         set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
 395         set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
 396         set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
 397         set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
 398         set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
 399         set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
 400 #endif
 401         set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
 402         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
 403         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
 404         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
 405
 406         if (boot_cpu_has(X86_FEATURE_NX))
 407                 kvm_enable_efer_bits(EFER_NX);
 408
 409         for_each_online_cpu(cpu) {
 410                 r = svm_cpu_init(cpu);
 411                 if (r)
 412                         goto err_2;
 413         }
 414         return 0;
 415
 416 err_2:
 417         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 418         msrpm_base = 0;
 419 err_1:
 420         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 421         iopm_base = 0;
 422         return r;
 423 }
 424
 425 static __exit void svm_hardware_unsetup(void)
 426 {
 427         __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
 428         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 429         iopm_base = msrpm_base = 0;
 430 }
 431
 432 static void init_seg(struct vmcb_seg *seg)
 433 {
 434         seg->selector = 0;
 435         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 436                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 437         seg->limit = 0xffff;
 438         seg->base = 0;
 439 }
 440
 441 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 442 {
 443         seg->selector = 0;
 444         seg->attrib = SVM_SELECTOR_P_MASK | type;
 445         seg->limit = 0xffff;
 446         seg->base = 0;
 447 }
 448
 449 static void init_vmcb(struct vmcb *vmcb)
 450 {
 451         struct vmcb_control_area *control = &vmcb->control;
 452         struct vmcb_save_area *save = &vmcb->save;
 453
 454         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 455                                         INTERCEPT_CR3_MASK |
 456                                         INTERCEPT_CR4_MASK |
 457                                         INTERCEPT_CR8_MASK;
 458
 459         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 460                                         INTERCEPT_CR3_MASK |
 461                                         INTERCEPT_CR4_MASK |
 462                                         INTERCEPT_CR8_MASK;
 463
 464         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 465                                         INTERCEPT_DR1_MASK |
 466                                         INTERCEPT_DR2_MASK |
 467                                         INTERCEPT_DR3_MASK;
 468
 469         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 470                                         INTERCEPT_DR1_MASK |
 471                                         INTERCEPT_DR2_MASK |
 472                                         INTERCEPT_DR3_MASK |
 473                                         INTERCEPT_DR5_MASK |
 474                                         INTERCEPT_DR7_MASK;
 475
 476         control->intercept_exceptions = (1 << PF_VECTOR) |
 477                                         (1 << UD_VECTOR);
 478
 479
 480         control->intercept =    (1ULL << INTERCEPT_INTR) |
 481                                 (1ULL << INTERCEPT_NMI) |
 482                                 (1ULL << INTERCEPT_SMI) |
 483                 /*
 484                  * selective cr0 intercept bug?
 485                  *      0:   0f 22 d8                mov    %eax,%cr3
 486                  *      3:   0f 20 c0                mov    %cr0,%eax
 487                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 488                  *      b:   0f 22 c0                mov    %eax,%cr0
 489                  * set cr3 ->interception
 490                  * get cr0 ->interception
 491                  * set cr0 -> no interception
 492                  */
 493                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 494                                 (1ULL << INTERCEPT_CPUID) |
 495                                 (1ULL << INTERCEPT_INVD) |
 496                                 (1ULL << INTERCEPT_HLT) |
 497                                 (1ULL << INTERCEPT_INVLPGA) |
 498                                 (1ULL << INTERCEPT_IOIO_PROT) |
 499                                 (1ULL << INTERCEPT_MSR_PROT) |
 500                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 501                                 (1ULL << INTERCEPT_SHUTDOWN) |
 502                                 (1ULL << INTERCEPT_VMRUN) |
 503                                 (1ULL << INTERCEPT_VMMCALL) |
 504                                 (1ULL << INTERCEPT_VMLOAD) |
 505                                 (1ULL << INTERCEPT_VMSAVE) |
 506                                 (1ULL << INTERCEPT_STGI) |
 507                                 (1ULL << INTERCEPT_CLGI) |
 508                                 (1ULL << INTERCEPT_SKINIT) |
 509                                 (1ULL << INTERCEPT_WBINVD) |
 510                                 (1ULL << INTERCEPT_MONITOR) |
 511                                 (1ULL << INTERCEPT_MWAIT);
 512
 513         control->iopm_base_pa = iopm_base;
 514         control->msrpm_base_pa = msrpm_base;
 515         control->tsc_offset = 0;
 516         control->int_ctl = V_INTR_MASKING_MASK;
 517
 518         init_seg(&save->es);
 519         init_seg(&save->ss);
 520         init_seg(&save->ds);
 521         init_seg(&save->fs);
 522         init_seg(&save->gs);
 523
 524         save->cs.selector = 0xf000;
 525         /* Executable/Readable Code Segment */
 526         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 527                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 528         save->cs.limit = 0xffff;
 529         /*
 530          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 531          * be consistent with it.
 532          *
 533          * Replace when we have real mode working for vmx.
 534          */
 535         save->cs.base = 0xf0000;
 536
 537         save->gdtr.limit = 0xffff;
 538         save->idtr.limit = 0xffff;
 539
 540         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 541         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 542
 543         save->efer = MSR_EFER_SVME_MASK;
 544         save->dr6 = 0xffff0ff0;
 545         save->dr7 = 0x400;
 546         save->rflags = 2;
 547         save->rip = 0x0000fff0;
 548
 549         /*
 550          * cr0 val on cpu init should be 0x60000010, we enable cpu
 551          * cache by default. the orderly way is to enable cache in bios.
 552          */
 553         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 554         save->cr4 = X86_CR4_PAE;
 555         /* rdx = ?? */
 556 }
 557
 558 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 559 {
 560         struct vcpu_svm *svm = to_svm(vcpu);
 561
 562         init_vmcb(svm->vmcb);
 563
 564         if (vcpu->vcpu_id != 0) {
 565                 svm->vmcb->save.rip = 0;
 566                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 567                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 568         }
 569
 570         return 0;
 571 }
 572
 573 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 574 {
 575         struct vcpu_svm *svm;
 576         struct page *page;
 577         int err;
 578
 579         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 580         if (!svm) {
 581                 err = -ENOMEM;
 582                 goto out;
 583         }
 584
 585         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 586         if (err)
 587                 goto free_svm;
 588
 589         page = alloc_page(GFP_KERNEL);
 590         if (!page) {
 591                 err = -ENOMEM;
 592                 goto uninit;
 593         }
 594
 595         svm->vmcb = page_address(page);
 596         clear_page(svm->vmcb);
 597         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 598         svm->asid_generation = 0;
 599         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 600         init_vmcb(svm->vmcb);
 601
 602         fx_init(&svm->vcpu);
 603         svm->vcpu.fpu_active = 1;
 604         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 605         if (svm->vcpu.vcpu_id == 0)
 606                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 607
 608         return &svm->vcpu;
 609
 610 uninit:
 611         kvm_vcpu_uninit(&svm->vcpu);
 612 free_svm:
 613         kmem_cache_free(kvm_vcpu_cache, svm);
 614 out:
 615         return ERR_PTR(err);
 616 }
 617
 618 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 619 {
 620         struct vcpu_svm *svm = to_svm(vcpu);
 621
 622         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 623         kvm_vcpu_uninit(vcpu);
 624         kmem_cache_free(kvm_vcpu_cache, svm);
 625 }
 626
 627 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 628 {
 629         struct vcpu_svm *svm = to_svm(vcpu);
 630         int i;
 631
 632         if (unlikely(cpu != vcpu->cpu)) {
 633                 u64 tsc_this, delta;
 634
 635                 /*
 636                  * Make sure that the guest sees a monotonically
 637                  * increasing TSC.
 638                  */
 639                 rdtscll(tsc_this);
 640                 delta = vcpu->arch.host_tsc - tsc_this;
 641                 svm->vmcb->control.tsc_offset += delta;
 642                 vcpu->cpu = cpu;
 643                 kvm_migrate_apic_timer(vcpu);
 644         }
 645
 646         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 647                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 648 }
 649
 650 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 651 {
 652         struct vcpu_svm *svm = to_svm(vcpu);
 653         int i;
 654
 655         ++vcpu->stat.host_state_reload;
 656         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 657                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 658
 659         rdtscll(vcpu->arch.host_tsc);
 660 }
 661
 662 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 663 {
 664 }
 665
 666 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 667 {
 668         struct vcpu_svm *svm = to_svm(vcpu);
 669
 670         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 671         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 672         vcpu->arch.rip = svm->vmcb->save.rip;
 673 }
 674
 675 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 676 {
 677         struct vcpu_svm *svm = to_svm(vcpu);
 678         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 679         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 680         svm->vmcb->save.rip = vcpu->arch.rip;
 681 }
 682
 683 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 684 {
 685         return to_svm(vcpu)->vmcb->save.rflags;
 686 }
 687
 688 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 689 {
 690         to_svm(vcpu)->vmcb->save.rflags = rflags;
 691 }
 692
 693 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 694 {
 695         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 696
 697         switch (seg) {
 698         case VCPU_SREG_CS: return &save->cs;
 699         case VCPU_SREG_DS: return &save->ds;
 700         case VCPU_SREG_ES: return &save->es;
 701         case VCPU_SREG_FS: return &save->fs;
 702         case VCPU_SREG_GS: return &save->gs;
 703         case VCPU_SREG_SS: return &save->ss;
 704         case VCPU_SREG_TR: return &save->tr;
 705         case VCPU_SREG_LDTR: return &save->ldtr;
 706         }
 707         BUG();
 708         return NULL;
 709 }
 710
 711 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 712 {
 713         struct vmcb_seg *s = svm_seg(vcpu, seg);
 714
 715         return s->base;
 716 }
 717
 718 static void svm_get_segment(struct kvm_vcpu *vcpu,
 719                             struct kvm_segment *var, int seg)
 720 {
 721         struct vmcb_seg *s = svm_seg(vcpu, seg);
 722
 723         var->base = s->base;
 724         var->limit = s->limit;
 725         var->selector = s->selector;
 726         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 727         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 728         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 729         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 730         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 731         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 732         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 733         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 734         var->unusable = !var->present;
 735 }
 736
 737 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 738 {
 739         struct vcpu_svm *svm = to_svm(vcpu);
 740
 741         dt->limit = svm->vmcb->save.idtr.limit;
 742         dt->base = svm->vmcb->save.idtr.base;
 743 }
 744
 745 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 746 {
 747         struct vcpu_svm *svm = to_svm(vcpu);
 748
 749         svm->vmcb->save.idtr.limit = dt->limit;
 750         svm->vmcb->save.idtr.base = dt->base ;
 751 }
 752
 753 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 754 {
 755         struct vcpu_svm *svm = to_svm(vcpu);
 756
 757         dt->limit = svm->vmcb->save.gdtr.limit;
 758         dt->base = svm->vmcb->save.gdtr.base;
 759 }
 760
 761 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 762 {
 763         struct vcpu_svm *svm = to_svm(vcpu);
 764
 765         svm->vmcb->save.gdtr.limit = dt->limit;
 766         svm->vmcb->save.gdtr.base = dt->base ;
 767 }
 768
 769 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 770 {
 771 }
 772
 773 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 774 {
 775         struct vcpu_svm *svm = to_svm(vcpu);
 776
 777 #ifdef CONFIG_X86_64
 778         if (vcpu->arch.shadow_efer & EFER_LME) {
 779                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 780                         vcpu->arch.shadow_efer |= EFER_LMA;
 781                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 782                 }
 783
 784                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 785                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 786                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 787                 }
 788         }
 789 #endif
 790         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 791                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 792                 vcpu->fpu_active = 1;
 793         }
 794
 795         vcpu->arch.cr0 = cr0;
 796         cr0 |= X86_CR0_PG | X86_CR0_WP;
 797         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 798         if (!vcpu->fpu_active) {
 799                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 800                 cr0 |= X86_CR0_TS;
 801         }
 802         svm->vmcb->save.cr0 = cr0;
 803 }
 804
 805 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 806 {
 807        vcpu->arch.cr4 = cr4;
 808        to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
 809 }
 810
 811 static void svm_set_segment(struct kvm_vcpu *vcpu,
 812                             struct kvm_segment *var, int seg)
 813 {
 814         struct vcpu_svm *svm = to_svm(vcpu);
 815         struct vmcb_seg *s = svm_seg(vcpu, seg);
 816
 817         s->base = var->base;
 818         s->limit = var->limit;
 819         s->selector = var->selector;
 820         if (var->unusable)
 821                 s->attrib = 0;
 822         else {
 823                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 824                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 825                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 826                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 827                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 828                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 829                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 830                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 831         }
 832         if (seg == VCPU_SREG_CS)
 833                 svm->vmcb->save.cpl
 834                         = (svm->vmcb->save.cs.attrib
 835                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 836
 837 }
 838
 839 /* FIXME:
 840
 841         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 842         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 843
 844 */
 845
 846 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 847 {
 848         return -EOPNOTSUPP;
 849 }
 850
 851 static int svm_get_irq(struct kvm_vcpu *vcpu)
 852 {
 853         struct vcpu_svm *svm = to_svm(vcpu);
 854         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 855
 856         if (is_external_interrupt(exit_int_info))
 857                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 858         return -1;
 859 }
 860
 861 static void load_host_msrs(struct kvm_vcpu *vcpu)
 862 {
 863 #ifdef CONFIG_X86_64
 864         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 865 #endif
 866 }
 867
 868 static void save_host_msrs(struct kvm_vcpu *vcpu)
 869 {
 870 #ifdef CONFIG_X86_64
 871         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 872 #endif
 873 }
 874
 875 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 876 {
 877         if (svm_data->next_asid > svm_data->max_asid) {
 878                 ++svm_data->asid_generation;
 879                 svm_data->next_asid = 1;
 880                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 881         }
 882
 883         svm->vcpu.cpu = svm_data->cpu;
 884         svm->asid_generation = svm_data->asid_generation;
 885         svm->vmcb->control.asid = svm_data->next_asid++;
 886 }
 887
 888 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 889 {
 890         return to_svm(vcpu)->db_regs[dr];
 891 }
 892
 893 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 894                        int *exception)
 895 {
 896         struct vcpu_svm *svm = to_svm(vcpu);
 897
 898         *exception = 0;
 899
 900         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 901                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 902                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 903                 *exception = DB_VECTOR;
 904                 return;
 905         }
 906
 907         switch (dr) {
 908         case 0 ... 3:
 909                 svm->db_regs[dr] = value;
 910                 return;
 911         case 4 ... 5:
 912                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 913                         *exception = UD_VECTOR;
 914                         return;
 915                 }
 916         case 7: {
 917                 if (value & ~((1ULL << 32) - 1)) {
 918                         *exception = GP_VECTOR;
 919                         return;
 920                 }
 921                 svm->vmcb->save.dr7 = value;
 922                 return;
 923         }
 924         default:
 925                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 926                        __FUNCTION__, dr);
 927                 *exception = UD_VECTOR;
 928                 return;
 929         }
 930 }
 931
 932 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 933 {
 934         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 935         struct kvm *kvm = svm->vcpu.kvm;
 936         u64 fault_address;
 937         u32 error_code;
 938
 939         if (!irqchip_in_kernel(kvm) &&
 940                 is_external_interrupt(exit_int_info))
 941                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
 942
 943         fault_address  = svm->vmcb->control.exit_info_2;
 944         error_code = svm->vmcb->control.exit_info_1;
 945         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
 946 }
 947
 948 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 949 {
 950         int er;
 951
 952         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
 953         if (er != EMULATE_DONE)
 954                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
 955         return 1;
 956 }
 957
 958 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 959 {
 960         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 961         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
 962                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
 963         svm->vcpu.fpu_active = 1;
 964
 965         return 1;
 966 }
 967
 968 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 969 {
 970         /*
 971          * VMCB is undefined after a SHUTDOWN intercept
 972          * so reinitialize it.
 973          */
 974         clear_page(svm->vmcb);
 975         init_vmcb(svm->vmcb);
 976
 977         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
 978         return 0;
 979 }
 980
 981 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 982 {
 983         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
 984         int size, down, in, string, rep;
 985         unsigned port;
 986
 987         ++svm->vcpu.stat.io_exits;
 988
 989         svm->next_rip = svm->vmcb->control.exit_info_2;
 990
 991         string = (io_info & SVM_IOIO_STR_MASK) != 0;
 992
 993         if (string) {
 994                 if (emulate_instruction(&svm->vcpu,
 995                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
 996                         return 0;
 997                 return 1;
 998         }
 999
1000         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1001         port = io_info >> 16;
1002         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1003         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1004         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1005
1006         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1007 }
1008
1009 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1010 {
1011         return 1;
1012 }
1013
1014 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1015 {
1016         svm->next_rip = svm->vmcb->save.rip + 1;
1017         skip_emulated_instruction(&svm->vcpu);
1018         return kvm_emulate_halt(&svm->vcpu);
1019 }
1020
1021 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1022 {
1023         svm->next_rip = svm->vmcb->save.rip + 3;
1024         skip_emulated_instruction(&svm->vcpu);
1025         kvm_emulate_hypercall(&svm->vcpu);
1026         return 1;
1027 }
1028
1029 static int invalid_op_interception(struct vcpu_svm *svm,
1030                                    struct kvm_run *kvm_run)
1031 {
1032         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1033         return 1;
1034 }
1035
1036 static int task_switch_interception(struct vcpu_svm *svm,
1037                                     struct kvm_run *kvm_run)
1038 {
1039         pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1040         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1041         return 0;
1042 }
1043
1044 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1045 {
1046         svm->next_rip = svm->vmcb->save.rip + 2;
1047         kvm_emulate_cpuid(&svm->vcpu);
1048         return 1;
1049 }
1050
1051 static int emulate_on_interception(struct vcpu_svm *svm,
1052                                    struct kvm_run *kvm_run)
1053 {
1054         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1055                 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1056         return 1;
1057 }
1058
1059 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1060 {
1061         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1062         if (irqchip_in_kernel(svm->vcpu.kvm))
1063                 return 1;
1064         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1065         return 0;
1066 }
1067
1068 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1069 {
1070         struct vcpu_svm *svm = to_svm(vcpu);
1071
1072         switch (ecx) {
1073         case MSR_IA32_TIME_STAMP_COUNTER: {
1074                 u64 tsc;
1075
1076                 rdtscll(tsc);
1077                 *data = svm->vmcb->control.tsc_offset + tsc;
1078                 break;
1079         }
1080         case MSR_K6_STAR:
1081                 *data = svm->vmcb->save.star;
1082                 break;
1083 #ifdef CONFIG_X86_64
1084         case MSR_LSTAR:
1085                 *data = svm->vmcb->save.lstar;
1086                 break;
1087         case MSR_CSTAR:
1088                 *data = svm->vmcb->save.cstar;
1089                 break;
1090         case MSR_KERNEL_GS_BASE:
1091                 *data = svm->vmcb->save.kernel_gs_base;
1092                 break;
1093         case MSR_SYSCALL_MASK:
1094                 *data = svm->vmcb->save.sfmask;
1095                 break;
1096 #endif
1097         case MSR_IA32_SYSENTER_CS:
1098                 *data = svm->vmcb->save.sysenter_cs;
1099                 break;
1100         case MSR_IA32_SYSENTER_EIP:
1101                 *data = svm->vmcb->save.sysenter_eip;
1102                 break;
1103         case MSR_IA32_SYSENTER_ESP:
1104                 *data = svm->vmcb->save.sysenter_esp;
1105                 break;
1106         /* Nobody will change the following 5 values in the VMCB so
1107            we can safely return them on rdmsr. They will always be 0
1108            until LBRV is implemented. */
1109         case MSR_IA32_DEBUGCTLMSR:
1110                 *data = svm->vmcb->save.dbgctl;
1111                 break;
1112         case MSR_IA32_LASTBRANCHFROMIP:
1113                 *data = svm->vmcb->save.br_from;
1114                 break;
1115         case MSR_IA32_LASTBRANCHTOIP:
1116                 *data = svm->vmcb->save.br_to;
1117                 break;
1118         case MSR_IA32_LASTINTFROMIP:
1119                 *data = svm->vmcb->save.last_excp_from;
1120                 break;
1121         case MSR_IA32_LASTINTTOIP:
1122                 *data = svm->vmcb->save.last_excp_to;
1123                 break;
1124         default:
1125                 return kvm_get_msr_common(vcpu, ecx, data);
1126         }
1127         return 0;
1128 }
1129
1130 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1131 {
1132         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1133         u64 data;
1134
1135         if (svm_get_msr(&svm->vcpu, ecx, &data))
1136                 kvm_inject_gp(&svm->vcpu, 0);
1137         else {
1138                 svm->vmcb->save.rax = data & 0xffffffff;
1139                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1140                 svm->next_rip = svm->vmcb->save.rip + 2;
1141                 skip_emulated_instruction(&svm->vcpu);
1142         }
1143         return 1;
1144 }
1145
1146 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1147 {
1148         struct vcpu_svm *svm = to_svm(vcpu);
1149
1150         switch (ecx) {
1151         case MSR_IA32_TIME_STAMP_COUNTER: {
1152                 u64 tsc;
1153
1154                 rdtscll(tsc);
1155                 svm->vmcb->control.tsc_offset = data - tsc;
1156                 break;
1157         }
1158         case MSR_K6_STAR:
1159                 svm->vmcb->save.star = data;
1160                 break;
1161 #ifdef CONFIG_X86_64
1162         case MSR_LSTAR:
1163                 svm->vmcb->save.lstar = data;
1164                 break;
1165         case MSR_CSTAR:
1166                 svm->vmcb->save.cstar = data;
1167                 break;
1168         case MSR_KERNEL_GS_BASE:
1169                 svm->vmcb->save.kernel_gs_base = data;
1170                 break;
1171         case MSR_SYSCALL_MASK:
1172                 svm->vmcb->save.sfmask = data;
1173                 break;
1174 #endif
1175         case MSR_IA32_SYSENTER_CS:
1176                 svm->vmcb->save.sysenter_cs = data;
1177                 break;
1178         case MSR_IA32_SYSENTER_EIP:
1179                 svm->vmcb->save.sysenter_eip = data;
1180                 break;
1181         case MSR_IA32_SYSENTER_ESP:
1182                 svm->vmcb->save.sysenter_esp = data;
1183                 break;
1184         case MSR_IA32_DEBUGCTLMSR:
1185                 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1186                                 __FUNCTION__, data);
1187                 break;
1188         case MSR_K7_EVNTSEL0:
1189         case MSR_K7_EVNTSEL1:
1190         case MSR_K7_EVNTSEL2:
1191         case MSR_K7_EVNTSEL3:
1192                 /*
1193                  * only support writing 0 to the performance counters for now
1194                  * to make Windows happy. Should be replaced by a real
1195                  * performance counter emulation later.
1196                  */
1197                 if (data != 0)
1198                         goto unhandled;
1199                 break;
1200         default:
1201         unhandled:
1202                 return kvm_set_msr_common(vcpu, ecx, data);
1203         }
1204         return 0;
1205 }
1206
1207 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1208 {
1209         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1210         u64 data = (svm->vmcb->save.rax & -1u)
1211                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1212         svm->next_rip = svm->vmcb->save.rip + 2;
1213         if (svm_set_msr(&svm->vcpu, ecx, data))
1214                 kvm_inject_gp(&svm->vcpu, 0);
1215         else
1216                 skip_emulated_instruction(&svm->vcpu);
1217         return 1;
1218 }
1219
1220 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1221 {
1222         if (svm->vmcb->control.exit_info_1)
1223                 return wrmsr_interception(svm, kvm_run);
1224         else
1225                 return rdmsr_interception(svm, kvm_run);
1226 }
1227
1228 static int interrupt_window_interception(struct vcpu_svm *svm,
1229                                    struct kvm_run *kvm_run)
1230 {
1231         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1232         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1233         /*
1234          * If the user space waits to inject interrupts, exit as soon as
1235          * possible
1236          */
1237         if (kvm_run->request_interrupt_window &&
1238             !svm->vcpu.arch.irq_summary) {
1239                 ++svm->vcpu.stat.irq_window_exits;
1240                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1241                 return 0;
1242         }
1243
1244         return 1;
1245 }
1246
1247 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1248                                       struct kvm_run *kvm_run) = {
1249         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1250         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1251         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1252         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1253         /* for now: */
1254         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1255         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1256         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1257         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1258         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1259         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1260         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1261         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1262         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1263         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1264         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1265         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1266         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1267         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1268         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1269         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1270         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1271         [SVM_EXIT_INTR]                         = nop_on_interception,
1272         [SVM_EXIT_NMI]                          = nop_on_interception,
1273         [SVM_EXIT_SMI]                          = nop_on_interception,
1274         [SVM_EXIT_INIT]                         = nop_on_interception,
1275         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1276         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1277         [SVM_EXIT_CPUID]                        = cpuid_interception,
1278         [SVM_EXIT_INVD]                         = emulate_on_interception,
1279         [SVM_EXIT_HLT]                          = halt_interception,
1280         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1281         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1282         [SVM_EXIT_IOIO]                         = io_interception,
1283         [SVM_EXIT_MSR]                          = msr_interception,
1284         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1285         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1286         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1287         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1288         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1289         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1290         [SVM_EXIT_STGI]                         = invalid_op_interception,
1291         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1292         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1293         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1294         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1295         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1296 };
1297
1298
1299 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1300 {
1301         struct vcpu_svm *svm = to_svm(vcpu);
1302         u32 exit_code = svm->vmcb->control.exit_code;
1303
1304         kvm_reput_irq(svm);
1305
1306         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1307                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1308                 kvm_run->fail_entry.hardware_entry_failure_reason
1309                         = svm->vmcb->control.exit_code;
1310                 return 0;
1311         }
1312
1313         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1314             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1315                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1316                        "exit_code 0x%x\n",
1317                        __FUNCTION__, svm->vmcb->control.exit_int_info,
1318                        exit_code);
1319
1320         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1321             || !svm_exit_handlers[exit_code]) {
1322                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1323                 kvm_run->hw.hardware_exit_reason = exit_code;
1324                 return 0;
1325         }
1326
1327         return svm_exit_handlers[exit_code](svm, kvm_run);
1328 }
1329
1330 static void reload_tss(struct kvm_vcpu *vcpu)
1331 {
1332         int cpu = raw_smp_processor_id();
1333
1334         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1335         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1336         load_TR_desc();
1337 }
1338
1339 static void pre_svm_run(struct vcpu_svm *svm)
1340 {
1341         int cpu = raw_smp_processor_id();
1342
1343         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1344
1345         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1346         if (svm->vcpu.cpu != cpu ||
1347             svm->asid_generation != svm_data->asid_generation)
1348                 new_asid(svm, svm_data);
1349 }
1350
1351
1352 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1353 {
1354         struct vmcb_control_area *control;
1355
1356         control = &svm->vmcb->control;
1357         control->int_vector = irq;
1358         control->int_ctl &= ~V_INTR_PRIO_MASK;
1359         control->int_ctl |= V_IRQ_MASK |
1360                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1361 }
1362
1363 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1364 {
1365         struct vcpu_svm *svm = to_svm(vcpu);
1366
1367         svm_inject_irq(svm, irq);
1368 }
1369
1370 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1371 {
1372         struct vcpu_svm *svm = to_svm(vcpu);
1373         struct vmcb *vmcb = svm->vmcb;
1374         int intr_vector = -1;
1375
1376         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1377             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1378                 intr_vector = vmcb->control.exit_int_info &
1379                               SVM_EVTINJ_VEC_MASK;
1380                 vmcb->control.exit_int_info = 0;
1381                 svm_inject_irq(svm, intr_vector);
1382                 return;
1383         }
1384
1385         if (vmcb->control.int_ctl & V_IRQ_MASK)
1386                 return;
1387
1388         if (!kvm_cpu_has_interrupt(vcpu))
1389                 return;
1390
1391         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1392             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1393             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1394                 /* unable to deliver irq, set pending irq */
1395                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1396                 svm_inject_irq(svm, 0x0);
1397                 return;
1398         }
1399         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1400         intr_vector = kvm_cpu_get_interrupt(vcpu);
1401         svm_inject_irq(svm, intr_vector);
1402         kvm_timer_intr_post(vcpu, intr_vector);
1403 }
1404
1405 static void kvm_reput_irq(struct vcpu_svm *svm)
1406 {
1407         struct vmcb_control_area *control = &svm->vmcb->control;
1408
1409         if ((control->int_ctl & V_IRQ_MASK)
1410             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1411                 control->int_ctl &= ~V_IRQ_MASK;
1412                 push_irq(&svm->vcpu, control->int_vector);
1413         }
1414
1415         svm->vcpu.arch.interrupt_window_open =
1416                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1417 }
1418
1419 static void svm_do_inject_vector(struct vcpu_svm *svm)
1420 {
1421         struct kvm_vcpu *vcpu = &svm->vcpu;
1422         int word_index = __ffs(vcpu->arch.irq_summary);
1423         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1424         int irq = word_index * BITS_PER_LONG + bit_index;
1425
1426         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1427         if (!vcpu->arch.irq_pending[word_index])
1428                 clear_bit(word_index, &vcpu->arch.irq_summary);
1429         svm_inject_irq(svm, irq);
1430 }
1431
1432 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1433                                        struct kvm_run *kvm_run)
1434 {
1435         struct vcpu_svm *svm = to_svm(vcpu);
1436         struct vmcb_control_area *control = &svm->vmcb->control;
1437
1438         svm->vcpu.arch.interrupt_window_open =
1439                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1440                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1441
1442         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1443                 /*
1444                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1445                  */
1446                 svm_do_inject_vector(svm);
1447
1448         /*
1449          * Interrupts blocked.  Wait for unblock.
1450          */
1451         if (!svm->vcpu.arch.interrupt_window_open &&
1452             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1453                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1454          else
1455                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1456 }
1457
1458 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1459 {
1460         return 0;
1461 }
1462
1463 static void save_db_regs(unsigned long *db_regs)
1464 {
1465         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1466         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1467         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1468         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1469 }
1470
1471 static void load_db_regs(unsigned long *db_regs)
1472 {
1473         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1474         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1475         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1476         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1477 }
1478
1479 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1480 {
1481         force_new_asid(vcpu);
1482 }
1483
1484 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1485 {
1486 }
1487
1488 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1489 {
1490         struct vcpu_svm *svm = to_svm(vcpu);
1491         u16 fs_selector;
1492         u16 gs_selector;
1493         u16 ldt_selector;
1494
1495         pre_svm_run(svm);
1496
1497         save_host_msrs(vcpu);
1498         fs_selector = read_fs();
1499         gs_selector = read_gs();
1500         ldt_selector = read_ldt();
1501         svm->host_cr2 = kvm_read_cr2();
1502         svm->host_dr6 = read_dr6();
1503         svm->host_dr7 = read_dr7();
1504         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1505
1506         if (svm->vmcb->save.dr7 & 0xff) {
1507                 write_dr7(0);
1508                 save_db_regs(svm->host_db_regs);
1509                 load_db_regs(svm->db_regs);
1510         }
1511
1512         clgi();
1513
1514         local_irq_enable();
1515
1516         asm volatile (
1517 #ifdef CONFIG_X86_64
1518                 "push %%rbp; \n\t"
1519 #else
1520                 "push %%ebp; \n\t"
1521 #endif
1522
1523 #ifdef CONFIG_X86_64
1524                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1525                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1526                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1527                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1528                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1529                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1530                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1531                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1532                 "mov %c[r10](%[svm]), %%r10 \n\t"
1533                 "mov %c[r11](%[svm]), %%r11 \n\t"
1534                 "mov %c[r12](%[svm]), %%r12 \n\t"
1535                 "mov %c[r13](%[svm]), %%r13 \n\t"
1536                 "mov %c[r14](%[svm]), %%r14 \n\t"
1537                 "mov %c[r15](%[svm]), %%r15 \n\t"
1538 #else
1539                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1540                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1541                 "mov %c[rdx](%[svm]), %%edx \n\t"
1542                 "mov %c[rsi](%[svm]), %%esi \n\t"
1543                 "mov %c[rdi](%[svm]), %%edi \n\t"
1544                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1545 #endif
1546
1547 #ifdef CONFIG_X86_64
1548                 /* Enter guest mode */
1549                 "push %%rax \n\t"
1550                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1551                 SVM_VMLOAD "\n\t"
1552                 SVM_VMRUN "\n\t"
1553                 SVM_VMSAVE "\n\t"
1554                 "pop %%rax \n\t"
1555 #else
1556                 /* Enter guest mode */
1557                 "push %%eax \n\t"
1558                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1559                 SVM_VMLOAD "\n\t"
1560                 SVM_VMRUN "\n\t"
1561                 SVM_VMSAVE "\n\t"
1562                 "pop %%eax \n\t"
1563 #endif
1564
1565                 /* Save guest registers, load host registers */
1566 #ifdef CONFIG_X86_64
1567                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1568                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1569                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1570                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1571                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1572                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1573                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1574                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1575                 "mov %%r10, %c[r10](%[svm]) \n\t"
1576                 "mov %%r11, %c[r11](%[svm]) \n\t"
1577                 "mov %%r12, %c[r12](%[svm]) \n\t"
1578                 "mov %%r13, %c[r13](%[svm]) \n\t"
1579                 "mov %%r14, %c[r14](%[svm]) \n\t"
1580                 "mov %%r15, %c[r15](%[svm]) \n\t"
1581
1582                 "pop  %%rbp; \n\t"
1583 #else
1584                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1585                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1586                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1587                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1588                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1589                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1590
1591                 "pop  %%ebp; \n\t"
1592 #endif
1593                 :
1594                 : [svm]"a"(svm),
1595                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1596                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1597                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1598                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1599                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1600                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1601                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1602 #ifdef CONFIG_X86_64
1603                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1604                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1605                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1606                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1607                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1608                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1609                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1610                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1611 #endif
1612                 : "cc", "memory"
1613 #ifdef CONFIG_X86_64
1614                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1615                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1616 #else
1617                 , "ebx", "ecx", "edx" , "esi", "edi"
1618 #endif
1619                 );
1620
1621         if ((svm->vmcb->save.dr7 & 0xff))
1622                 load_db_regs(svm->host_db_regs);
1623
1624         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1625
1626         write_dr6(svm->host_dr6);
1627         write_dr7(svm->host_dr7);
1628         kvm_write_cr2(svm->host_cr2);
1629
1630         load_fs(fs_selector);
1631         load_gs(gs_selector);
1632         load_ldt(ldt_selector);
1633         load_host_msrs(vcpu);
1634
1635         reload_tss(vcpu);
1636
1637         local_irq_disable();
1638
1639         stgi();
1640
1641         svm->next_rip = 0;
1642 }
1643
1644 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1645 {
1646         struct vcpu_svm *svm = to_svm(vcpu);
1647
1648         svm->vmcb->save.cr3 = root;
1649         force_new_asid(vcpu);
1650
1651         if (vcpu->fpu_active) {
1652                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1653                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1654                 vcpu->fpu_active = 0;
1655         }
1656 }
1657
1658 static int is_disabled(void)
1659 {
1660         u64 vm_cr;
1661
1662         rdmsrl(MSR_VM_CR, vm_cr);
1663         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1664                 return 1;
1665
1666         return 0;
1667 }
1668
1669 static void
1670 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1671 {
1672         /*
1673          * Patch in the VMMCALL instruction:
1674          */
1675         hypercall[0] = 0x0f;
1676         hypercall[1] = 0x01;
1677         hypercall[2] = 0xd9;
1678 }
1679
1680 static void svm_check_processor_compat(void *rtn)
1681 {
1682         *(int *)rtn = 0;
1683 }
1684
1685 static bool svm_cpu_has_accelerated_tpr(void)
1686 {
1687         return false;
1688 }
1689
1690 static struct kvm_x86_ops svm_x86_ops = {
1691         .cpu_has_kvm_support = has_svm,
1692         .disabled_by_bios = is_disabled,
1693         .hardware_setup = svm_hardware_setup,
1694         .hardware_unsetup = svm_hardware_unsetup,
1695         .check_processor_compatibility = svm_check_processor_compat,
1696         .hardware_enable = svm_hardware_enable,
1697         .hardware_disable = svm_hardware_disable,
1698         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1699
1700         .vcpu_create = svm_create_vcpu,
1701         .vcpu_free = svm_free_vcpu,
1702         .vcpu_reset = svm_vcpu_reset,
1703
1704         .prepare_guest_switch = svm_prepare_guest_switch,
1705         .vcpu_load = svm_vcpu_load,
1706         .vcpu_put = svm_vcpu_put,
1707         .vcpu_decache = svm_vcpu_decache,
1708
1709         .set_guest_debug = svm_guest_debug,
1710         .get_msr = svm_get_msr,
1711         .set_msr = svm_set_msr,
1712         .get_segment_base = svm_get_segment_base,
1713         .get_segment = svm_get_segment,
1714         .set_segment = svm_set_segment,
1715         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1716         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1717         .set_cr0 = svm_set_cr0,
1718         .set_cr3 = svm_set_cr3,
1719         .set_cr4 = svm_set_cr4,
1720         .set_efer = svm_set_efer,
1721         .get_idt = svm_get_idt,
1722         .set_idt = svm_set_idt,
1723         .get_gdt = svm_get_gdt,
1724         .set_gdt = svm_set_gdt,
1725         .get_dr = svm_get_dr,
1726         .set_dr = svm_set_dr,
1727         .cache_regs = svm_cache_regs,
1728         .decache_regs = svm_decache_regs,
1729         .get_rflags = svm_get_rflags,
1730         .set_rflags = svm_set_rflags,
1731
1732         .tlb_flush = svm_flush_tlb,
1733
1734         .run = svm_vcpu_run,
1735         .handle_exit = handle_exit,
1736         .skip_emulated_instruction = skip_emulated_instruction,
1737         .patch_hypercall = svm_patch_hypercall,
1738         .get_irq = svm_get_irq,
1739         .set_irq = svm_set_irq,
1740         .queue_exception = svm_queue_exception,
1741         .exception_injected = svm_exception_injected,
1742         .inject_pending_irq = svm_intr_assist,
1743         .inject_pending_vectors = do_interrupt_requests,
1744
1745         .set_tss_addr = svm_set_tss_addr,
1746 };
1747
1748 static int __init svm_init(void)
1749 {
1750         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1751                               THIS_MODULE);
1752 }
1753
1754 static void __exit svm_exit(void)
1755 {
1756         kvm_exit();
1757 }
1758
1759 module_init(svm_init)
1760 module_exit(svm_exit)