2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
38 static int bypass_guest_pf = 1;
39 module_param(bypass_guest_pf, bool, 0);
41 static int enable_vpid = 1;
42 module_param(enable_vpid, bool, 0);
44 static int flexpriority_enabled = 1;
45 module_param(flexpriority_enabled, bool, 0);
47 static int enable_ept = 1;
48 module_param(enable_ept, bool, 0);
58 struct list_head local_vcpus_link;
61 u32 idt_vectoring_info;
62 struct kvm_msr_entry *guest_msrs;
63 struct kvm_msr_entry *host_msrs;
68 int msr_offset_kernel_gs_base;
73 u16 fs_sel, gs_sel, ldt_sel;
74 int gs_ldt_reload_needed;
76 int guest_efer_loaded;
88 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
90 return container_of(vcpu, struct vcpu_vmx, vcpu);
93 static int init_rmode(struct kvm *kvm);
95 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
96 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
97 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
99 static struct page *vmx_io_bitmap_a;
100 static struct page *vmx_io_bitmap_b;
101 static struct page *vmx_msr_bitmap;
103 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
104 static DEFINE_SPINLOCK(vmx_vpid_lock);
106 static struct vmcs_config {
110 u32 pin_based_exec_ctrl;
111 u32 cpu_based_exec_ctrl;
112 u32 cpu_based_2nd_exec_ctrl;
117 struct vmx_capability {
122 #define VMX_SEGMENT_FIELD(seg) \
123 [VCPU_SREG_##seg] = { \
124 .selector = GUEST_##seg##_SELECTOR, \
125 .base = GUEST_##seg##_BASE, \
126 .limit = GUEST_##seg##_LIMIT, \
127 .ar_bytes = GUEST_##seg##_AR_BYTES, \
130 static struct kvm_vmx_segment_field {
135 } kvm_vmx_segment_fields[] = {
136 VMX_SEGMENT_FIELD(CS),
137 VMX_SEGMENT_FIELD(DS),
138 VMX_SEGMENT_FIELD(ES),
139 VMX_SEGMENT_FIELD(FS),
140 VMX_SEGMENT_FIELD(GS),
141 VMX_SEGMENT_FIELD(SS),
142 VMX_SEGMENT_FIELD(TR),
143 VMX_SEGMENT_FIELD(LDTR),
147 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
148 * away by decrementing the array size.
150 static const u32 vmx_msr_index[] = {
152 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
154 MSR_EFER, MSR_K6_STAR,
156 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
158 static void load_msrs(struct kvm_msr_entry *e, int n)
162 for (i = 0; i < n; ++i)
163 wrmsrl(e[i].index, e[i].data);
166 static void save_msrs(struct kvm_msr_entry *e, int n)
170 for (i = 0; i < n; ++i)
171 rdmsrl(e[i].index, e[i].data);
174 static inline int is_page_fault(u32 intr_info)
176 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
177 INTR_INFO_VALID_MASK)) ==
178 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
181 static inline int is_no_device(u32 intr_info)
183 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
184 INTR_INFO_VALID_MASK)) ==
185 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
188 static inline int is_invalid_opcode(u32 intr_info)
190 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
191 INTR_INFO_VALID_MASK)) ==
192 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
195 static inline int is_external_interrupt(u32 intr_info)
197 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
198 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
201 static inline int cpu_has_vmx_msr_bitmap(void)
203 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
206 static inline int cpu_has_vmx_tpr_shadow(void)
208 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
211 static inline int vm_need_tpr_shadow(struct kvm *kvm)
213 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
216 static inline int cpu_has_secondary_exec_ctrls(void)
218 return (vmcs_config.cpu_based_exec_ctrl &
219 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
222 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
224 return flexpriority_enabled
225 && (vmcs_config.cpu_based_2nd_exec_ctrl &
226 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
229 static inline int cpu_has_vmx_invept_individual_addr(void)
231 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
234 static inline int cpu_has_vmx_invept_context(void)
236 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
239 static inline int cpu_has_vmx_invept_global(void)
241 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
244 static inline int cpu_has_vmx_ept(void)
246 return (vmcs_config.cpu_based_2nd_exec_ctrl &
247 SECONDARY_EXEC_ENABLE_EPT);
250 static inline int vm_need_ept(void)
252 return (cpu_has_vmx_ept() && enable_ept);
255 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
257 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
258 (irqchip_in_kernel(kvm)));
261 static inline int cpu_has_vmx_vpid(void)
263 return (vmcs_config.cpu_based_2nd_exec_ctrl &
264 SECONDARY_EXEC_ENABLE_VPID);
267 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
271 for (i = 0; i < vmx->nmsrs; ++i)
272 if (vmx->guest_msrs[i].index == msr)
277 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
283 } operand = { vpid, 0, gva };
285 asm volatile (__ex(ASM_VMX_INVVPID)
286 /* CF==1 or ZF==1 --> rc = -1 */
288 : : "a"(&operand), "c"(ext) : "cc", "memory");
291 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
295 } operand = {eptp, gpa};
297 asm volatile (__ex(ASM_VMX_INVEPT)
298 /* CF==1 or ZF==1 --> rc = -1 */
299 "; ja 1f ; ud2 ; 1:\n"
300 : : "a" (&operand), "c" (ext) : "cc", "memory");
303 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
307 i = __find_msr_index(vmx, msr);
309 return &vmx->guest_msrs[i];
313 static void vmcs_clear(struct vmcs *vmcs)
315 u64 phys_addr = __pa(vmcs);
318 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
319 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
322 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
326 static void __vcpu_clear(void *arg)
328 struct vcpu_vmx *vmx = arg;
329 int cpu = raw_smp_processor_id();
331 if (vmx->vcpu.cpu == cpu)
332 vmcs_clear(vmx->vmcs);
333 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
334 per_cpu(current_vmcs, cpu) = NULL;
335 rdtscll(vmx->vcpu.arch.host_tsc);
336 list_del(&vmx->local_vcpus_link);
341 static void vcpu_clear(struct vcpu_vmx *vmx)
343 if (vmx->vcpu.cpu == -1)
345 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
348 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
353 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
356 static inline void ept_sync_global(void)
358 if (cpu_has_vmx_invept_global())
359 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
362 static inline void ept_sync_context(u64 eptp)
365 if (cpu_has_vmx_invept_context())
366 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
372 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
375 if (cpu_has_vmx_invept_individual_addr())
376 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
379 ept_sync_context(eptp);
383 static unsigned long vmcs_readl(unsigned long field)
387 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
388 : "=a"(value) : "d"(field) : "cc");
392 static u16 vmcs_read16(unsigned long field)
394 return vmcs_readl(field);
397 static u32 vmcs_read32(unsigned long field)
399 return vmcs_readl(field);
402 static u64 vmcs_read64(unsigned long field)
405 return vmcs_readl(field);
407 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
411 static noinline void vmwrite_error(unsigned long field, unsigned long value)
413 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
414 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
418 static void vmcs_writel(unsigned long field, unsigned long value)
422 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
423 : "=q"(error) : "a"(value), "d"(field) : "cc");
425 vmwrite_error(field, value);
428 static void vmcs_write16(unsigned long field, u16 value)
430 vmcs_writel(field, value);
433 static void vmcs_write32(unsigned long field, u32 value)
435 vmcs_writel(field, value);
438 static void vmcs_write64(unsigned long field, u64 value)
440 vmcs_writel(field, value);
441 #ifndef CONFIG_X86_64
443 vmcs_writel(field+1, value >> 32);
447 static void vmcs_clear_bits(unsigned long field, u32 mask)
449 vmcs_writel(field, vmcs_readl(field) & ~mask);
452 static void vmcs_set_bits(unsigned long field, u32 mask)
454 vmcs_writel(field, vmcs_readl(field) | mask);
457 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
461 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
462 if (!vcpu->fpu_active)
463 eb |= 1u << NM_VECTOR;
464 if (vcpu->guest_debug.enabled)
466 if (vcpu->arch.rmode.active)
469 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
470 vmcs_write32(EXCEPTION_BITMAP, eb);
473 static void reload_tss(void)
476 * VT restores TR but not its size. Useless.
478 struct descriptor_table gdt;
479 struct desc_struct *descs;
482 descs = (void *)gdt.base;
483 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
487 static void load_transition_efer(struct vcpu_vmx *vmx)
489 int efer_offset = vmx->msr_offset_efer;
490 u64 host_efer = vmx->host_msrs[efer_offset].data;
491 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
497 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
500 ignore_bits = EFER_NX | EFER_SCE;
502 ignore_bits |= EFER_LMA | EFER_LME;
503 /* SCE is meaningful only in long mode on Intel */
504 if (guest_efer & EFER_LMA)
505 ignore_bits &= ~(u64)EFER_SCE;
507 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
510 vmx->host_state.guest_efer_loaded = 1;
511 guest_efer &= ~ignore_bits;
512 guest_efer |= host_efer & ignore_bits;
513 wrmsrl(MSR_EFER, guest_efer);
514 vmx->vcpu.stat.efer_reload++;
517 static void reload_host_efer(struct vcpu_vmx *vmx)
519 if (vmx->host_state.guest_efer_loaded) {
520 vmx->host_state.guest_efer_loaded = 0;
521 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
525 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
527 struct vcpu_vmx *vmx = to_vmx(vcpu);
529 if (vmx->host_state.loaded)
532 vmx->host_state.loaded = 1;
534 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
535 * allow segment selectors with cpl > 0 or ti == 1.
537 vmx->host_state.ldt_sel = read_ldt();
538 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
539 vmx->host_state.fs_sel = read_fs();
540 if (!(vmx->host_state.fs_sel & 7)) {
541 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
542 vmx->host_state.fs_reload_needed = 0;
544 vmcs_write16(HOST_FS_SELECTOR, 0);
545 vmx->host_state.fs_reload_needed = 1;
547 vmx->host_state.gs_sel = read_gs();
548 if (!(vmx->host_state.gs_sel & 7))
549 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
551 vmcs_write16(HOST_GS_SELECTOR, 0);
552 vmx->host_state.gs_ldt_reload_needed = 1;
556 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
557 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
559 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
560 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
564 if (is_long_mode(&vmx->vcpu))
565 save_msrs(vmx->host_msrs +
566 vmx->msr_offset_kernel_gs_base, 1);
569 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
570 load_transition_efer(vmx);
573 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
577 if (!vmx->host_state.loaded)
580 ++vmx->vcpu.stat.host_state_reload;
581 vmx->host_state.loaded = 0;
582 if (vmx->host_state.fs_reload_needed)
583 load_fs(vmx->host_state.fs_sel);
584 if (vmx->host_state.gs_ldt_reload_needed) {
585 load_ldt(vmx->host_state.ldt_sel);
587 * If we have to reload gs, we must take care to
588 * preserve our gs base.
590 local_irq_save(flags);
591 load_gs(vmx->host_state.gs_sel);
593 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
595 local_irq_restore(flags);
598 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
599 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
600 reload_host_efer(vmx);
603 static void vmx_load_host_state(struct vcpu_vmx *vmx)
606 __vmx_load_host_state(vmx);
611 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
612 * vcpu mutex is already taken.
614 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
616 struct vcpu_vmx *vmx = to_vmx(vcpu);
617 u64 phys_addr = __pa(vmx->vmcs);
618 u64 tsc_this, delta, new_offset;
620 if (vcpu->cpu != cpu) {
622 kvm_migrate_timers(vcpu);
623 vpid_sync_vcpu_all(vmx);
625 list_add(&vmx->local_vcpus_link,
626 &per_cpu(vcpus_on_cpu, cpu));
630 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
633 per_cpu(current_vmcs, cpu) = vmx->vmcs;
634 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
635 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
638 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
639 vmx->vmcs, phys_addr);
642 if (vcpu->cpu != cpu) {
643 struct descriptor_table dt;
644 unsigned long sysenter_esp;
648 * Linux uses per-cpu TSS and GDT, so set these when switching
651 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
653 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
655 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
656 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
659 * Make sure the time stamp counter is monotonous.
662 if (tsc_this < vcpu->arch.host_tsc) {
663 delta = vcpu->arch.host_tsc - tsc_this;
664 new_offset = vmcs_read64(TSC_OFFSET) + delta;
665 vmcs_write64(TSC_OFFSET, new_offset);
670 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
672 __vmx_load_host_state(to_vmx(vcpu));
675 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
677 if (vcpu->fpu_active)
679 vcpu->fpu_active = 1;
680 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
681 if (vcpu->arch.cr0 & X86_CR0_TS)
682 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
683 update_exception_bitmap(vcpu);
686 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
688 if (!vcpu->fpu_active)
690 vcpu->fpu_active = 0;
691 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
692 update_exception_bitmap(vcpu);
695 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
697 vcpu_clear(to_vmx(vcpu));
700 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
702 return vmcs_readl(GUEST_RFLAGS);
705 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
707 if (vcpu->arch.rmode.active)
708 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
709 vmcs_writel(GUEST_RFLAGS, rflags);
712 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
715 u32 interruptibility;
717 rip = vmcs_readl(GUEST_RIP);
718 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
719 vmcs_writel(GUEST_RIP, rip);
722 * We emulated an instruction, so temporary interrupt blocking
723 * should be removed, if set.
725 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
726 if (interruptibility & 3)
727 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
728 interruptibility & ~3);
729 vcpu->arch.interrupt_window_open = 1;
732 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
733 bool has_error_code, u32 error_code)
735 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
736 nr | INTR_TYPE_EXCEPTION
737 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
738 | INTR_INFO_VALID_MASK);
740 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
743 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
745 struct vcpu_vmx *vmx = to_vmx(vcpu);
747 return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
751 * Swap MSR entry in host/guest MSR entry array.
754 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
756 struct kvm_msr_entry tmp;
758 tmp = vmx->guest_msrs[to];
759 vmx->guest_msrs[to] = vmx->guest_msrs[from];
760 vmx->guest_msrs[from] = tmp;
761 tmp = vmx->host_msrs[to];
762 vmx->host_msrs[to] = vmx->host_msrs[from];
763 vmx->host_msrs[from] = tmp;
768 * Set up the vmcs to automatically save and restore system
769 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
770 * mode, as fiddling with msrs is very expensive.
772 static void setup_msrs(struct vcpu_vmx *vmx)
776 vmx_load_host_state(vmx);
779 if (is_long_mode(&vmx->vcpu)) {
782 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
784 move_msr_up(vmx, index, save_nmsrs++);
785 index = __find_msr_index(vmx, MSR_LSTAR);
787 move_msr_up(vmx, index, save_nmsrs++);
788 index = __find_msr_index(vmx, MSR_CSTAR);
790 move_msr_up(vmx, index, save_nmsrs++);
791 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
793 move_msr_up(vmx, index, save_nmsrs++);
795 * MSR_K6_STAR is only needed on long mode guests, and only
796 * if efer.sce is enabled.
798 index = __find_msr_index(vmx, MSR_K6_STAR);
799 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
800 move_msr_up(vmx, index, save_nmsrs++);
803 vmx->save_nmsrs = save_nmsrs;
806 vmx->msr_offset_kernel_gs_base =
807 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
809 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
813 * reads and returns guest's timestamp counter "register"
814 * guest_tsc = host_tsc + tsc_offset -- 21.3
816 static u64 guest_read_tsc(void)
818 u64 host_tsc, tsc_offset;
821 tsc_offset = vmcs_read64(TSC_OFFSET);
822 return host_tsc + tsc_offset;
826 * writes 'guest_tsc' into guest's timestamp counter "register"
827 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
829 static void guest_write_tsc(u64 guest_tsc)
834 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
838 * Reads an msr value (of 'msr_index') into 'pdata'.
839 * Returns 0 on success, non-0 otherwise.
840 * Assumes vcpu_load() was already called.
842 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
845 struct kvm_msr_entry *msr;
848 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
855 data = vmcs_readl(GUEST_FS_BASE);
858 data = vmcs_readl(GUEST_GS_BASE);
861 return kvm_get_msr_common(vcpu, msr_index, pdata);
863 case MSR_IA32_TIME_STAMP_COUNTER:
864 data = guest_read_tsc();
866 case MSR_IA32_SYSENTER_CS:
867 data = vmcs_read32(GUEST_SYSENTER_CS);
869 case MSR_IA32_SYSENTER_EIP:
870 data = vmcs_readl(GUEST_SYSENTER_EIP);
872 case MSR_IA32_SYSENTER_ESP:
873 data = vmcs_readl(GUEST_SYSENTER_ESP);
876 msr = find_msr_entry(to_vmx(vcpu), msr_index);
881 return kvm_get_msr_common(vcpu, msr_index, pdata);
889 * Writes msr value into into the appropriate "register".
890 * Returns 0 on success, non-0 otherwise.
891 * Assumes vcpu_load() was already called.
893 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
895 struct vcpu_vmx *vmx = to_vmx(vcpu);
896 struct kvm_msr_entry *msr;
902 vmx_load_host_state(vmx);
903 ret = kvm_set_msr_common(vcpu, msr_index, data);
906 vmcs_writel(GUEST_FS_BASE, data);
909 vmcs_writel(GUEST_GS_BASE, data);
912 case MSR_IA32_SYSENTER_CS:
913 vmcs_write32(GUEST_SYSENTER_CS, data);
915 case MSR_IA32_SYSENTER_EIP:
916 vmcs_writel(GUEST_SYSENTER_EIP, data);
918 case MSR_IA32_SYSENTER_ESP:
919 vmcs_writel(GUEST_SYSENTER_ESP, data);
921 case MSR_IA32_TIME_STAMP_COUNTER:
922 guest_write_tsc(data);
925 vmx_load_host_state(vmx);
926 msr = find_msr_entry(vmx, msr_index);
931 ret = kvm_set_msr_common(vcpu, msr_index, data);
938 * Sync the rsp and rip registers into the vcpu structure. This allows
939 * registers to be accessed by indexing vcpu->arch.regs.
941 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
943 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
944 vcpu->arch.rip = vmcs_readl(GUEST_RIP);
948 * Syncs rsp and rip back into the vmcs. Should be called after possible
951 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
953 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
954 vmcs_writel(GUEST_RIP, vcpu->arch.rip);
957 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
959 unsigned long dr7 = 0x400;
962 old_singlestep = vcpu->guest_debug.singlestep;
964 vcpu->guest_debug.enabled = dbg->enabled;
965 if (vcpu->guest_debug.enabled) {
968 dr7 |= 0x200; /* exact */
969 for (i = 0; i < 4; ++i) {
970 if (!dbg->breakpoints[i].enabled)
972 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
973 dr7 |= 2 << (i*2); /* global enable */
974 dr7 |= 0 << (i*4+16); /* execution breakpoint */
977 vcpu->guest_debug.singlestep = dbg->singlestep;
979 vcpu->guest_debug.singlestep = 0;
981 if (old_singlestep && !vcpu->guest_debug.singlestep) {
984 flags = vmcs_readl(GUEST_RFLAGS);
985 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
986 vmcs_writel(GUEST_RFLAGS, flags);
989 update_exception_bitmap(vcpu);
990 vmcs_writel(GUEST_DR7, dr7);
995 static int vmx_get_irq(struct kvm_vcpu *vcpu)
997 struct vcpu_vmx *vmx = to_vmx(vcpu);
1000 idtv_info_field = vmx->idt_vectoring_info;
1001 if (idtv_info_field & INTR_INFO_VALID_MASK) {
1002 if (is_external_interrupt(idtv_info_field))
1003 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
1005 printk(KERN_DEBUG "pending exception: not handled yet\n");
1010 static __init int cpu_has_kvm_support(void)
1012 unsigned long ecx = cpuid_ecx(1);
1013 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1016 static __init int vmx_disabled_by_bios(void)
1020 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1021 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1022 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1023 == MSR_IA32_FEATURE_CONTROL_LOCKED;
1024 /* locked but not enabled */
1027 static void hardware_enable(void *garbage)
1029 int cpu = raw_smp_processor_id();
1030 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1033 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1034 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1035 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1036 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1037 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
1038 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1039 /* enable and lock */
1040 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1041 MSR_IA32_FEATURE_CONTROL_LOCKED |
1042 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
1043 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1044 asm volatile (ASM_VMX_VMXON_RAX
1045 : : "a"(&phys_addr), "m"(phys_addr)
1049 static void vmclear_local_vcpus(void)
1051 int cpu = raw_smp_processor_id();
1052 struct vcpu_vmx *vmx, *n;
1054 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1059 static void hardware_disable(void *garbage)
1061 vmclear_local_vcpus();
1062 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1063 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1066 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1067 u32 msr, u32 *result)
1069 u32 vmx_msr_low, vmx_msr_high;
1070 u32 ctl = ctl_min | ctl_opt;
1072 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1074 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1075 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1077 /* Ensure minimum (required) set of control bits are supported. */
1085 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1087 u32 vmx_msr_low, vmx_msr_high;
1088 u32 min, opt, min2, opt2;
1089 u32 _pin_based_exec_control = 0;
1090 u32 _cpu_based_exec_control = 0;
1091 u32 _cpu_based_2nd_exec_control = 0;
1092 u32 _vmexit_control = 0;
1093 u32 _vmentry_control = 0;
1095 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1097 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1098 &_pin_based_exec_control) < 0)
1101 min = CPU_BASED_HLT_EXITING |
1102 #ifdef CONFIG_X86_64
1103 CPU_BASED_CR8_LOAD_EXITING |
1104 CPU_BASED_CR8_STORE_EXITING |
1106 CPU_BASED_CR3_LOAD_EXITING |
1107 CPU_BASED_CR3_STORE_EXITING |
1108 CPU_BASED_USE_IO_BITMAPS |
1109 CPU_BASED_MOV_DR_EXITING |
1110 CPU_BASED_USE_TSC_OFFSETING;
1111 opt = CPU_BASED_TPR_SHADOW |
1112 CPU_BASED_USE_MSR_BITMAPS |
1113 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1114 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1115 &_cpu_based_exec_control) < 0)
1117 #ifdef CONFIG_X86_64
1118 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1119 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1120 ~CPU_BASED_CR8_STORE_EXITING;
1122 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1124 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1125 SECONDARY_EXEC_WBINVD_EXITING |
1126 SECONDARY_EXEC_ENABLE_VPID |
1127 SECONDARY_EXEC_ENABLE_EPT;
1128 if (adjust_vmx_controls(min2, opt2,
1129 MSR_IA32_VMX_PROCBASED_CTLS2,
1130 &_cpu_based_2nd_exec_control) < 0)
1133 #ifndef CONFIG_X86_64
1134 if (!(_cpu_based_2nd_exec_control &
1135 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1136 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1138 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1139 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1140 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1141 CPU_BASED_CR3_STORE_EXITING);
1142 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1143 &_cpu_based_exec_control) < 0)
1145 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1146 vmx_capability.ept, vmx_capability.vpid);
1150 #ifdef CONFIG_X86_64
1151 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1154 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1155 &_vmexit_control) < 0)
1159 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1160 &_vmentry_control) < 0)
1163 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1165 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1166 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1169 #ifdef CONFIG_X86_64
1170 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1171 if (vmx_msr_high & (1u<<16))
1175 /* Require Write-Back (WB) memory type for VMCS accesses. */
1176 if (((vmx_msr_high >> 18) & 15) != 6)
1179 vmcs_conf->size = vmx_msr_high & 0x1fff;
1180 vmcs_conf->order = get_order(vmcs_config.size);
1181 vmcs_conf->revision_id = vmx_msr_low;
1183 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1184 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1185 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1186 vmcs_conf->vmexit_ctrl = _vmexit_control;
1187 vmcs_conf->vmentry_ctrl = _vmentry_control;
1192 static struct vmcs *alloc_vmcs_cpu(int cpu)
1194 int node = cpu_to_node(cpu);
1198 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1201 vmcs = page_address(pages);
1202 memset(vmcs, 0, vmcs_config.size);
1203 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1207 static struct vmcs *alloc_vmcs(void)
1209 return alloc_vmcs_cpu(raw_smp_processor_id());
1212 static void free_vmcs(struct vmcs *vmcs)
1214 free_pages((unsigned long)vmcs, vmcs_config.order);
1217 static void free_kvm_area(void)
1221 for_each_online_cpu(cpu)
1222 free_vmcs(per_cpu(vmxarea, cpu));
1225 static __init int alloc_kvm_area(void)
1229 for_each_online_cpu(cpu) {
1232 vmcs = alloc_vmcs_cpu(cpu);
1238 per_cpu(vmxarea, cpu) = vmcs;
1243 static __init int hardware_setup(void)
1245 if (setup_vmcs_config(&vmcs_config) < 0)
1248 if (boot_cpu_has(X86_FEATURE_NX))
1249 kvm_enable_efer_bits(EFER_NX);
1251 return alloc_kvm_area();
1254 static __exit void hardware_unsetup(void)
1259 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1261 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1263 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1264 vmcs_write16(sf->selector, save->selector);
1265 vmcs_writel(sf->base, save->base);
1266 vmcs_write32(sf->limit, save->limit);
1267 vmcs_write32(sf->ar_bytes, save->ar);
1269 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1271 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1275 static void enter_pmode(struct kvm_vcpu *vcpu)
1277 unsigned long flags;
1279 vcpu->arch.rmode.active = 0;
1281 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1282 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1283 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1285 flags = vmcs_readl(GUEST_RFLAGS);
1286 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1287 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1288 vmcs_writel(GUEST_RFLAGS, flags);
1290 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1291 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1293 update_exception_bitmap(vcpu);
1295 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1296 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1297 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1298 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1300 vmcs_write16(GUEST_SS_SELECTOR, 0);
1301 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1303 vmcs_write16(GUEST_CS_SELECTOR,
1304 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1305 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1308 static gva_t rmode_tss_base(struct kvm *kvm)
1310 if (!kvm->arch.tss_addr) {
1311 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1312 kvm->memslots[0].npages - 3;
1313 return base_gfn << PAGE_SHIFT;
1315 return kvm->arch.tss_addr;
1318 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1320 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1322 save->selector = vmcs_read16(sf->selector);
1323 save->base = vmcs_readl(sf->base);
1324 save->limit = vmcs_read32(sf->limit);
1325 save->ar = vmcs_read32(sf->ar_bytes);
1326 vmcs_write16(sf->selector, save->base >> 4);
1327 vmcs_write32(sf->base, save->base & 0xfffff);
1328 vmcs_write32(sf->limit, 0xffff);
1329 vmcs_write32(sf->ar_bytes, 0xf3);
1332 static void enter_rmode(struct kvm_vcpu *vcpu)
1334 unsigned long flags;
1336 vcpu->arch.rmode.active = 1;
1338 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1339 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1341 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1342 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1344 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1345 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1347 flags = vmcs_readl(GUEST_RFLAGS);
1348 vcpu->arch.rmode.save_iopl
1349 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1351 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1353 vmcs_writel(GUEST_RFLAGS, flags);
1354 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1355 update_exception_bitmap(vcpu);
1357 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1358 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1359 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1361 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1362 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1363 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1364 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1365 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1367 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1368 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1369 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1370 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1372 kvm_mmu_reset_context(vcpu);
1373 init_rmode(vcpu->kvm);
1376 #ifdef CONFIG_X86_64
1378 static void enter_lmode(struct kvm_vcpu *vcpu)
1382 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1383 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1384 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1386 vmcs_write32(GUEST_TR_AR_BYTES,
1387 (guest_tr_ar & ~AR_TYPE_MASK)
1388 | AR_TYPE_BUSY_64_TSS);
1391 vcpu->arch.shadow_efer |= EFER_LMA;
1393 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1394 vmcs_write32(VM_ENTRY_CONTROLS,
1395 vmcs_read32(VM_ENTRY_CONTROLS)
1396 | VM_ENTRY_IA32E_MODE);
1399 static void exit_lmode(struct kvm_vcpu *vcpu)
1401 vcpu->arch.shadow_efer &= ~EFER_LMA;
1403 vmcs_write32(VM_ENTRY_CONTROLS,
1404 vmcs_read32(VM_ENTRY_CONTROLS)
1405 & ~VM_ENTRY_IA32E_MODE);
1410 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1412 vpid_sync_vcpu_all(to_vmx(vcpu));
1415 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1417 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1418 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1421 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1423 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1424 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1425 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1428 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1429 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1430 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1431 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1435 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1437 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1439 struct kvm_vcpu *vcpu)
1441 if (!(cr0 & X86_CR0_PG)) {
1442 /* From paging/starting to nonpaging */
1443 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1444 vmcs_config.cpu_based_exec_ctrl |
1445 (CPU_BASED_CR3_LOAD_EXITING |
1446 CPU_BASED_CR3_STORE_EXITING));
1447 vcpu->arch.cr0 = cr0;
1448 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1449 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1450 *hw_cr0 &= ~X86_CR0_WP;
1451 } else if (!is_paging(vcpu)) {
1452 /* From nonpaging to paging */
1453 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1454 vmcs_config.cpu_based_exec_ctrl &
1455 ~(CPU_BASED_CR3_LOAD_EXITING |
1456 CPU_BASED_CR3_STORE_EXITING));
1457 vcpu->arch.cr0 = cr0;
1458 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1459 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1460 *hw_cr0 &= ~X86_CR0_WP;
1464 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1465 struct kvm_vcpu *vcpu)
1467 if (!is_paging(vcpu)) {
1468 *hw_cr4 &= ~X86_CR4_PAE;
1469 *hw_cr4 |= X86_CR4_PSE;
1470 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1471 *hw_cr4 &= ~X86_CR4_PAE;
1474 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1476 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1477 KVM_VM_CR0_ALWAYS_ON;
1479 vmx_fpu_deactivate(vcpu);
1481 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1484 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1487 #ifdef CONFIG_X86_64
1488 if (vcpu->arch.shadow_efer & EFER_LME) {
1489 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1491 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1497 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1499 vmcs_writel(CR0_READ_SHADOW, cr0);
1500 vmcs_writel(GUEST_CR0, hw_cr0);
1501 vcpu->arch.cr0 = cr0;
1503 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1504 vmx_fpu_activate(vcpu);
1507 static u64 construct_eptp(unsigned long root_hpa)
1511 /* TODO write the value reading from MSR */
1512 eptp = VMX_EPT_DEFAULT_MT |
1513 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1514 eptp |= (root_hpa & PAGE_MASK);
1519 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1521 unsigned long guest_cr3;
1525 if (vm_need_ept()) {
1526 eptp = construct_eptp(cr3);
1527 vmcs_write64(EPT_POINTER, eptp);
1528 ept_sync_context(eptp);
1529 ept_load_pdptrs(vcpu);
1530 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1531 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1534 vmx_flush_tlb(vcpu);
1535 vmcs_writel(GUEST_CR3, guest_cr3);
1536 if (vcpu->arch.cr0 & X86_CR0_PE)
1537 vmx_fpu_deactivate(vcpu);
1540 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1542 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1543 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1545 vcpu->arch.cr4 = cr4;
1547 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1549 vmcs_writel(CR4_READ_SHADOW, cr4);
1550 vmcs_writel(GUEST_CR4, hw_cr4);
1553 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1555 struct vcpu_vmx *vmx = to_vmx(vcpu);
1556 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1558 vcpu->arch.shadow_efer = efer;
1561 if (efer & EFER_LMA) {
1562 vmcs_write32(VM_ENTRY_CONTROLS,
1563 vmcs_read32(VM_ENTRY_CONTROLS) |
1564 VM_ENTRY_IA32E_MODE);
1568 vmcs_write32(VM_ENTRY_CONTROLS,
1569 vmcs_read32(VM_ENTRY_CONTROLS) &
1570 ~VM_ENTRY_IA32E_MODE);
1572 msr->data = efer & ~EFER_LME;
1577 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1579 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1581 return vmcs_readl(sf->base);
1584 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1585 struct kvm_segment *var, int seg)
1587 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1590 var->base = vmcs_readl(sf->base);
1591 var->limit = vmcs_read32(sf->limit);
1592 var->selector = vmcs_read16(sf->selector);
1593 ar = vmcs_read32(sf->ar_bytes);
1594 if (ar & AR_UNUSABLE_MASK)
1596 var->type = ar & 15;
1597 var->s = (ar >> 4) & 1;
1598 var->dpl = (ar >> 5) & 3;
1599 var->present = (ar >> 7) & 1;
1600 var->avl = (ar >> 12) & 1;
1601 var->l = (ar >> 13) & 1;
1602 var->db = (ar >> 14) & 1;
1603 var->g = (ar >> 15) & 1;
1604 var->unusable = (ar >> 16) & 1;
1607 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1609 struct kvm_segment kvm_seg;
1611 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1614 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1617 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1618 return kvm_seg.selector & 3;
1621 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1628 ar = var->type & 15;
1629 ar |= (var->s & 1) << 4;
1630 ar |= (var->dpl & 3) << 5;
1631 ar |= (var->present & 1) << 7;
1632 ar |= (var->avl & 1) << 12;
1633 ar |= (var->l & 1) << 13;
1634 ar |= (var->db & 1) << 14;
1635 ar |= (var->g & 1) << 15;
1637 if (ar == 0) /* a 0 value means unusable */
1638 ar = AR_UNUSABLE_MASK;
1643 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1644 struct kvm_segment *var, int seg)
1646 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1649 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1650 vcpu->arch.rmode.tr.selector = var->selector;
1651 vcpu->arch.rmode.tr.base = var->base;
1652 vcpu->arch.rmode.tr.limit = var->limit;
1653 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1656 vmcs_writel(sf->base, var->base);
1657 vmcs_write32(sf->limit, var->limit);
1658 vmcs_write16(sf->selector, var->selector);
1659 if (vcpu->arch.rmode.active && var->s) {
1661 * Hack real-mode segments into vm86 compatibility.
1663 if (var->base == 0xffff0000 && var->selector == 0xf000)
1664 vmcs_writel(sf->base, 0xf0000);
1667 ar = vmx_segment_access_rights(var);
1668 vmcs_write32(sf->ar_bytes, ar);
1671 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1673 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1675 *db = (ar >> 14) & 1;
1676 *l = (ar >> 13) & 1;
1679 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1681 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1682 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1685 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1687 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1688 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1691 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1693 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1694 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1697 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1699 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1700 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1703 static int init_rmode_tss(struct kvm *kvm)
1705 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1710 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1713 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1714 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1717 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1720 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1724 r = kvm_write_guest_page(kvm, fn, &data,
1725 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1735 static int init_rmode_identity_map(struct kvm *kvm)
1738 pfn_t identity_map_pfn;
1743 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1744 printk(KERN_ERR "EPT: identity-mapping pagetable "
1745 "haven't been allocated!\n");
1748 if (likely(kvm->arch.ept_identity_pagetable_done))
1751 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1752 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1755 /* Set up identity-mapping pagetable for EPT in real mode */
1756 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1757 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1758 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1759 r = kvm_write_guest_page(kvm, identity_map_pfn,
1760 &tmp, i * sizeof(tmp), sizeof(tmp));
1764 kvm->arch.ept_identity_pagetable_done = true;
1770 static void seg_setup(int seg)
1772 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1774 vmcs_write16(sf->selector, 0);
1775 vmcs_writel(sf->base, 0);
1776 vmcs_write32(sf->limit, 0xffff);
1777 vmcs_write32(sf->ar_bytes, 0x93);
1780 static int alloc_apic_access_page(struct kvm *kvm)
1782 struct kvm_userspace_memory_region kvm_userspace_mem;
1785 down_write(&kvm->slots_lock);
1786 if (kvm->arch.apic_access_page)
1788 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1789 kvm_userspace_mem.flags = 0;
1790 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1791 kvm_userspace_mem.memory_size = PAGE_SIZE;
1792 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1796 down_read(¤t->mm->mmap_sem);
1797 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1798 up_read(¤t->mm->mmap_sem);
1800 up_write(&kvm->slots_lock);
1804 static int alloc_identity_pagetable(struct kvm *kvm)
1806 struct kvm_userspace_memory_region kvm_userspace_mem;
1809 down_write(&kvm->slots_lock);
1810 if (kvm->arch.ept_identity_pagetable)
1812 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1813 kvm_userspace_mem.flags = 0;
1814 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1815 kvm_userspace_mem.memory_size = PAGE_SIZE;
1816 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1820 down_read(¤t->mm->mmap_sem);
1821 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1822 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1823 up_read(¤t->mm->mmap_sem);
1825 up_write(&kvm->slots_lock);
1829 static void allocate_vpid(struct vcpu_vmx *vmx)
1834 if (!enable_vpid || !cpu_has_vmx_vpid())
1836 spin_lock(&vmx_vpid_lock);
1837 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1838 if (vpid < VMX_NR_VPIDS) {
1840 __set_bit(vpid, vmx_vpid_bitmap);
1842 spin_unlock(&vmx_vpid_lock);
1845 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
1849 if (!cpu_has_vmx_msr_bitmap())
1853 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1854 * have the write-low and read-high bitmap offsets the wrong way round.
1855 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1857 va = kmap(msr_bitmap);
1858 if (msr <= 0x1fff) {
1859 __clear_bit(msr, va + 0x000); /* read-low */
1860 __clear_bit(msr, va + 0x800); /* write-low */
1861 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1863 __clear_bit(msr, va + 0x400); /* read-high */
1864 __clear_bit(msr, va + 0xc00); /* write-high */
1870 * Sets up the vmcs for emulated real mode.
1872 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1874 u32 host_sysenter_cs;
1877 struct descriptor_table dt;
1879 unsigned long kvm_vmx_return;
1883 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1884 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1886 if (cpu_has_vmx_msr_bitmap())
1887 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1889 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1892 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1893 vmcs_config.pin_based_exec_ctrl);
1895 exec_control = vmcs_config.cpu_based_exec_ctrl;
1896 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1897 exec_control &= ~CPU_BASED_TPR_SHADOW;
1898 #ifdef CONFIG_X86_64
1899 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1900 CPU_BASED_CR8_LOAD_EXITING;
1904 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1905 CPU_BASED_CR3_LOAD_EXITING;
1906 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1908 if (cpu_has_secondary_exec_ctrls()) {
1909 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1910 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1912 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1914 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1916 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
1917 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1920 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1921 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1922 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1924 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1925 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1926 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1928 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1929 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1930 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1931 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1932 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1933 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1934 #ifdef CONFIG_X86_64
1935 rdmsrl(MSR_FS_BASE, a);
1936 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1937 rdmsrl(MSR_GS_BASE, a);
1938 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1940 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1941 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1944 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1947 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1949 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1950 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1951 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1952 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1953 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1955 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1956 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1957 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1958 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1959 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1960 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1962 for (i = 0; i < NR_VMX_MSR; ++i) {
1963 u32 index = vmx_msr_index[i];
1964 u32 data_low, data_high;
1968 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1970 if (wrmsr_safe(index, data_low, data_high) < 0)
1972 data = data_low | ((u64)data_high << 32);
1973 vmx->host_msrs[j].index = index;
1974 vmx->host_msrs[j].reserved = 0;
1975 vmx->host_msrs[j].data = data;
1976 vmx->guest_msrs[j] = vmx->host_msrs[j];
1980 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1982 /* 22.2.1, 20.8.1 */
1983 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1985 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1986 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1992 static int init_rmode(struct kvm *kvm)
1994 if (!init_rmode_tss(kvm))
1996 if (!init_rmode_identity_map(kvm))
2001 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2003 struct vcpu_vmx *vmx = to_vmx(vcpu);
2007 down_read(&vcpu->kvm->slots_lock);
2008 if (!init_rmode(vmx->vcpu.kvm)) {
2013 vmx->vcpu.arch.rmode.active = 0;
2015 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2016 kvm_set_cr8(&vmx->vcpu, 0);
2017 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2018 if (vmx->vcpu.vcpu_id == 0)
2019 msr |= MSR_IA32_APICBASE_BSP;
2020 kvm_set_apic_base(&vmx->vcpu, msr);
2022 fx_init(&vmx->vcpu);
2025 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2026 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2028 if (vmx->vcpu.vcpu_id == 0) {
2029 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2030 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2032 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2033 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2035 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2036 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2038 seg_setup(VCPU_SREG_DS);
2039 seg_setup(VCPU_SREG_ES);
2040 seg_setup(VCPU_SREG_FS);
2041 seg_setup(VCPU_SREG_GS);
2042 seg_setup(VCPU_SREG_SS);
2044 vmcs_write16(GUEST_TR_SELECTOR, 0);
2045 vmcs_writel(GUEST_TR_BASE, 0);
2046 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2047 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2049 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2050 vmcs_writel(GUEST_LDTR_BASE, 0);
2051 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2052 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2054 vmcs_write32(GUEST_SYSENTER_CS, 0);
2055 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2056 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2058 vmcs_writel(GUEST_RFLAGS, 0x02);
2059 if (vmx->vcpu.vcpu_id == 0)
2060 vmcs_writel(GUEST_RIP, 0xfff0);
2062 vmcs_writel(GUEST_RIP, 0);
2063 vmcs_writel(GUEST_RSP, 0);
2065 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2066 vmcs_writel(GUEST_DR7, 0x400);
2068 vmcs_writel(GUEST_GDTR_BASE, 0);
2069 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2071 vmcs_writel(GUEST_IDTR_BASE, 0);
2072 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2074 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2075 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2076 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2080 /* Special registers */
2081 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2085 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2087 if (cpu_has_vmx_tpr_shadow()) {
2088 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2089 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2090 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2091 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2092 vmcs_write32(TPR_THRESHOLD, 0);
2095 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2096 vmcs_write64(APIC_ACCESS_ADDR,
2097 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2100 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2102 vmx->vcpu.arch.cr0 = 0x60000010;
2103 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2104 vmx_set_cr4(&vmx->vcpu, 0);
2105 vmx_set_efer(&vmx->vcpu, 0);
2106 vmx_fpu_activate(&vmx->vcpu);
2107 update_exception_bitmap(&vmx->vcpu);
2109 vpid_sync_vcpu_all(vmx);
2114 up_read(&vcpu->kvm->slots_lock);
2118 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2120 struct vcpu_vmx *vmx = to_vmx(vcpu);
2122 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2124 if (vcpu->arch.rmode.active) {
2125 vmx->rmode.irq.pending = true;
2126 vmx->rmode.irq.vector = irq;
2127 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
2128 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2129 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2130 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2131 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
2134 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2135 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2138 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2140 int word_index = __ffs(vcpu->arch.irq_summary);
2141 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2142 int irq = word_index * BITS_PER_LONG + bit_index;
2144 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2145 if (!vcpu->arch.irq_pending[word_index])
2146 clear_bit(word_index, &vcpu->arch.irq_summary);
2147 vmx_inject_irq(vcpu, irq);
2151 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2152 struct kvm_run *kvm_run)
2154 u32 cpu_based_vm_exec_control;
2156 vcpu->arch.interrupt_window_open =
2157 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2158 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2160 if (vcpu->arch.interrupt_window_open &&
2161 vcpu->arch.irq_summary &&
2162 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
2164 * If interrupts enabled, and not blocked by sti or mov ss. Good.
2166 kvm_do_inject_irq(vcpu);
2168 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2169 if (!vcpu->arch.interrupt_window_open &&
2170 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2172 * Interrupts blocked. Wait for unblock.
2174 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2176 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2177 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2180 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2183 struct kvm_userspace_memory_region tss_mem = {
2185 .guest_phys_addr = addr,
2186 .memory_size = PAGE_SIZE * 3,
2190 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2193 kvm->arch.tss_addr = addr;
2197 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2199 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2201 set_debugreg(dbg->bp[0], 0);
2202 set_debugreg(dbg->bp[1], 1);
2203 set_debugreg(dbg->bp[2], 2);
2204 set_debugreg(dbg->bp[3], 3);
2206 if (dbg->singlestep) {
2207 unsigned long flags;
2209 flags = vmcs_readl(GUEST_RFLAGS);
2210 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2211 vmcs_writel(GUEST_RFLAGS, flags);
2215 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2216 int vec, u32 err_code)
2218 if (!vcpu->arch.rmode.active)
2222 * Instruction with address size override prefix opcode 0x67
2223 * Cause the #SS fault with 0 error code in VM86 mode.
2225 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2226 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2231 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2233 struct vcpu_vmx *vmx = to_vmx(vcpu);
2234 u32 intr_info, error_code;
2235 unsigned long cr2, rip;
2237 enum emulation_result er;
2239 vect_info = vmx->idt_vectoring_info;
2240 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2242 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2243 !is_page_fault(intr_info))
2244 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2245 "intr info 0x%x\n", __func__, vect_info, intr_info);
2247 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2248 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2249 set_bit(irq, vcpu->arch.irq_pending);
2250 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2253 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2254 return 1; /* already handled by vmx_vcpu_run() */
2256 if (is_no_device(intr_info)) {
2257 vmx_fpu_activate(vcpu);
2261 if (is_invalid_opcode(intr_info)) {
2262 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2263 if (er != EMULATE_DONE)
2264 kvm_queue_exception(vcpu, UD_VECTOR);
2269 rip = vmcs_readl(GUEST_RIP);
2270 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2271 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2272 if (is_page_fault(intr_info)) {
2273 /* EPT won't cause page fault directly */
2276 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2277 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2278 (u32)((u64)cr2 >> 32), handler);
2279 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2282 if (vcpu->arch.rmode.active &&
2283 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2285 if (vcpu->arch.halt_request) {
2286 vcpu->arch.halt_request = 0;
2287 return kvm_emulate_halt(vcpu);
2292 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2293 (INTR_TYPE_EXCEPTION | 1)) {
2294 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2297 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2298 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2299 kvm_run->ex.error_code = error_code;
2303 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2304 struct kvm_run *kvm_run)
2306 ++vcpu->stat.irq_exits;
2307 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2311 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2313 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2317 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2319 unsigned long exit_qualification;
2320 int size, down, in, string, rep;
2323 ++vcpu->stat.io_exits;
2324 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2325 string = (exit_qualification & 16) != 0;
2328 if (emulate_instruction(vcpu,
2329 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2334 size = (exit_qualification & 7) + 1;
2335 in = (exit_qualification & 8) != 0;
2336 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2337 rep = (exit_qualification & 32) != 0;
2338 port = exit_qualification >> 16;
2340 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2344 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2347 * Patch in the VMCALL instruction:
2349 hypercall[0] = 0x0f;
2350 hypercall[1] = 0x01;
2351 hypercall[2] = 0xc1;
2354 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2356 unsigned long exit_qualification;
2360 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2361 cr = exit_qualification & 15;
2362 reg = (exit_qualification >> 8) & 15;
2363 switch ((exit_qualification >> 4) & 3) {
2364 case 0: /* mov to cr */
2365 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg],
2366 (u32)((u64)vcpu->arch.regs[reg] >> 32), handler);
2369 vcpu_load_rsp_rip(vcpu);
2370 kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
2371 skip_emulated_instruction(vcpu);
2374 vcpu_load_rsp_rip(vcpu);
2375 kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
2376 skip_emulated_instruction(vcpu);
2379 vcpu_load_rsp_rip(vcpu);
2380 kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
2381 skip_emulated_instruction(vcpu);
2384 vcpu_load_rsp_rip(vcpu);
2385 kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
2386 skip_emulated_instruction(vcpu);
2387 if (irqchip_in_kernel(vcpu->kvm))
2389 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2394 vcpu_load_rsp_rip(vcpu);
2395 vmx_fpu_deactivate(vcpu);
2396 vcpu->arch.cr0 &= ~X86_CR0_TS;
2397 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2398 vmx_fpu_activate(vcpu);
2399 KVMTRACE_0D(CLTS, vcpu, handler);
2400 skip_emulated_instruction(vcpu);
2402 case 1: /*mov from cr*/
2405 vcpu_load_rsp_rip(vcpu);
2406 vcpu->arch.regs[reg] = vcpu->arch.cr3;
2407 vcpu_put_rsp_rip(vcpu);
2408 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2409 (u32)vcpu->arch.regs[reg],
2410 (u32)((u64)vcpu->arch.regs[reg] >> 32),
2412 skip_emulated_instruction(vcpu);
2415 vcpu_load_rsp_rip(vcpu);
2416 vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
2417 vcpu_put_rsp_rip(vcpu);
2418 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2419 (u32)vcpu->arch.regs[reg], handler);
2420 skip_emulated_instruction(vcpu);
2425 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2427 skip_emulated_instruction(vcpu);
2432 kvm_run->exit_reason = 0;
2433 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2434 (int)(exit_qualification >> 4) & 3, cr);
2438 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2440 unsigned long exit_qualification;
2445 * FIXME: this code assumes the host is debugging the guest.
2446 * need to deal with guest debugging itself too.
2448 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2449 dr = exit_qualification & 7;
2450 reg = (exit_qualification >> 8) & 15;
2451 vcpu_load_rsp_rip(vcpu);
2452 if (exit_qualification & 16) {
2464 vcpu->arch.regs[reg] = val;
2465 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2469 vcpu_put_rsp_rip(vcpu);
2470 skip_emulated_instruction(vcpu);
2474 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2476 kvm_emulate_cpuid(vcpu);
2480 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2482 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2485 if (vmx_get_msr(vcpu, ecx, &data)) {
2486 kvm_inject_gp(vcpu, 0);
2490 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2493 /* FIXME: handling of bits 32:63 of rax, rdx */
2494 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2495 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2496 skip_emulated_instruction(vcpu);
2500 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2502 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2503 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2504 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2506 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2509 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2510 kvm_inject_gp(vcpu, 0);
2514 skip_emulated_instruction(vcpu);
2518 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2519 struct kvm_run *kvm_run)
2524 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2525 struct kvm_run *kvm_run)
2527 u32 cpu_based_vm_exec_control;
2529 /* clear pending irq */
2530 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2531 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2532 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2534 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2537 * If the user space waits to inject interrupts, exit as soon as
2540 if (kvm_run->request_interrupt_window &&
2541 !vcpu->arch.irq_summary) {
2542 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2543 ++vcpu->stat.irq_window_exits;
2549 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2551 skip_emulated_instruction(vcpu);
2552 return kvm_emulate_halt(vcpu);
2555 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2557 skip_emulated_instruction(vcpu);
2558 kvm_emulate_hypercall(vcpu);
2562 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2564 skip_emulated_instruction(vcpu);
2565 /* TODO: Add support for VT-d/pass-through device */
2569 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2571 u64 exit_qualification;
2572 enum emulation_result er;
2573 unsigned long offset;
2575 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2576 offset = exit_qualification & 0xffful;
2578 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2580 if (er != EMULATE_DONE) {
2582 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2589 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2591 unsigned long exit_qualification;
2595 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2597 reason = (u32)exit_qualification >> 30;
2598 tss_selector = exit_qualification;
2600 return kvm_task_switch(vcpu, tss_selector, reason);
2603 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2605 u64 exit_qualification;
2606 enum emulation_result er;
2612 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2614 if (exit_qualification & (1 << 6)) {
2615 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2619 gla_validity = (exit_qualification >> 7) & 0x3;
2620 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2621 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2622 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2623 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2624 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2625 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2626 (long unsigned int)exit_qualification);
2627 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2628 kvm_run->hw.hardware_exit_reason = 0;
2632 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2633 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2634 if (!kvm_is_error_hva(hva)) {
2635 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2637 printk(KERN_ERR "EPT: Not enough memory!\n");
2643 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2645 if (er == EMULATE_FAIL) {
2647 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2649 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2650 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2651 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2652 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2653 (long unsigned int)exit_qualification);
2655 } else if (er == EMULATE_DO_MMIO)
2662 * The exit handlers return 1 if the exit was handled fully and guest execution
2663 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2664 * to be done to userspace and return 0.
2666 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2667 struct kvm_run *kvm_run) = {
2668 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2669 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2670 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2671 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2672 [EXIT_REASON_CR_ACCESS] = handle_cr,
2673 [EXIT_REASON_DR_ACCESS] = handle_dr,
2674 [EXIT_REASON_CPUID] = handle_cpuid,
2675 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2676 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2677 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2678 [EXIT_REASON_HLT] = handle_halt,
2679 [EXIT_REASON_VMCALL] = handle_vmcall,
2680 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2681 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
2682 [EXIT_REASON_WBINVD] = handle_wbinvd,
2683 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
2684 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
2687 static const int kvm_vmx_max_exit_handlers =
2688 ARRAY_SIZE(kvm_vmx_exit_handlers);
2691 * The guest has exited. See if we can fix it or if we need userspace
2694 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2696 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2697 struct vcpu_vmx *vmx = to_vmx(vcpu);
2698 u32 vectoring_info = vmx->idt_vectoring_info;
2700 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP),
2701 (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit);
2703 /* Access CR3 don't cause VMExit in paging mode, so we need
2704 * to sync with guest real CR3. */
2705 if (vm_need_ept() && is_paging(vcpu)) {
2706 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2707 ept_load_pdptrs(vcpu);
2710 if (unlikely(vmx->fail)) {
2711 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2712 kvm_run->fail_entry.hardware_entry_failure_reason
2713 = vmcs_read32(VM_INSTRUCTION_ERROR);
2717 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2718 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2719 exit_reason != EXIT_REASON_EPT_VIOLATION))
2720 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2721 "exit reason is 0x%x\n", __func__, exit_reason);
2722 if (exit_reason < kvm_vmx_max_exit_handlers
2723 && kvm_vmx_exit_handlers[exit_reason])
2724 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2726 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2727 kvm_run->hw.hardware_exit_reason = exit_reason;
2732 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2736 if (!vm_need_tpr_shadow(vcpu->kvm))
2739 if (!kvm_lapic_enabled(vcpu) ||
2740 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2741 vmcs_write32(TPR_THRESHOLD, 0);
2745 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2746 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2749 static void enable_irq_window(struct kvm_vcpu *vcpu)
2751 u32 cpu_based_vm_exec_control;
2753 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2754 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2755 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2758 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2760 struct vcpu_vmx *vmx = to_vmx(vcpu);
2761 u32 idtv_info_field, intr_info_field;
2762 int has_ext_irq, interrupt_window_open;
2765 update_tpr_threshold(vcpu);
2767 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2768 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2769 idtv_info_field = vmx->idt_vectoring_info;
2770 if (intr_info_field & INTR_INFO_VALID_MASK) {
2771 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2772 /* TODO: fault when IDT_Vectoring */
2773 if (printk_ratelimit())
2774 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2777 enable_irq_window(vcpu);
2780 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2781 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2782 == INTR_TYPE_EXT_INTR
2783 && vcpu->arch.rmode.active) {
2784 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2786 vmx_inject_irq(vcpu, vect);
2787 if (unlikely(has_ext_irq))
2788 enable_irq_window(vcpu);
2792 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2794 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2795 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2796 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2798 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
2799 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2800 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2801 if (unlikely(has_ext_irq))
2802 enable_irq_window(vcpu);
2807 interrupt_window_open =
2808 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2809 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2810 if (interrupt_window_open) {
2811 vector = kvm_cpu_get_interrupt(vcpu);
2812 vmx_inject_irq(vcpu, vector);
2813 kvm_timer_intr_post(vcpu, vector);
2815 enable_irq_window(vcpu);
2819 * Failure to inject an interrupt should give us the information
2820 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2821 * when fetching the interrupt redirection bitmap in the real-mode
2822 * tss, this doesn't happen. So we do it ourselves.
2824 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2826 vmx->rmode.irq.pending = 0;
2827 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2829 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2830 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2831 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2832 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2835 vmx->idt_vectoring_info =
2836 VECTORING_INFO_VALID_MASK
2837 | INTR_TYPE_EXT_INTR
2838 | vmx->rmode.irq.vector;
2841 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2843 struct vcpu_vmx *vmx = to_vmx(vcpu);
2847 * Loading guest fpu may have cleared host cr0.ts
2849 vmcs_writel(HOST_CR0, read_cr0());
2852 /* Store host registers */
2853 #ifdef CONFIG_X86_64
2854 "push %%rdx; push %%rbp;"
2857 "push %%edx; push %%ebp;"
2860 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
2861 /* Check if vmlaunch of vmresume is needed */
2862 "cmpl $0, %c[launched](%0) \n\t"
2863 /* Load guest registers. Don't clobber flags. */
2864 #ifdef CONFIG_X86_64
2865 "mov %c[cr2](%0), %%rax \n\t"
2866 "mov %%rax, %%cr2 \n\t"
2867 "mov %c[rax](%0), %%rax \n\t"
2868 "mov %c[rbx](%0), %%rbx \n\t"
2869 "mov %c[rdx](%0), %%rdx \n\t"
2870 "mov %c[rsi](%0), %%rsi \n\t"
2871 "mov %c[rdi](%0), %%rdi \n\t"
2872 "mov %c[rbp](%0), %%rbp \n\t"
2873 "mov %c[r8](%0), %%r8 \n\t"
2874 "mov %c[r9](%0), %%r9 \n\t"
2875 "mov %c[r10](%0), %%r10 \n\t"
2876 "mov %c[r11](%0), %%r11 \n\t"
2877 "mov %c[r12](%0), %%r12 \n\t"
2878 "mov %c[r13](%0), %%r13 \n\t"
2879 "mov %c[r14](%0), %%r14 \n\t"
2880 "mov %c[r15](%0), %%r15 \n\t"
2881 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2883 "mov %c[cr2](%0), %%eax \n\t"
2884 "mov %%eax, %%cr2 \n\t"
2885 "mov %c[rax](%0), %%eax \n\t"
2886 "mov %c[rbx](%0), %%ebx \n\t"
2887 "mov %c[rdx](%0), %%edx \n\t"
2888 "mov %c[rsi](%0), %%esi \n\t"
2889 "mov %c[rdi](%0), %%edi \n\t"
2890 "mov %c[rbp](%0), %%ebp \n\t"
2891 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2893 /* Enter guest mode */
2894 "jne .Llaunched \n\t"
2895 __ex(ASM_VMX_VMLAUNCH) "\n\t"
2896 "jmp .Lkvm_vmx_return \n\t"
2897 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
2898 ".Lkvm_vmx_return: "
2899 /* Save guest registers, load host registers, keep flags */
2900 #ifdef CONFIG_X86_64
2901 "xchg %0, (%%rsp) \n\t"
2902 "mov %%rax, %c[rax](%0) \n\t"
2903 "mov %%rbx, %c[rbx](%0) \n\t"
2904 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2905 "mov %%rdx, %c[rdx](%0) \n\t"
2906 "mov %%rsi, %c[rsi](%0) \n\t"
2907 "mov %%rdi, %c[rdi](%0) \n\t"
2908 "mov %%rbp, %c[rbp](%0) \n\t"
2909 "mov %%r8, %c[r8](%0) \n\t"
2910 "mov %%r9, %c[r9](%0) \n\t"
2911 "mov %%r10, %c[r10](%0) \n\t"
2912 "mov %%r11, %c[r11](%0) \n\t"
2913 "mov %%r12, %c[r12](%0) \n\t"
2914 "mov %%r13, %c[r13](%0) \n\t"
2915 "mov %%r14, %c[r14](%0) \n\t"
2916 "mov %%r15, %c[r15](%0) \n\t"
2917 "mov %%cr2, %%rax \n\t"
2918 "mov %%rax, %c[cr2](%0) \n\t"
2920 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
2922 "xchg %0, (%%esp) \n\t"
2923 "mov %%eax, %c[rax](%0) \n\t"
2924 "mov %%ebx, %c[rbx](%0) \n\t"
2925 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2926 "mov %%edx, %c[rdx](%0) \n\t"
2927 "mov %%esi, %c[rsi](%0) \n\t"
2928 "mov %%edi, %c[rdi](%0) \n\t"
2929 "mov %%ebp, %c[rbp](%0) \n\t"
2930 "mov %%cr2, %%eax \n\t"
2931 "mov %%eax, %c[cr2](%0) \n\t"
2933 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2935 "setbe %c[fail](%0) \n\t"
2936 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2937 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2938 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2939 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2940 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2941 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2942 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2943 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2944 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2945 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
2946 #ifdef CONFIG_X86_64
2947 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2948 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2949 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2950 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2951 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2952 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2953 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2954 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
2956 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
2958 #ifdef CONFIG_X86_64
2959 , "rbx", "rdi", "rsi"
2960 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2962 , "ebx", "edi", "rsi"
2966 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2967 if (vmx->rmode.irq.pending)
2968 fixup_rmode_irq(vmx);
2970 vcpu->arch.interrupt_window_open =
2971 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2973 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2976 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2978 /* We need to handle NMIs before interrupts are enabled */
2979 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
2980 KVMTRACE_0D(NMI, vcpu, handler);
2985 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2987 struct vcpu_vmx *vmx = to_vmx(vcpu);
2991 free_vmcs(vmx->vmcs);
2996 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2998 struct vcpu_vmx *vmx = to_vmx(vcpu);
3000 spin_lock(&vmx_vpid_lock);
3002 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3003 spin_unlock(&vmx_vpid_lock);
3004 vmx_free_vmcs(vcpu);
3005 kfree(vmx->host_msrs);
3006 kfree(vmx->guest_msrs);
3007 kvm_vcpu_uninit(vcpu);
3008 kmem_cache_free(kvm_vcpu_cache, vmx);
3011 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3014 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3018 return ERR_PTR(-ENOMEM);
3021 if (id == 0 && vm_need_ept()) {
3022 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3023 VMX_EPT_WRITABLE_MASK |
3024 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3025 kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK,
3026 VMX_EPT_FAKE_DIRTY_MASK, 0ull,
3027 VMX_EPT_EXECUTABLE_MASK);
3031 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3035 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3036 if (!vmx->guest_msrs) {
3041 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3042 if (!vmx->host_msrs)
3043 goto free_guest_msrs;
3045 vmx->vmcs = alloc_vmcs();
3049 vmcs_clear(vmx->vmcs);
3052 vmx_vcpu_load(&vmx->vcpu, cpu);
3053 err = vmx_vcpu_setup(vmx);
3054 vmx_vcpu_put(&vmx->vcpu);
3058 if (vm_need_virtualize_apic_accesses(kvm))
3059 if (alloc_apic_access_page(kvm) != 0)
3063 if (alloc_identity_pagetable(kvm) != 0)
3069 free_vmcs(vmx->vmcs);
3071 kfree(vmx->host_msrs);
3073 kfree(vmx->guest_msrs);
3075 kvm_vcpu_uninit(&vmx->vcpu);
3077 kmem_cache_free(kvm_vcpu_cache, vmx);
3078 return ERR_PTR(err);
3081 static void __init vmx_check_processor_compat(void *rtn)
3083 struct vmcs_config vmcs_conf;
3086 if (setup_vmcs_config(&vmcs_conf) < 0)
3088 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3089 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3090 smp_processor_id());
3095 static int get_ept_level(void)
3097 return VMX_EPT_DEFAULT_GAW + 1;
3100 static struct kvm_x86_ops vmx_x86_ops = {
3101 .cpu_has_kvm_support = cpu_has_kvm_support,
3102 .disabled_by_bios = vmx_disabled_by_bios,
3103 .hardware_setup = hardware_setup,
3104 .hardware_unsetup = hardware_unsetup,
3105 .check_processor_compatibility = vmx_check_processor_compat,
3106 .hardware_enable = hardware_enable,
3107 .hardware_disable = hardware_disable,
3108 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3110 .vcpu_create = vmx_create_vcpu,
3111 .vcpu_free = vmx_free_vcpu,
3112 .vcpu_reset = vmx_vcpu_reset,
3114 .prepare_guest_switch = vmx_save_host_state,
3115 .vcpu_load = vmx_vcpu_load,
3116 .vcpu_put = vmx_vcpu_put,
3117 .vcpu_decache = vmx_vcpu_decache,
3119 .set_guest_debug = set_guest_debug,
3120 .guest_debug_pre = kvm_guest_debug_pre,
3121 .get_msr = vmx_get_msr,
3122 .set_msr = vmx_set_msr,
3123 .get_segment_base = vmx_get_segment_base,
3124 .get_segment = vmx_get_segment,
3125 .set_segment = vmx_set_segment,
3126 .get_cpl = vmx_get_cpl,
3127 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3128 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3129 .set_cr0 = vmx_set_cr0,
3130 .set_cr3 = vmx_set_cr3,
3131 .set_cr4 = vmx_set_cr4,
3132 .set_efer = vmx_set_efer,
3133 .get_idt = vmx_get_idt,
3134 .set_idt = vmx_set_idt,
3135 .get_gdt = vmx_get_gdt,
3136 .set_gdt = vmx_set_gdt,
3137 .cache_regs = vcpu_load_rsp_rip,
3138 .decache_regs = vcpu_put_rsp_rip,
3139 .get_rflags = vmx_get_rflags,
3140 .set_rflags = vmx_set_rflags,
3142 .tlb_flush = vmx_flush_tlb,
3144 .run = vmx_vcpu_run,
3145 .handle_exit = kvm_handle_exit,
3146 .skip_emulated_instruction = skip_emulated_instruction,
3147 .patch_hypercall = vmx_patch_hypercall,
3148 .get_irq = vmx_get_irq,
3149 .set_irq = vmx_inject_irq,
3150 .queue_exception = vmx_queue_exception,
3151 .exception_injected = vmx_exception_injected,
3152 .inject_pending_irq = vmx_intr_assist,
3153 .inject_pending_vectors = do_interrupt_requests,
3155 .set_tss_addr = vmx_set_tss_addr,
3156 .get_tdp_level = get_ept_level,
3159 static int __init vmx_init(void)
3164 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3165 if (!vmx_io_bitmap_a)
3168 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3169 if (!vmx_io_bitmap_b) {
3174 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3175 if (!vmx_msr_bitmap) {
3181 * Allow direct access to the PC debug port (it is often used for I/O
3182 * delays, but the vmexits simply slow things down).
3184 va = kmap(vmx_io_bitmap_a);
3185 memset(va, 0xff, PAGE_SIZE);
3186 clear_bit(0x80, va);
3187 kunmap(vmx_io_bitmap_a);
3189 va = kmap(vmx_io_bitmap_b);
3190 memset(va, 0xff, PAGE_SIZE);
3191 kunmap(vmx_io_bitmap_b);
3193 va = kmap(vmx_msr_bitmap);
3194 memset(va, 0xff, PAGE_SIZE);
3195 kunmap(vmx_msr_bitmap);
3197 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3199 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3203 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3204 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3205 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3206 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3207 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3209 if (cpu_has_vmx_ept())
3210 bypass_guest_pf = 0;
3212 if (bypass_guest_pf)
3213 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3220 __free_page(vmx_msr_bitmap);
3222 __free_page(vmx_io_bitmap_b);
3224 __free_page(vmx_io_bitmap_a);
3228 static void __exit vmx_exit(void)
3230 __free_page(vmx_msr_bitmap);
3231 __free_page(vmx_io_bitmap_b);
3232 __free_page(vmx_io_bitmap_a);
3237 module_init(vmx_init)
3238 module_exit(vmx_exit)