arch/x86_64/kernel/pci-calgary.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/proto.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44 #include <asm/rio.h>
  45
  46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  47 int use_calgary __read_mostly = 1;
  48 #else
  49 int use_calgary __read_mostly = 0;
  50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  51
  52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  53 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  54
  55 /* register offsets inside the host bridge space */
  56 #define CALGARY_CONFIG_REG      0x0108
  57 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  58 #define PHB_PLSSR_OFFSET        0x0120
  59 #define PHB_CONFIG_RW_OFFSET    0x0160
  60 #define PHB_IOBASE_BAR_LOW      0x0170
  61 #define PHB_IOBASE_BAR_HIGH     0x0180
  62 #define PHB_MEM_1_LOW           0x0190
  63 #define PHB_MEM_1_HIGH          0x01A0
  64 #define PHB_IO_ADDR_SIZE        0x01B0
  65 #define PHB_MEM_1_SIZE          0x01C0
  66 #define PHB_MEM_ST_OFFSET       0x01D0
  67 #define PHB_AER_OFFSET          0x0200
  68 #define PHB_CONFIG_0_HIGH       0x0220
  69 #define PHB_CONFIG_0_LOW        0x0230
  70 #define PHB_CONFIG_0_END        0x0240
  71 #define PHB_MEM_2_LOW           0x02B0
  72 #define PHB_MEM_2_HIGH          0x02C0
  73 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  74 #define PHB_MEM_2_SIZE_LOW      0x02E0
  75 #define PHB_DOSHOLE_OFFSET      0x08E0
  76
  77 /* CalIOC2 specific */
  78 #define PHB_SAVIOR_L2           0x0DB0
  79 #define PHB_PAGE_MIG_CTRL       0x0DA8
  80 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  81 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  82
  83 /* PHB_CONFIG_RW */
  84 #define PHB_TCE_ENABLE          0x20000000
  85 #define PHB_SLOT_DISABLE        0x1C000000
  86 #define PHB_DAC_DISABLE         0x01000000
  87 #define PHB_MEM2_ENABLE         0x00400000
  88 #define PHB_MCSR_ENABLE         0x00100000
  89 /* TAR (Table Address Register) */
  90 #define TAR_SW_BITS             0x0000ffffffff800fUL
  91 #define TAR_VALID               0x0000000000000008UL
  92 /* CSR (Channel/DMA Status Register) */
  93 #define CSR_AGENT_MASK          0xffe0ffff
  94 /* CCR (Calgary Configuration Register) */
  95 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  96 /* PMCR/PMDR (Page Migration Control/Debug Registers */
  97 #define PMR_SOFTSTOP            0x80000000
  98 #define PMR_SOFTSTOPFAULT       0x40000000
  99 #define PMR_HARDSTOP            0x20000000
 100
 101 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 102 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 103 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 104 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 105 #define PHBS_PER_CALGARY        4
 106
 107 /* register offsets in Calgary's internal register space */
 108 static const unsigned long tar_offsets[] = {
 109         0x0580 /* TAR0 */,
 110         0x0588 /* TAR1 */,
 111         0x0590 /* TAR2 */,
 112         0x0598 /* TAR3 */
 113 };
 114
 115 static const unsigned long split_queue_offsets[] = {
 116         0x4870 /* SPLIT QUEUE 0 */,
 117         0x5870 /* SPLIT QUEUE 1 */,
 118         0x6870 /* SPLIT QUEUE 2 */,
 119         0x7870 /* SPLIT QUEUE 3 */
 120 };
 121
 122 static const unsigned long phb_offsets[] = {
 123         0x8000 /* PHB0 */,
 124         0x9000 /* PHB1 */,
 125         0xA000 /* PHB2 */,
 126         0xB000 /* PHB3 */
 127 };
 128
 129 /* PHB debug registers */
 130
 131 static const unsigned long phb_debug_offsets[] = {
 132         0x4000  /* PHB 0 DEBUG */,
 133         0x5000  /* PHB 1 DEBUG */,
 134         0x6000  /* PHB 2 DEBUG */,
 135         0x7000  /* PHB 3 DEBUG */
 136 };
 137
 138 /*
 139  * STUFF register for each debug PHB,
 140  * byte 1 = start bus number, byte 2 = end bus number
 141  */
 142
 143 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 144
 145 #define EMERGENCY_PAGES 32 /* = 128KB */
 146
 147 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 148 static int translate_empty_slots __read_mostly = 0;
 149 static int calgary_detected __read_mostly = 0;
 150
 151 static struct rio_table_hdr     *rio_table_hdr __initdata;
 152 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 153 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 154
 155 struct calgary_bus_info {
 156         void *tce_space;
 157         unsigned char translation_disabled;
 158         signed char phbid;
 159         void __iomem *bbar;
 160 };
 161
 162 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 163 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 164 static void calgary_dump_error_regs(struct iommu_table *tbl);
 165 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 166 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 167 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 168
 169 static struct cal_chipset_ops calgary_chip_ops = {
 170         .handle_quirks = calgary_handle_quirks,
 171         .tce_cache_blast = calgary_tce_cache_blast,
 172         .dump_error_regs = calgary_dump_error_regs
 173 };
 174
 175 static struct cal_chipset_ops calioc2_chip_ops = {
 176         .handle_quirks = calioc2_handle_quirks,
 177         .tce_cache_blast = calioc2_tce_cache_blast,
 178         .dump_error_regs = calioc2_dump_error_regs
 179 };
 180
 181 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 182
 183 /* enable this to stress test the chip's TCE cache */
 184 #ifdef CONFIG_IOMMU_DEBUG
 185 int debugging __read_mostly = 1;
 186
 187 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 188         int expected, unsigned long start, unsigned long end)
 189 {
 190         unsigned long idx = start;
 191
 192         BUG_ON(start >= end);
 193
 194         while (idx < end) {
 195                 if (!!test_bit(idx, bitmap) != expected)
 196                         return idx;
 197                 ++idx;
 198         }
 199
 200         /* all bits have the expected value */
 201         return ~0UL;
 202 }
 203 #else /* debugging is disabled */
 204 int debugging __read_mostly = 0;
 205
 206 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 207         int expected, unsigned long start, unsigned long end)
 208 {
 209         return ~0UL;
 210 }
 211
 212 #endif /* CONFIG_IOMMU_DEBUG */
 213
 214 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 215 {
 216         unsigned int npages;
 217
 218         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 219         npages >>= PAGE_SHIFT;
 220
 221         return npages;
 222 }
 223
 224 static inline int translate_phb(struct pci_dev* dev)
 225 {
 226         int disabled = bus_info[dev->bus->number].translation_disabled;
 227         return !disabled;
 228 }
 229
 230 static void iommu_range_reserve(struct iommu_table *tbl,
 231         unsigned long start_addr, unsigned int npages)
 232 {
 233         unsigned long index;
 234         unsigned long end;
 235         unsigned long badbit;
 236         unsigned long flags;
 237
 238         index = start_addr >> PAGE_SHIFT;
 239
 240         /* bail out if we're asked to reserve a region we don't cover */
 241         if (index >= tbl->it_size)
 242                 return;
 243
 244         end = index + npages;
 245         if (end > tbl->it_size) /* don't go off the table */
 246                 end = tbl->it_size;
 247
 248         spin_lock_irqsave(&tbl->it_lock, flags);
 249
 250         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 251         if (badbit != ~0UL) {
 252                 if (printk_ratelimit())
 253                         printk(KERN_ERR "Calgary: entry already allocated at "
 254                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 255                                badbit, tbl, start_addr, npages);
 256         }
 257
 258         set_bit_string(tbl->it_map, index, npages);
 259
 260         spin_unlock_irqrestore(&tbl->it_lock, flags);
 261 }
 262
 263 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 264         unsigned int npages)
 265 {
 266         unsigned long flags;
 267         unsigned long offset;
 268
 269         BUG_ON(npages == 0);
 270
 271         spin_lock_irqsave(&tbl->it_lock, flags);
 272
 273         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 274                                        tbl->it_size, npages);
 275         if (offset == ~0UL) {
 276                 tbl->chip_ops->tce_cache_blast(tbl);
 277                 offset = find_next_zero_string(tbl->it_map, 0,
 278                                                tbl->it_size, npages);
 279                 if (offset == ~0UL) {
 280                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 281                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 282                         if (panic_on_overflow)
 283                                 panic("Calgary: fix the allocator.\n");
 284                         else
 285                                 return bad_dma_address;
 286                 }
 287         }
 288
 289         set_bit_string(tbl->it_map, offset, npages);
 290         tbl->it_hint = offset + npages;
 291         BUG_ON(tbl->it_hint > tbl->it_size);
 292
 293         spin_unlock_irqrestore(&tbl->it_lock, flags);
 294
 295         return offset;
 296 }
 297
 298 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 299         unsigned int npages, int direction)
 300 {
 301         unsigned long entry;
 302         dma_addr_t ret = bad_dma_address;
 303
 304         entry = iommu_range_alloc(tbl, npages);
 305
 306         if (unlikely(entry == bad_dma_address))
 307                 goto error;
 308
 309         /* set the return dma address */
 310         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 311
 312         /* put the TCEs in the HW table */
 313         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 314                   direction);
 315
 316         return ret;
 317
 318 error:
 319         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 320                "iommu %p\n", npages, tbl);
 321         return bad_dma_address;
 322 }
 323
 324 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 325         unsigned int npages)
 326 {
 327         unsigned long entry;
 328         unsigned long badbit;
 329         unsigned long badend;
 330         unsigned long flags;
 331
 332         /* were we called with bad_dma_address? */
 333         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 334         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 335                 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
 336                        "address 0x%Lx\n", dma_addr);
 337                 WARN_ON(1);
 338                 return;
 339         }
 340
 341         entry = dma_addr >> PAGE_SHIFT;
 342
 343         BUG_ON(entry + npages > tbl->it_size);
 344
 345         tce_free(tbl, entry, npages);
 346
 347         spin_lock_irqsave(&tbl->it_lock, flags);
 348
 349         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 350         if (badbit != ~0UL) {
 351                 if (printk_ratelimit())
 352                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 353                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 354                                badbit, tbl, dma_addr, entry, npages);
 355         }
 356
 357         __clear_bit_string(tbl->it_map, entry, npages);
 358
 359         spin_unlock_irqrestore(&tbl->it_lock, flags);
 360 }
 361
 362 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 363         unsigned int npages)
 364 {
 365         __iommu_free(tbl, dma_addr, npages);
 366 }
 367
 368 static inline struct iommu_table *find_iommu_table(struct device *dev)
 369 {
 370         struct pci_dev *pdev;
 371         struct pci_bus *pbus;
 372         struct iommu_table *tbl;
 373
 374         pdev = to_pci_dev(dev);
 375
 376         /* is the device behind a bridge? */
 377         if (unlikely(pdev->bus->parent))
 378                 pbus = pdev->bus->parent;
 379         else
 380                 pbus = pdev->bus;
 381
 382         tbl = pbus->self->sysdata;
 383
 384         BUG_ON(pdev->bus->parent &&
 385                (tbl->it_busno != pdev->bus->parent->number));
 386
 387         return tbl;
 388 }
 389
 390 static void __calgary_unmap_sg(struct iommu_table *tbl,
 391         struct scatterlist *sglist, int nelems, int direction)
 392 {
 393         while (nelems--) {
 394                 unsigned int npages;
 395                 dma_addr_t dma = sglist->dma_address;
 396                 unsigned int dmalen = sglist->dma_length;
 397
 398                 if (dmalen == 0)
 399                         break;
 400
 401                 npages = num_dma_pages(dma, dmalen);
 402                 __iommu_free(tbl, dma, npages);
 403                 sglist++;
 404         }
 405 }
 406
 407 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 408                       int nelems, int direction)
 409 {
 410         struct iommu_table *tbl = find_iommu_table(dev);
 411
 412         if (!translate_phb(to_pci_dev(dev)))
 413                 return;
 414
 415         __calgary_unmap_sg(tbl, sglist, nelems, direction);
 416 }
 417
 418 static int calgary_nontranslate_map_sg(struct device* dev,
 419         struct scatterlist *sg, int nelems, int direction)
 420 {
 421         int i;
 422
 423         for (i = 0; i < nelems; i++ ) {
 424                 struct scatterlist *s = &sg[i];
 425                 BUG_ON(!s->page);
 426                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 427                 s->dma_length = s->length;
 428         }
 429         return nelems;
 430 }
 431
 432 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 433         int nelems, int direction)
 434 {
 435         struct iommu_table *tbl = find_iommu_table(dev);
 436         unsigned long vaddr;
 437         unsigned int npages;
 438         unsigned long entry;
 439         int i;
 440
 441         if (!translate_phb(to_pci_dev(dev)))
 442                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 443
 444         for (i = 0; i < nelems; i++ ) {
 445                 struct scatterlist *s = &sg[i];
 446                 BUG_ON(!s->page);
 447
 448                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 449                 npages = num_dma_pages(vaddr, s->length);
 450
 451                 entry = iommu_range_alloc(tbl, npages);
 452                 if (entry == bad_dma_address) {
 453                         /* makes sure unmap knows to stop */
 454                         s->dma_length = 0;
 455                         goto error;
 456                 }
 457
 458                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 459
 460                 /* insert into HW table */
 461                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 462                           direction);
 463
 464                 s->dma_length = s->length;
 465         }
 466
 467         return nelems;
 468 error:
 469         __calgary_unmap_sg(tbl, sg, nelems, direction);
 470         for (i = 0; i < nelems; i++) {
 471                 sg[i].dma_address = bad_dma_address;
 472                 sg[i].dma_length = 0;
 473         }
 474         return 0;
 475 }
 476
 477 static dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 478         size_t size, int direction)
 479 {
 480         dma_addr_t dma_handle = bad_dma_address;
 481         unsigned long uaddr;
 482         unsigned int npages;
 483         struct iommu_table *tbl = find_iommu_table(dev);
 484
 485         uaddr = (unsigned long)vaddr;
 486         npages = num_dma_pages(uaddr, size);
 487
 488         if (translate_phb(to_pci_dev(dev)))
 489                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 490         else
 491                 dma_handle = virt_to_bus(vaddr);
 492
 493         return dma_handle;
 494 }
 495
 496 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 497         size_t size, int direction)
 498 {
 499         struct iommu_table *tbl = find_iommu_table(dev);
 500         unsigned int npages;
 501
 502         if (!translate_phb(to_pci_dev(dev)))
 503                 return;
 504
 505         npages = num_dma_pages(dma_handle, size);
 506         iommu_free(tbl, dma_handle, npages);
 507 }
 508
 509 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 510         dma_addr_t *dma_handle, gfp_t flag)
 511 {
 512         void *ret = NULL;
 513         dma_addr_t mapping;
 514         unsigned int npages, order;
 515         struct iommu_table *tbl = find_iommu_table(dev);
 516
 517         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 518         npages = size >> PAGE_SHIFT;
 519         order = get_order(size);
 520
 521         /* alloc enough pages (and possibly more) */
 522         ret = (void *)__get_free_pages(flag, order);
 523         if (!ret)
 524                 goto error;
 525         memset(ret, 0, size);
 526
 527         if (translate_phb(to_pci_dev(dev))) {
 528                 /* set up tces to cover the allocated range */
 529                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 530                 if (mapping == bad_dma_address)
 531                         goto free;
 532
 533                 *dma_handle = mapping;
 534         } else /* non translated slot */
 535                 *dma_handle = virt_to_bus(ret);
 536
 537         return ret;
 538
 539 free:
 540         free_pages((unsigned long)ret, get_order(size));
 541         ret = NULL;
 542 error:
 543         return ret;
 544 }
 545
 546 static const struct dma_mapping_ops calgary_dma_ops = {
 547         .alloc_coherent = calgary_alloc_coherent,
 548         .map_single = calgary_map_single,
 549         .unmap_single = calgary_unmap_single,
 550         .map_sg = calgary_map_sg,
 551         .unmap_sg = calgary_unmap_sg,
 552 };
 553
 554 static inline void __iomem * busno_to_bbar(unsigned char num)
 555 {
 556         return bus_info[num].bbar;
 557 }
 558
 559 static inline int busno_to_phbid(unsigned char num)
 560 {
 561         return bus_info[num].phbid;
 562 }
 563
 564 static inline unsigned long split_queue_offset(unsigned char num)
 565 {
 566         size_t idx = busno_to_phbid(num);
 567
 568         return split_queue_offsets[idx];
 569 }
 570
 571 static inline unsigned long tar_offset(unsigned char num)
 572 {
 573         size_t idx = busno_to_phbid(num);
 574
 575         return tar_offsets[idx];
 576 }
 577
 578 static inline unsigned long phb_offset(unsigned char num)
 579 {
 580         size_t idx = busno_to_phbid(num);
 581
 582         return phb_offsets[idx];
 583 }
 584
 585 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 586 {
 587         unsigned long target = ((unsigned long)bar) | offset;
 588         return (void __iomem*)target;
 589 }
 590
 591 static inline int is_calioc2(unsigned short device)
 592 {
 593         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 594 }
 595
 596 static inline int is_calgary(unsigned short device)
 597 {
 598         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 599 }
 600
 601 static inline int is_cal_pci_dev(unsigned short device)
 602 {
 603         return (is_calgary(device) || is_calioc2(device));
 604 }
 605
 606 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 607 {
 608         u64 val;
 609         u32 aer;
 610         int i = 0;
 611         void __iomem *bbar = tbl->bbar;
 612         void __iomem *target;
 613
 614         /* disable arbitration on the bus */
 615         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 616         aer = readl(target);
 617         writel(0, target);
 618
 619         /* read plssr to ensure it got there */
 620         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 621         val = readl(target);
 622
 623         /* poll split queues until all DMA activity is done */
 624         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 625         do {
 626                 val = readq(target);
 627                 i++;
 628         } while ((val & 0xff) != 0xff && i < 100);
 629         if (i == 100)
 630                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 631                        "continuing anyway\n");
 632
 633         /* invalidate TCE cache */
 634         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 635         writeq(tbl->tar_val, target);
 636
 637         /* enable arbitration */
 638         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 639         writel(aer, target);
 640         (void)readl(target); /* flush */
 641 }
 642
 643 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 644 {
 645         void __iomem *bbar = tbl->bbar;
 646         void __iomem *target;
 647         u64 val64;
 648         u32 val;
 649         int i = 0;
 650         int count = 1;
 651         unsigned char bus = tbl->it_busno;
 652
 653 begin:
 654         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 655                "sequence - count %d\n", bus, count);
 656
 657         /* 1. using the Page Migration Control reg set SoftStop */
 658         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 659         val = be32_to_cpu(readl(target));
 660         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 661         val |= PMR_SOFTSTOP;
 662         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 663         writel(cpu_to_be32(val), target);
 664
 665         /* 2. poll split queues until all DMA activity is done */
 666         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 667         target = calgary_reg(bbar, split_queue_offset(bus));
 668         do {
 669                 val64 = readq(target);
 670                 i++;
 671         } while ((val64 & 0xff) != 0xff && i < 100);
 672         if (i == 100)
 673                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 674                        "continuing anyway\n");
 675
 676         /* 3. poll Page Migration DEBUG for SoftStopFault */
 677         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 678         val = be32_to_cpu(readl(target));
 679         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 680
 681         /* 4. if SoftStopFault - goto (1) */
 682         if (val & PMR_SOFTSTOPFAULT) {
 683                 if (++count < 100)
 684                         goto begin;
 685                 else {
 686                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 687                                "aborting TCE cache flush sequence!\n");
 688                         return; /* pray for the best */
 689                 }
 690         }
 691
 692         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 693         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 694         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 695         val = be32_to_cpu(readl(target));
 696         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 697         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 698         val = be32_to_cpu(readl(target));
 699         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 700
 701         /* 6. invalidate TCE cache */
 702         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 703         target = calgary_reg(bbar, tar_offset(bus));
 704         writeq(tbl->tar_val, target);
 705
 706         /* 7. Re-read PMCR */
 707         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 708         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 709         val = be32_to_cpu(readl(target));
 710         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 711
 712         /* 8. Remove HardStop */
 713         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 714         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 715         val = 0;
 716         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 717         writel(cpu_to_be32(val), target);
 718         val = be32_to_cpu(readl(target));
 719         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 720 }
 721
 722 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 723         u64 limit)
 724 {
 725         unsigned int numpages;
 726
 727         limit = limit | 0xfffff;
 728         limit++;
 729
 730         numpages = ((limit - start) >> PAGE_SHIFT);
 731         iommu_range_reserve(dev->sysdata, start, numpages);
 732 }
 733
 734 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 735 {
 736         void __iomem *target;
 737         u64 low, high, sizelow;
 738         u64 start, limit;
 739         struct iommu_table *tbl = dev->sysdata;
 740         unsigned char busnum = dev->bus->number;
 741         void __iomem *bbar = tbl->bbar;
 742
 743         /* peripheral MEM_1 region */
 744         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 745         low = be32_to_cpu(readl(target));
 746         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 747         high = be32_to_cpu(readl(target));
 748         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 749         sizelow = be32_to_cpu(readl(target));
 750
 751         start = (high << 32) | low;
 752         limit = sizelow;
 753
 754         calgary_reserve_mem_region(dev, start, limit);
 755 }
 756
 757 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 758 {
 759         void __iomem *target;
 760         u32 val32;
 761         u64 low, high, sizelow, sizehigh;
 762         u64 start, limit;
 763         struct iommu_table *tbl = dev->sysdata;
 764         unsigned char busnum = dev->bus->number;
 765         void __iomem *bbar = tbl->bbar;
 766
 767         /* is it enabled? */
 768         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 769         val32 = be32_to_cpu(readl(target));
 770         if (!(val32 & PHB_MEM2_ENABLE))
 771                 return;
 772
 773         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 774         low = be32_to_cpu(readl(target));
 775         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 776         high = be32_to_cpu(readl(target));
 777         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 778         sizelow = be32_to_cpu(readl(target));
 779         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 780         sizehigh = be32_to_cpu(readl(target));
 781
 782         start = (high << 32) | low;
 783         limit = (sizehigh << 32) | sizelow;
 784
 785         calgary_reserve_mem_region(dev, start, limit);
 786 }
 787
 788 /*
 789  * some regions of the IO address space do not get translated, so we
 790  * must not give devices IO addresses in those regions. The regions
 791  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 792  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 793  * later.
 794  */
 795 static void __init calgary_reserve_regions(struct pci_dev *dev)
 796 {
 797         unsigned int npages;
 798         u64 start;
 799         struct iommu_table *tbl = dev->sysdata;
 800
 801         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 802         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 803
 804         /* avoid the BIOS/VGA first 640KB-1MB region */
 805         /* for CalIOC2 - avoid the entire first MB */
 806         if (is_calgary(dev->device)) {
 807                 start = (640 * 1024);
 808                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 809         } else { /* calioc2 */
 810                 start = 0;
 811                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 812         }
 813         iommu_range_reserve(tbl, start, npages);
 814
 815         /* reserve the two PCI peripheral memory regions in IO space */
 816         calgary_reserve_peripheral_mem_1(dev);
 817         calgary_reserve_peripheral_mem_2(dev);
 818 }
 819
 820 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 821 {
 822         u64 val64;
 823         u64 table_phys;
 824         void __iomem *target;
 825         int ret;
 826         struct iommu_table *tbl;
 827
 828         /* build TCE tables for each PHB */
 829         ret = build_tce_table(dev, bbar);
 830         if (ret)
 831                 return ret;
 832
 833         tbl = dev->sysdata;
 834         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 835         tce_free(tbl, 0, tbl->it_size);
 836
 837         if (is_calgary(dev->device))
 838                 tbl->chip_ops = &calgary_chip_ops;
 839         else if (is_calioc2(dev->device))
 840                 tbl->chip_ops = &calioc2_chip_ops;
 841         else
 842                 BUG();
 843
 844         calgary_reserve_regions(dev);
 845
 846         /* set TARs for each PHB */
 847         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 848         val64 = be64_to_cpu(readq(target));
 849
 850         /* zero out all TAR bits under sw control */
 851         val64 &= ~TAR_SW_BITS;
 852         table_phys = (u64)__pa(tbl->it_base);
 853
 854         val64 |= table_phys;
 855
 856         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 857         val64 |= (u64) specified_table_size;
 858
 859         tbl->tar_val = cpu_to_be64(val64);
 860
 861         writeq(tbl->tar_val, target);
 862         readq(target); /* flush */
 863
 864         return 0;
 865 }
 866
 867 static void __init calgary_free_bus(struct pci_dev *dev)
 868 {
 869         u64 val64;
 870         struct iommu_table *tbl = dev->sysdata;
 871         void __iomem *target;
 872         unsigned int bitmapsz;
 873
 874         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 875         val64 = be64_to_cpu(readq(target));
 876         val64 &= ~TAR_SW_BITS;
 877         writeq(cpu_to_be64(val64), target);
 878         readq(target); /* flush */
 879
 880         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 881         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 882         tbl->it_map = NULL;
 883
 884         kfree(tbl);
 885         dev->sysdata = NULL;
 886
 887         /* Can't free bootmem allocated memory after system is up :-( */
 888         bus_info[dev->bus->number].tce_space = NULL;
 889 }
 890
 891 static void calgary_dump_error_regs(struct iommu_table *tbl)
 892 {
 893         void __iomem *bbar = tbl->bbar;
 894         void __iomem *target;
 895         u32 csr, plssr;
 896
 897         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 898         csr = be32_to_cpu(readl(target));
 899
 900         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 901         plssr = be32_to_cpu(readl(target));
 902
 903         /* If no error, the agent ID in the CSR is not valid */
 904         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 905                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 906 }
 907
 908 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 909 {
 910         void __iomem *bbar = tbl->bbar;
 911         u32 csr, csmr, plssr, mck, rcstat;
 912         void __iomem *target;
 913         unsigned long phboff = phb_offset(tbl->it_busno);
 914         unsigned long erroff;
 915         u32 errregs[7];
 916         int i;
 917
 918         /* dump CSR */
 919         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 920         csr = be32_to_cpu(readl(target));
 921         /* dump PLSSR */
 922         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 923         plssr = be32_to_cpu(readl(target));
 924         /* dump CSMR */
 925         target = calgary_reg(bbar, phboff | 0x290);
 926         csmr = be32_to_cpu(readl(target));
 927         /* dump mck */
 928         target = calgary_reg(bbar, phboff | 0x800);
 929         mck = be32_to_cpu(readl(target));
 930
 931         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 932                tbl->it_busno);
 933
 934         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 935                csr, plssr, csmr, mck);
 936
 937         /* dump rest of error regs */
 938         printk(KERN_EMERG "Calgary: ");
 939         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 940                 /* err regs are at 0x810 - 0x870 */
 941                 erroff = (0x810 + (i * 0x10));
 942                 target = calgary_reg(bbar, phboff | erroff);
 943                 errregs[i] = be32_to_cpu(readl(target));
 944                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 945         }
 946         printk("\n");
 947
 948         /* root complex status */
 949         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 950         rcstat = be32_to_cpu(readl(target));
 951         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 952                PHB_ROOT_COMPLEX_STATUS);
 953 }
 954
 955 static void calgary_watchdog(unsigned long data)
 956 {
 957         struct pci_dev *dev = (struct pci_dev *)data;
 958         struct iommu_table *tbl = dev->sysdata;
 959         void __iomem *bbar = tbl->bbar;
 960         u32 val32;
 961         void __iomem *target;
 962
 963         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 964         val32 = be32_to_cpu(readl(target));
 965
 966         /* If no error, the agent ID in the CSR is not valid */
 967         if (val32 & CSR_AGENT_MASK) {
 968                 tbl->chip_ops->dump_error_regs(tbl);
 969
 970                 /* reset error */
 971                 writel(0, target);
 972
 973                 /* Disable bus that caused the error */
 974                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 975                                      PHB_CONFIG_RW_OFFSET);
 976                 val32 = be32_to_cpu(readl(target));
 977                 val32 |= PHB_SLOT_DISABLE;
 978                 writel(cpu_to_be32(val32), target);
 979                 readl(target); /* flush */
 980         } else {
 981                 /* Reset the timer */
 982                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 983         }
 984 }
 985
 986 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 987         unsigned char busnum, unsigned long timeout)
 988 {
 989         u64 val64;
 990         void __iomem *target;
 991         unsigned int phb_shift = ~0; /* silence gcc */
 992         u64 mask;
 993
 994         switch (busno_to_phbid(busnum)) {
 995         case 0: phb_shift = (63 - 19);
 996                 break;
 997         case 1: phb_shift = (63 - 23);
 998                 break;
 999         case 2: phb_shift = (63 - 27);
1000                 break;
1001         case 3: phb_shift = (63 - 35);
1002                 break;
1003         default:
1004                 BUG_ON(busno_to_phbid(busnum));
1005         }
1006
1007         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
1008         val64 = be64_to_cpu(readq(target));
1009
1010         /* zero out this PHB's timer bits */
1011         mask = ~(0xFUL << phb_shift);
1012         val64 &= mask;
1013         val64 |= (timeout << phb_shift);
1014         writeq(cpu_to_be64(val64), target);
1015         readq(target); /* flush */
1016 }
1017
1018 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1019 {
1020         unsigned char busnum = dev->bus->number;
1021         void __iomem *bbar = tbl->bbar;
1022         void __iomem *target;
1023         u32 val;
1024
1025         /*
1026          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1027          */
1028         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1029         val = cpu_to_be32(readl(target));
1030         val |= 0x00800000;
1031         writel(cpu_to_be32(val), target);
1032 }
1033
1034 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1035 {
1036         unsigned char busnum = dev->bus->number;
1037
1038         /*
1039          * Give split completion a longer timeout on bus 1 for aic94xx
1040          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1041          */
1042         if (is_calgary(dev->device) && (busnum == 1))
1043                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1044                                                      CCR_2SEC_TIMEOUT);
1045 }
1046
1047 static void __init calgary_enable_translation(struct pci_dev *dev)
1048 {
1049         u32 val32;
1050         unsigned char busnum;
1051         void __iomem *target;
1052         void __iomem *bbar;
1053         struct iommu_table *tbl;
1054
1055         busnum = dev->bus->number;
1056         tbl = dev->sysdata;
1057         bbar = tbl->bbar;
1058
1059         /* enable TCE in PHB Config Register */
1060         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1061         val32 = be32_to_cpu(readl(target));
1062         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1063
1064         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1065                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1066                "Calgary" : "CalIOC2", busnum);
1067         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1068                "bus.\n");
1069
1070         writel(cpu_to_be32(val32), target);
1071         readl(target); /* flush */
1072
1073         init_timer(&tbl->watchdog_timer);
1074         tbl->watchdog_timer.function = &calgary_watchdog;
1075         tbl->watchdog_timer.data = (unsigned long)dev;
1076         mod_timer(&tbl->watchdog_timer, jiffies);
1077 }
1078
1079 static void __init calgary_disable_translation(struct pci_dev *dev)
1080 {
1081         u32 val32;
1082         unsigned char busnum;
1083         void __iomem *target;
1084         void __iomem *bbar;
1085         struct iommu_table *tbl;
1086
1087         busnum = dev->bus->number;
1088         tbl = dev->sysdata;
1089         bbar = tbl->bbar;
1090
1091         /* disable TCE in PHB Config Register */
1092         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1093         val32 = be32_to_cpu(readl(target));
1094         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1095
1096         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1097         writel(cpu_to_be32(val32), target);
1098         readl(target); /* flush */
1099
1100         del_timer_sync(&tbl->watchdog_timer);
1101 }
1102
1103 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1104 {
1105         pci_dev_get(dev);
1106         dev->sysdata = NULL;
1107
1108         /* is the device behind a bridge? */
1109         if (dev->bus->parent)
1110                 dev->bus->parent->self = dev;
1111         else
1112                 dev->bus->self = dev;
1113 }
1114
1115 static int __init calgary_init_one(struct pci_dev *dev)
1116 {
1117         void __iomem *bbar;
1118         struct iommu_table *tbl;
1119         int ret;
1120
1121         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1122
1123         bbar = busno_to_bbar(dev->bus->number);
1124         ret = calgary_setup_tar(dev, bbar);
1125         if (ret)
1126                 goto done;
1127
1128         pci_dev_get(dev);
1129
1130         if (dev->bus->parent) {
1131                 if (dev->bus->parent->self)
1132                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1133                                "bus->parent->self!\n", dev);
1134                 dev->bus->parent->self = dev;
1135         } else
1136                 dev->bus->self = dev;
1137
1138         tbl = dev->sysdata;
1139         tbl->chip_ops->handle_quirks(tbl, dev);
1140
1141         calgary_enable_translation(dev);
1142
1143         return 0;
1144
1145 done:
1146         return ret;
1147 }
1148
1149 static int __init calgary_locate_bbars(void)
1150 {
1151         int ret;
1152         int rioidx, phb, bus;
1153         void __iomem *bbar;
1154         void __iomem *target;
1155         unsigned long offset;
1156         u8 start_bus, end_bus;
1157         u32 val;
1158
1159         ret = -ENODATA;
1160         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1161                 struct rio_detail *rio = rio_devs[rioidx];
1162
1163                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1164                         continue;
1165
1166                 /* map entire 1MB of Calgary config space */
1167                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1168                 if (!bbar)
1169                         goto error;
1170
1171                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1172                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1173                         target = calgary_reg(bbar, offset);
1174
1175                         val = be32_to_cpu(readl(target));
1176
1177                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1178                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1179
1180                         if (end_bus) {
1181                                 for (bus = start_bus; bus <= end_bus; bus++) {
1182                                         bus_info[bus].bbar = bbar;
1183                                         bus_info[bus].phbid = phb;
1184                                 }
1185                         } else {
1186                                 bus_info[start_bus].bbar = bbar;
1187                                 bus_info[start_bus].phbid = phb;
1188                         }
1189                 }
1190         }
1191
1192         return 0;
1193
1194 error:
1195         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1196         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1197                 if (bus_info[bus].bbar)
1198                         iounmap(bus_info[bus].bbar);
1199
1200         return ret;
1201 }
1202
1203 static int __init calgary_init(void)
1204 {
1205         int ret;
1206         struct pci_dev *dev = NULL;
1207         void *tce_space;
1208
1209         ret = calgary_locate_bbars();
1210         if (ret)
1211                 return ret;
1212
1213         do {
1214                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1215                 if (!dev)
1216                         break;
1217                 if (!is_cal_pci_dev(dev->device))
1218                         continue;
1219                 if (!translate_phb(dev)) {
1220                         calgary_init_one_nontraslated(dev);
1221                         continue;
1222                 }
1223                 tce_space = bus_info[dev->bus->number].tce_space;
1224                 if (!tce_space && !translate_empty_slots)
1225                         continue;
1226
1227                 ret = calgary_init_one(dev);
1228                 if (ret)
1229                         goto error;
1230         } while (1);
1231
1232         return ret;
1233
1234 error:
1235         do {
1236                 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
1237                                              PCI_ANY_ID, dev);
1238                 if (!dev)
1239                         break;
1240                 if (!is_cal_pci_dev(dev->device))
1241                         continue;
1242                 if (!translate_phb(dev)) {
1243                         pci_dev_put(dev);
1244                         continue;
1245                 }
1246                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
1247                         continue;
1248
1249                 calgary_disable_translation(dev);
1250                 calgary_free_bus(dev);
1251                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1252         } while (1);
1253
1254         return ret;
1255 }
1256
1257 static inline int __init determine_tce_table_size(u64 ram)
1258 {
1259         int ret;
1260
1261         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1262                 return specified_table_size;
1263
1264         /*
1265          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1266          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1267          * larger table size has twice as many entries, so shift the
1268          * max ram address by 13 to divide by 8K and then look at the
1269          * order of the result to choose between 0-7.
1270          */
1271         ret = get_order(ram >> 13);
1272         if (ret > TCE_TABLE_SIZE_8M)
1273                 ret = TCE_TABLE_SIZE_8M;
1274
1275         return ret;
1276 }
1277
1278 static int __init build_detail_arrays(void)
1279 {
1280         unsigned long ptr;
1281         int i, scal_detail_size, rio_detail_size;
1282
1283         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1284                 printk(KERN_WARNING
1285                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1286                         "but system has %d nodes.\n",
1287                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1288                 return -ENODEV;
1289         }
1290
1291         switch (rio_table_hdr->version){
1292         case 2:
1293                 scal_detail_size = 11;
1294                 rio_detail_size = 13;
1295                 break;
1296         case 3:
1297                 scal_detail_size = 12;
1298                 rio_detail_size = 15;
1299                 break;
1300         default:
1301                 printk(KERN_WARNING
1302                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1303                        rio_table_hdr->version);
1304                 return -EPROTO;
1305         }
1306
1307         ptr = ((unsigned long)rio_table_hdr) + 3;
1308         for (i = 0; i < rio_table_hdr->num_scal_dev;
1309                     i++, ptr += scal_detail_size)
1310                 scal_devs[i] = (struct scal_detail *)ptr;
1311
1312         for (i = 0; i < rio_table_hdr->num_rio_dev;
1313                     i++, ptr += rio_detail_size)
1314                 rio_devs[i] = (struct rio_detail *)ptr;
1315
1316         return 0;
1317 }
1318
1319 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1320 {
1321         int dev;
1322         u32 val;
1323
1324         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1325                 /*
1326                  * FIXME: properly scan for devices accross the
1327                  * PCI-to-PCI bridge on every CalIOC2 port.
1328                  */
1329                 return 1;
1330         }
1331
1332         for (dev = 1; dev < 8; dev++) {
1333                 val = read_pci_config(bus, dev, 0, 0);
1334                 if (val != 0xffffffff)
1335                         break;
1336         }
1337         return (val != 0xffffffff);
1338 }
1339
1340 void __init detect_calgary(void)
1341 {
1342         int bus;
1343         void *tbl;
1344         int calgary_found = 0;
1345         unsigned long ptr;
1346         unsigned int offset, prev_offset;
1347         int ret;
1348
1349         /*
1350          * if the user specified iommu=off or iommu=soft or we found
1351          * another HW IOMMU already, bail out.
1352          */
1353         if (swiotlb || no_iommu || iommu_detected)
1354                 return;
1355
1356         if (!use_calgary)
1357                 return;
1358
1359         if (!early_pci_allowed())
1360                 return;
1361
1362         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1363
1364         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1365
1366         rio_table_hdr = NULL;
1367         prev_offset = 0;
1368         offset = 0x180;
1369         /*
1370          * The next offset is stored in the 1st word.
1371          * Only parse up until the offset increases:
1372          */
1373         while (offset > prev_offset) {
1374                 /* The block id is stored in the 2nd word */
1375                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1376                         /* set the pointer past the offset & block id */
1377                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1378                         break;
1379                 }
1380                 prev_offset = offset;
1381                 offset = *((unsigned short *)(ptr + offset));
1382         }
1383         if (!rio_table_hdr) {
1384                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1385                        "in EBDA - bailing!\n");
1386                 return;
1387         }
1388
1389         ret = build_detail_arrays();
1390         if (ret) {
1391                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1392                 return;
1393         }
1394
1395         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1396
1397         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1398                 struct calgary_bus_info *info = &bus_info[bus];
1399                 unsigned short pci_device;
1400                 u32 val;
1401
1402                 val = read_pci_config(bus, 0, 0, 0);
1403                 pci_device = (val & 0xFFFF0000) >> 16;
1404
1405                 if (!is_cal_pci_dev(pci_device))
1406                         continue;
1407
1408                 if (info->translation_disabled)
1409                         continue;
1410
1411                 if (calgary_bus_has_devices(bus, pci_device) ||
1412                     translate_empty_slots) {
1413                         tbl = alloc_tce_table();
1414                         if (!tbl)
1415                                 goto cleanup;
1416                         info->tce_space = tbl;
1417                         calgary_found = 1;
1418                 }
1419         }
1420
1421         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1422                calgary_found ? "found" : "not found");
1423
1424         if (calgary_found) {
1425                 iommu_detected = 1;
1426                 calgary_detected = 1;
1427                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1428                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1429                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1430                        debugging ? "enabled" : "disabled");
1431         }
1432         return;
1433
1434 cleanup:
1435         for (--bus; bus >= 0; --bus) {
1436                 struct calgary_bus_info *info = &bus_info[bus];
1437
1438                 if (info->tce_space)
1439                         free_tce_table(info->tce_space);
1440         }
1441 }
1442
1443 int __init calgary_iommu_init(void)
1444 {
1445         int ret;
1446
1447         if (no_iommu || swiotlb)
1448                 return -ENODEV;
1449
1450         if (!calgary_detected)
1451                 return -ENODEV;
1452
1453         /* ok, we're trying to use Calgary - let's roll */
1454         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1455
1456         ret = calgary_init();
1457         if (ret) {
1458                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1459                        "falling back to no_iommu\n", ret);
1460                 if (end_pfn > MAX_DMA32_PFN)
1461                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1462                                         "32bit PCI may malfunction.\n");
1463                 return ret;
1464         }
1465
1466         force_iommu = 1;
1467         bad_dma_address = 0x0;
1468         dma_ops = &calgary_dma_ops;
1469
1470         return 0;
1471 }
1472
1473 static int __init calgary_parse_options(char *p)
1474 {
1475         unsigned int bridge;
1476         size_t len;
1477         char* endp;
1478
1479         while (*p) {
1480                 if (!strncmp(p, "64k", 3))
1481                         specified_table_size = TCE_TABLE_SIZE_64K;
1482                 else if (!strncmp(p, "128k", 4))
1483                         specified_table_size = TCE_TABLE_SIZE_128K;
1484                 else if (!strncmp(p, "256k", 4))
1485                         specified_table_size = TCE_TABLE_SIZE_256K;
1486                 else if (!strncmp(p, "512k", 4))
1487                         specified_table_size = TCE_TABLE_SIZE_512K;
1488                 else if (!strncmp(p, "1M", 2))
1489                         specified_table_size = TCE_TABLE_SIZE_1M;
1490                 else if (!strncmp(p, "2M", 2))
1491                         specified_table_size = TCE_TABLE_SIZE_2M;
1492                 else if (!strncmp(p, "4M", 2))
1493                         specified_table_size = TCE_TABLE_SIZE_4M;
1494                 else if (!strncmp(p, "8M", 2))
1495                         specified_table_size = TCE_TABLE_SIZE_8M;
1496
1497                 len = strlen("translate_empty_slots");
1498                 if (!strncmp(p, "translate_empty_slots", len))
1499                         translate_empty_slots = 1;
1500
1501                 len = strlen("disable");
1502                 if (!strncmp(p, "disable", len)) {
1503                         p += len;
1504                         if (*p == '=')
1505                                 ++p;
1506                         if (*p == '\0')
1507                                 break;
1508                         bridge = simple_strtol(p, &endp, 0);
1509                         if (p == endp)
1510                                 break;
1511
1512                         if (bridge < MAX_PHB_BUS_NUM) {
1513                                 printk(KERN_INFO "Calgary: disabling "
1514                                        "translation for PHB %#x\n", bridge);
1515                                 bus_info[bridge].translation_disabled = 1;
1516                         }
1517                 }
1518
1519                 p = strpbrk(p, ",");
1520                 if (!p)
1521                         break;
1522
1523                 p++; /* skip ',' */
1524         }
1525         return 1;
1526 }
1527 __setup("calgary=", calgary_parse_options);
1528
1529 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1530 {
1531         struct iommu_table *tbl;
1532         unsigned int npages;
1533         int i;
1534
1535         tbl = dev->sysdata;
1536
1537         for (i = 0; i < 4; i++) {
1538                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1539
1540                 /* Don't give out TCEs that map MEM resources */
1541                 if (!(r->flags & IORESOURCE_MEM))
1542                         continue;
1543
1544                 /* 0-based? we reserve the whole 1st MB anyway */
1545                 if (!r->start)
1546                         continue;
1547
1548                 /* cover the whole region */
1549                 npages = (r->end - r->start) >> PAGE_SHIFT;
1550                 npages++;
1551
1552                 iommu_range_reserve(tbl, r->start, npages);
1553         }
1554 }
1555
1556 static int __init calgary_fixup_tce_spaces(void)
1557 {
1558         struct pci_dev *dev = NULL;
1559         void *tce_space;
1560
1561         if (no_iommu || swiotlb || !calgary_detected)
1562                 return -ENODEV;
1563
1564         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1565
1566         do {
1567                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1568                 if (!dev)
1569                         break;
1570                 if (!is_cal_pci_dev(dev->device))
1571                         continue;
1572                 if (!translate_phb(dev))
1573                         continue;
1574
1575                 tce_space = bus_info[dev->bus->number].tce_space;
1576                 if (!tce_space)
1577                         continue;
1578
1579                 calgary_fixup_one_tce_space(dev);
1580
1581         } while (1);
1582
1583         return 0;
1584 }
1585
1586 /*
1587  * We need to be call after pcibios_assign_resources (fs_initcall level)
1588  * and before device_initcall.
1589  */
1590 rootfs_initcall(calgary_fixup_tce_spaces);