2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "3.0"
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
102 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
121 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
149 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
151 PORT_IRQ_HBUS_DATA_ERR,
152 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
153 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
154 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
157 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
158 PORT_CMD_PMP = (1 << 17), /* PMP attached */
159 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
160 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
161 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
162 PORT_CMD_CLO = (1 << 3), /* Command list override */
163 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
164 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
165 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
167 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
168 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
169 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
170 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
173 AHCI_FLAG_NO_NCQ = (1 << 24),
174 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
175 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
176 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
177 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
178 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
179 AHCI_FLAG_NO_HOTPLUG = (1 << 31), /* ignore PxSERR.DIAG.N */
181 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
182 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
183 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
184 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
187 struct ahci_cmd_hdr {
202 struct ahci_host_priv {
203 u32 cap; /* cap to use */
204 u32 port_map; /* port map to use */
205 u32 saved_cap; /* saved initial cap */
206 u32 saved_port_map; /* saved initial port_map */
209 struct ahci_port_priv {
210 struct ata_link *active_link;
211 struct ahci_cmd_hdr *cmd_slot;
212 dma_addr_t cmd_slot_dma;
214 dma_addr_t cmd_tbl_dma;
216 dma_addr_t rx_fis_dma;
217 /* for NCQ spurious interrupt analysis */
218 unsigned int ncq_saw_d2h:1;
219 unsigned int ncq_saw_dmas:1;
220 unsigned int ncq_saw_sdb:1;
221 u32 intr_mask; /* interrupts to enable */
224 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
225 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
226 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
227 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
228 static void ahci_irq_clear(struct ata_port *ap);
229 static int ahci_port_start(struct ata_port *ap);
230 static void ahci_port_stop(struct ata_port *ap);
231 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
232 static void ahci_qc_prep(struct ata_queued_cmd *qc);
233 static u8 ahci_check_status(struct ata_port *ap);
234 static void ahci_freeze(struct ata_port *ap);
235 static void ahci_thaw(struct ata_port *ap);
236 static void ahci_pmp_attach(struct ata_port *ap);
237 static void ahci_pmp_detach(struct ata_port *ap);
238 static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val);
239 static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val);
240 static void ahci_error_handler(struct ata_port *ap);
241 static void ahci_vt8251_error_handler(struct ata_port *ap);
242 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
243 static int ahci_port_resume(struct ata_port *ap);
244 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
245 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
248 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
249 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
250 static int ahci_pci_device_resume(struct pci_dev *pdev);
253 static struct scsi_host_template ahci_sht = {
254 .module = THIS_MODULE,
256 .ioctl = ata_scsi_ioctl,
257 .queuecommand = ata_scsi_queuecmd,
258 .change_queue_depth = ata_scsi_change_queue_depth,
259 .can_queue = AHCI_MAX_CMDS - 1,
260 .this_id = ATA_SHT_THIS_ID,
261 .sg_tablesize = AHCI_MAX_SG,
262 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
263 .emulated = ATA_SHT_EMULATED,
264 .use_clustering = AHCI_USE_CLUSTERING,
265 .proc_name = DRV_NAME,
266 .dma_boundary = AHCI_DMA_BOUNDARY,
267 .slave_configure = ata_scsi_slave_config,
268 .slave_destroy = ata_scsi_slave_destroy,
269 .bios_param = ata_std_bios_param,
272 static const struct ata_port_operations ahci_ops = {
273 .check_status = ahci_check_status,
274 .check_altstatus = ahci_check_status,
275 .dev_select = ata_noop_dev_select,
277 .tf_read = ahci_tf_read,
279 .qc_defer = sata_pmp_qc_defer_cmd_switch,
280 .qc_prep = ahci_qc_prep,
281 .qc_issue = ahci_qc_issue,
283 .irq_clear = ahci_irq_clear,
285 .scr_read = ahci_scr_read,
286 .scr_write = ahci_scr_write,
288 .freeze = ahci_freeze,
291 .error_handler = ahci_error_handler,
292 .post_internal_cmd = ahci_post_internal_cmd,
294 .pmp_attach = ahci_pmp_attach,
295 .pmp_detach = ahci_pmp_detach,
296 .pmp_read = ahci_pmp_read,
297 .pmp_write = ahci_pmp_write,
300 .port_suspend = ahci_port_suspend,
301 .port_resume = ahci_port_resume,
304 .port_start = ahci_port_start,
305 .port_stop = ahci_port_stop,
308 static const struct ata_port_operations ahci_vt8251_ops = {
309 .check_status = ahci_check_status,
310 .check_altstatus = ahci_check_status,
311 .dev_select = ata_noop_dev_select,
313 .tf_read = ahci_tf_read,
315 .qc_defer = sata_pmp_qc_defer_cmd_switch,
316 .qc_prep = ahci_qc_prep,
317 .qc_issue = ahci_qc_issue,
319 .irq_clear = ahci_irq_clear,
321 .scr_read = ahci_scr_read,
322 .scr_write = ahci_scr_write,
324 .freeze = ahci_freeze,
327 .error_handler = ahci_vt8251_error_handler,
328 .post_internal_cmd = ahci_post_internal_cmd,
330 .pmp_attach = ahci_pmp_attach,
331 .pmp_detach = ahci_pmp_detach,
332 .pmp_read = ahci_pmp_read,
333 .pmp_write = ahci_pmp_write,
336 .port_suspend = ahci_port_suspend,
337 .port_resume = ahci_port_resume,
340 .port_start = ahci_port_start,
341 .port_stop = ahci_port_stop,
344 static const struct ata_port_info ahci_port_info[] = {
347 .flags = AHCI_FLAG_COMMON,
348 .link_flags = AHCI_LFLAG_COMMON,
349 .pio_mask = 0x1f, /* pio0-4 */
350 .udma_mask = ATA_UDMA6,
351 .port_ops = &ahci_ops,
353 /* board_ahci_vt8251 */
355 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_NO_NCQ,
356 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
357 .pio_mask = 0x1f, /* pio0-4 */
358 .udma_mask = ATA_UDMA6,
359 .port_ops = &ahci_vt8251_ops,
361 /* board_ahci_ign_iferr */
363 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
364 .link_flags = AHCI_LFLAG_COMMON,
365 .pio_mask = 0x1f, /* pio0-4 */
366 .udma_mask = ATA_UDMA6,
367 .port_ops = &ahci_ops,
369 /* board_ahci_sb600 */
371 .flags = AHCI_FLAG_COMMON |
372 AHCI_FLAG_IGN_SERR_INTERNAL |
373 AHCI_FLAG_32BIT_ONLY,
374 .link_flags = AHCI_LFLAG_COMMON,
375 .pio_mask = 0x1f, /* pio0-4 */
376 .udma_mask = ATA_UDMA6,
377 .port_ops = &ahci_ops,
382 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
383 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
384 AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
386 .link_flags = AHCI_LFLAG_COMMON,
387 .pio_mask = 0x1f, /* pio0-4 */
388 .udma_mask = ATA_UDMA6,
389 .port_ops = &ahci_ops,
393 static const struct pci_device_id ahci_pci_tbl[] = {
395 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
396 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
397 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
398 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
399 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
400 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
401 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
402 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
403 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
404 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
405 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
406 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
407 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
408 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
409 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
410 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
411 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
412 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
413 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
414 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
415 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
416 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
417 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
418 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
419 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
420 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
421 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
422 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
423 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
425 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
426 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
427 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
430 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
431 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
436 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
439 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
440 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
443 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
444 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
445 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
446 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
447 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
454 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
455 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
489 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
490 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
491 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
494 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
496 /* Generic, PCI class code for AHCI */
497 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
498 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
500 { } /* terminate list */
504 static struct pci_driver ahci_pci_driver = {
506 .id_table = ahci_pci_tbl,
507 .probe = ahci_init_one,
508 .remove = ata_pci_remove_one,
510 .suspend = ahci_pci_device_suspend,
511 .resume = ahci_pci_device_resume,
516 static inline int ahci_nr_ports(u32 cap)
518 return (cap & 0x1f) + 1;
521 static inline void __iomem *__ahci_port_base(struct ata_host *host,
522 unsigned int port_no)
524 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
526 return mmio + 0x100 + (port_no * 0x80);
529 static inline void __iomem *ahci_port_base(struct ata_port *ap)
531 return __ahci_port_base(ap->host, ap->port_no);
535 * ahci_save_initial_config - Save and fixup initial config values
536 * @pdev: target PCI device
537 * @pi: associated ATA port info
538 * @hpriv: host private area to store config values
540 * Some registers containing configuration info might be setup by
541 * BIOS and might be cleared on reset. This function saves the
542 * initial values of those registers into @hpriv such that they
543 * can be restored after controller reset.
545 * If inconsistent, config values are fixed up by this function.
550 static void ahci_save_initial_config(struct pci_dev *pdev,
551 const struct ata_port_info *pi,
552 struct ahci_host_priv *hpriv)
554 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
558 /* Values prefixed with saved_ are written back to host after
559 * reset. Values without are used for driver operation.
561 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
562 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
564 /* some chips have errata preventing 64bit use */
565 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
566 dev_printk(KERN_INFO, &pdev->dev,
567 "controller can't do 64bit DMA, forcing 32bit\n");
571 if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) {
572 dev_printk(KERN_INFO, &pdev->dev,
573 "controller can't do NCQ, turning off CAP_NCQ\n");
574 cap &= ~HOST_CAP_NCQ;
578 * Temporary Marvell 6145 hack: PATA port presence
579 * is asserted through the standard AHCI port
580 * presence register, as bit 4 (counting from 0)
582 if (pi->flags & AHCI_FLAG_MV_PATA) {
583 dev_printk(KERN_ERR, &pdev->dev,
584 "MV_AHCI HACK: port_map %x -> %x\n",
586 hpriv->port_map & 0xf);
591 /* cross check port_map and cap.n_ports */
593 u32 tmp_port_map = port_map;
594 int n_ports = ahci_nr_ports(cap);
596 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
597 if (tmp_port_map & (1 << i)) {
599 tmp_port_map &= ~(1 << i);
603 /* If n_ports and port_map are inconsistent, whine and
604 * clear port_map and let it be generated from n_ports.
606 if (n_ports || tmp_port_map) {
607 dev_printk(KERN_WARNING, &pdev->dev,
608 "nr_ports (%u) and implemented port map "
609 "(0x%x) don't match, using nr_ports\n",
610 ahci_nr_ports(cap), port_map);
615 /* fabricate port_map from cap.nr_ports */
617 port_map = (1 << ahci_nr_ports(cap)) - 1;
618 dev_printk(KERN_WARNING, &pdev->dev,
619 "forcing PORTS_IMPL to 0x%x\n", port_map);
621 /* write the fixed up value to the PI register */
622 hpriv->saved_port_map = port_map;
625 /* record values to use during operation */
627 hpriv->port_map = port_map;
631 * ahci_restore_initial_config - Restore initial config
632 * @host: target ATA host
634 * Restore initial config stored by ahci_save_initial_config().
639 static void ahci_restore_initial_config(struct ata_host *host)
641 struct ahci_host_priv *hpriv = host->private_data;
642 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
644 writel(hpriv->saved_cap, mmio + HOST_CAP);
645 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
646 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
649 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
651 static const int offset[] = {
652 [SCR_STATUS] = PORT_SCR_STAT,
653 [SCR_CONTROL] = PORT_SCR_CTL,
654 [SCR_ERROR] = PORT_SCR_ERR,
655 [SCR_ACTIVE] = PORT_SCR_ACT,
656 [SCR_NOTIFICATION] = PORT_SCR_NTF,
658 struct ahci_host_priv *hpriv = ap->host->private_data;
660 if (sc_reg < ARRAY_SIZE(offset) &&
661 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
662 return offset[sc_reg];
666 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
668 void __iomem *port_mmio = ahci_port_base(ap);
669 int offset = ahci_scr_offset(ap, sc_reg);
672 *val = readl(port_mmio + offset);
678 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
680 void __iomem *port_mmio = ahci_port_base(ap);
681 int offset = ahci_scr_offset(ap, sc_reg);
684 writel(val, port_mmio + offset);
690 static void ahci_start_engine(struct ata_port *ap)
692 void __iomem *port_mmio = ahci_port_base(ap);
696 tmp = readl(port_mmio + PORT_CMD);
697 tmp |= PORT_CMD_START;
698 writel(tmp, port_mmio + PORT_CMD);
699 readl(port_mmio + PORT_CMD); /* flush */
702 static int ahci_stop_engine(struct ata_port *ap)
704 void __iomem *port_mmio = ahci_port_base(ap);
707 tmp = readl(port_mmio + PORT_CMD);
709 /* check if the HBA is idle */
710 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
713 /* setting HBA to idle */
714 tmp &= ~PORT_CMD_START;
715 writel(tmp, port_mmio + PORT_CMD);
717 /* wait for engine to stop. This could be as long as 500 msec */
718 tmp = ata_wait_register(port_mmio + PORT_CMD,
719 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
720 if (tmp & PORT_CMD_LIST_ON)
726 static void ahci_start_fis_rx(struct ata_port *ap)
728 void __iomem *port_mmio = ahci_port_base(ap);
729 struct ahci_host_priv *hpriv = ap->host->private_data;
730 struct ahci_port_priv *pp = ap->private_data;
733 /* set FIS registers */
734 if (hpriv->cap & HOST_CAP_64)
735 writel((pp->cmd_slot_dma >> 16) >> 16,
736 port_mmio + PORT_LST_ADDR_HI);
737 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
739 if (hpriv->cap & HOST_CAP_64)
740 writel((pp->rx_fis_dma >> 16) >> 16,
741 port_mmio + PORT_FIS_ADDR_HI);
742 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
744 /* enable FIS reception */
745 tmp = readl(port_mmio + PORT_CMD);
746 tmp |= PORT_CMD_FIS_RX;
747 writel(tmp, port_mmio + PORT_CMD);
750 readl(port_mmio + PORT_CMD);
753 static int ahci_stop_fis_rx(struct ata_port *ap)
755 void __iomem *port_mmio = ahci_port_base(ap);
758 /* disable FIS reception */
759 tmp = readl(port_mmio + PORT_CMD);
760 tmp &= ~PORT_CMD_FIS_RX;
761 writel(tmp, port_mmio + PORT_CMD);
763 /* wait for completion, spec says 500ms, give it 1000 */
764 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
765 PORT_CMD_FIS_ON, 10, 1000);
766 if (tmp & PORT_CMD_FIS_ON)
772 static void ahci_power_up(struct ata_port *ap)
774 struct ahci_host_priv *hpriv = ap->host->private_data;
775 void __iomem *port_mmio = ahci_port_base(ap);
778 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
781 if (hpriv->cap & HOST_CAP_SSS) {
782 cmd |= PORT_CMD_SPIN_UP;
783 writel(cmd, port_mmio + PORT_CMD);
787 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
791 static void ahci_power_down(struct ata_port *ap)
793 struct ahci_host_priv *hpriv = ap->host->private_data;
794 void __iomem *port_mmio = ahci_port_base(ap);
797 if (!(hpriv->cap & HOST_CAP_SSS))
800 /* put device into listen mode, first set PxSCTL.DET to 0 */
801 scontrol = readl(port_mmio + PORT_SCR_CTL);
803 writel(scontrol, port_mmio + PORT_SCR_CTL);
805 /* then set PxCMD.SUD to 0 */
806 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
807 cmd &= ~PORT_CMD_SPIN_UP;
808 writel(cmd, port_mmio + PORT_CMD);
812 static void ahci_start_port(struct ata_port *ap)
814 /* enable FIS reception */
815 ahci_start_fis_rx(ap);
818 ahci_start_engine(ap);
821 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
826 rc = ahci_stop_engine(ap);
828 *emsg = "failed to stop engine";
832 /* disable FIS reception */
833 rc = ahci_stop_fis_rx(ap);
835 *emsg = "failed stop FIS RX";
842 static int ahci_reset_controller(struct ata_host *host)
844 struct pci_dev *pdev = to_pci_dev(host->dev);
845 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
848 /* we must be in AHCI mode, before using anything
849 * AHCI-specific, such as HOST_RESET.
851 tmp = readl(mmio + HOST_CTL);
852 if (!(tmp & HOST_AHCI_EN))
853 writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
855 /* global controller reset */
856 if ((tmp & HOST_RESET) == 0) {
857 writel(tmp | HOST_RESET, mmio + HOST_CTL);
858 readl(mmio + HOST_CTL); /* flush */
861 /* reset must complete within 1 second, or
862 * the hardware should be considered fried.
866 tmp = readl(mmio + HOST_CTL);
867 if (tmp & HOST_RESET) {
868 dev_printk(KERN_ERR, host->dev,
869 "controller reset failed (0x%x)\n", tmp);
873 /* turn on AHCI mode */
874 writel(HOST_AHCI_EN, mmio + HOST_CTL);
875 (void) readl(mmio + HOST_CTL); /* flush */
877 /* some registers might be cleared on reset. restore initial values */
878 ahci_restore_initial_config(host);
880 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
884 pci_read_config_word(pdev, 0x92, &tmp16);
886 pci_write_config_word(pdev, 0x92, tmp16);
892 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
893 int port_no, void __iomem *mmio,
894 void __iomem *port_mmio)
896 const char *emsg = NULL;
900 /* make sure port is not active */
901 rc = ahci_deinit_port(ap, &emsg);
903 dev_printk(KERN_WARNING, &pdev->dev,
904 "%s (%d)\n", emsg, rc);
907 tmp = readl(port_mmio + PORT_SCR_ERR);
908 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
909 writel(tmp, port_mmio + PORT_SCR_ERR);
912 tmp = readl(port_mmio + PORT_IRQ_STAT);
913 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
915 writel(tmp, port_mmio + PORT_IRQ_STAT);
917 writel(1 << port_no, mmio + HOST_IRQ_STAT);
920 static void ahci_init_controller(struct ata_host *host)
922 struct pci_dev *pdev = to_pci_dev(host->dev);
923 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
925 void __iomem *port_mmio;
928 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
929 port_mmio = __ahci_port_base(host, 4);
931 writel(0, port_mmio + PORT_IRQ_MASK);
934 tmp = readl(port_mmio + PORT_IRQ_STAT);
935 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
937 writel(tmp, port_mmio + PORT_IRQ_STAT);
940 for (i = 0; i < host->n_ports; i++) {
941 struct ata_port *ap = host->ports[i];
943 port_mmio = ahci_port_base(ap);
944 if (ata_port_is_dummy(ap))
947 ahci_port_init(pdev, ap, i, mmio, port_mmio);
950 tmp = readl(mmio + HOST_CTL);
951 VPRINTK("HOST_CTL 0x%x\n", tmp);
952 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
953 tmp = readl(mmio + HOST_CTL);
954 VPRINTK("HOST_CTL 0x%x\n", tmp);
957 static unsigned int ahci_dev_classify(struct ata_port *ap)
959 void __iomem *port_mmio = ahci_port_base(ap);
960 struct ata_taskfile tf;
963 tmp = readl(port_mmio + PORT_SIG);
964 tf.lbah = (tmp >> 24) & 0xff;
965 tf.lbam = (tmp >> 16) & 0xff;
966 tf.lbal = (tmp >> 8) & 0xff;
967 tf.nsect = (tmp) & 0xff;
969 return ata_dev_classify(&tf);
972 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
975 dma_addr_t cmd_tbl_dma;
977 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
979 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
980 pp->cmd_slot[tag].status = 0;
981 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
982 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
985 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
987 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
988 struct ahci_host_priv *hpriv = ap->host->private_data;
992 /* do we need to kick the port? */
993 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
994 if (!busy && !force_restart)
998 rc = ahci_stop_engine(ap);
1002 /* need to do CLO? */
1008 if (!(hpriv->cap & HOST_CAP_CLO)) {
1014 tmp = readl(port_mmio + PORT_CMD);
1015 tmp |= PORT_CMD_CLO;
1016 writel(tmp, port_mmio + PORT_CMD);
1019 tmp = ata_wait_register(port_mmio + PORT_CMD,
1020 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1021 if (tmp & PORT_CMD_CLO)
1024 /* restart engine */
1026 ahci_start_engine(ap);
1030 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1031 struct ata_taskfile *tf, int is_cmd, u16 flags,
1032 unsigned long timeout_msec)
1034 const u32 cmd_fis_len = 5; /* five dwords */
1035 struct ahci_port_priv *pp = ap->private_data;
1036 void __iomem *port_mmio = ahci_port_base(ap);
1037 u8 *fis = pp->cmd_tbl;
1040 /* prep the command */
1041 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1042 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1045 writel(1, port_mmio + PORT_CMD_ISSUE);
1048 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1051 ahci_kick_engine(ap, 1);
1055 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1060 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1061 int pmp, unsigned long deadline)
1063 struct ata_port *ap = link->ap;
1064 const char *reason = NULL;
1065 unsigned long now, msecs;
1066 struct ata_taskfile tf;
1071 if (ata_link_offline(link)) {
1072 DPRINTK("PHY reports no device\n");
1073 *class = ATA_DEV_NONE;
1077 /* prepare for SRST (AHCI-1.1 10.4.1) */
1078 rc = ahci_kick_engine(ap, 1);
1080 ata_link_printk(link, KERN_WARNING,
1081 "failed to reset engine (errno=%d)", rc);
1083 ata_tf_init(link->device, &tf);
1085 /* issue the first D2H Register FIS */
1088 if (time_after(now, deadline))
1089 msecs = jiffies_to_msecs(deadline - now);
1092 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1093 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1095 reason = "1st FIS failed";
1099 /* spec says at least 5us, but be generous and sleep for 1ms */
1102 /* issue the second D2H Register FIS */
1103 tf.ctl &= ~ATA_SRST;
1104 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1106 /* spec mandates ">= 2ms" before checking status.
1107 * We wait 150ms, because that was the magic delay used for
1108 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1109 * between when the ATA command register is written, and then
1110 * status is checked. Because waiting for "a while" before
1111 * checking status is fine, post SRST, we perform this magic
1112 * delay here as well.
1116 rc = ata_wait_ready(ap, deadline);
1117 /* link occupied, -ENODEV too is an error */
1119 reason = "device not ready";
1122 *class = ahci_dev_classify(ap);
1124 DPRINTK("EXIT, class=%u\n", *class);
1128 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1132 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1133 unsigned long deadline)
1137 if (link->ap->flags & ATA_FLAG_PMP)
1138 pmp = SATA_PMP_CTRL_PORT;
1140 return ahci_do_softreset(link, class, pmp, deadline);
1143 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1144 unsigned long deadline)
1146 struct ata_port *ap = link->ap;
1147 struct ahci_port_priv *pp = ap->private_data;
1148 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1149 struct ata_taskfile tf;
1154 ahci_stop_engine(ap);
1156 /* clear D2H reception area to properly wait for D2H FIS */
1157 ata_tf_init(link->device, &tf);
1159 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1161 rc = sata_std_hardreset(link, class, deadline);
1163 ahci_start_engine(ap);
1165 if (rc == 0 && ata_link_online(link))
1166 *class = ahci_dev_classify(ap);
1167 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1168 *class = ATA_DEV_NONE;
1170 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1174 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1175 unsigned long deadline)
1177 struct ata_port *ap = link->ap;
1183 ahci_stop_engine(ap);
1185 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1188 /* vt8251 needs SError cleared for the port to operate */
1189 ahci_scr_read(ap, SCR_ERROR, &serror);
1190 ahci_scr_write(ap, SCR_ERROR, serror);
1192 ahci_start_engine(ap);
1194 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1196 /* vt8251 doesn't clear BSY on signature FIS reception,
1197 * request follow-up softreset.
1199 return rc ?: -EAGAIN;
1202 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1204 struct ata_port *ap = link->ap;
1205 void __iomem *port_mmio = ahci_port_base(ap);
1208 ata_std_postreset(link, class);
1210 /* Make sure port's ATAPI bit is set appropriately */
1211 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1212 if (*class == ATA_DEV_ATAPI)
1213 new_tmp |= PORT_CMD_ATAPI;
1215 new_tmp &= ~PORT_CMD_ATAPI;
1216 if (new_tmp != tmp) {
1217 writel(new_tmp, port_mmio + PORT_CMD);
1218 readl(port_mmio + PORT_CMD); /* flush */
1222 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1223 unsigned long deadline)
1225 return ahci_do_softreset(link, class, link->pmp, deadline);
1228 static u8 ahci_check_status(struct ata_port *ap)
1230 void __iomem *mmio = ap->ioaddr.cmd_addr;
1232 return readl(mmio + PORT_TFDATA) & 0xFF;
1235 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1237 struct ahci_port_priv *pp = ap->private_data;
1238 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1240 ata_tf_from_fis(d2h_fis, tf);
1243 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1245 struct scatterlist *sg;
1246 struct ahci_sg *ahci_sg;
1247 unsigned int n_sg = 0;
1252 * Next, the S/G list.
1254 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1255 ata_for_each_sg(sg, qc) {
1256 dma_addr_t addr = sg_dma_address(sg);
1257 u32 sg_len = sg_dma_len(sg);
1259 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1260 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1261 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1270 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1272 struct ata_port *ap = qc->ap;
1273 struct ahci_port_priv *pp = ap->private_data;
1274 int is_atapi = is_atapi_taskfile(&qc->tf);
1277 const u32 cmd_fis_len = 5; /* five dwords */
1278 unsigned int n_elem;
1281 * Fill in command table information. First, the header,
1282 * a SATA Register - Host to Device command FIS.
1284 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1286 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1288 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1289 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1293 if (qc->flags & ATA_QCFLAG_DMAMAP)
1294 n_elem = ahci_fill_sg(qc, cmd_tbl);
1297 * Fill in command slot information.
1299 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1300 if (qc->tf.flags & ATA_TFLAG_WRITE)
1301 opts |= AHCI_CMD_WRITE;
1303 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1305 ahci_fill_cmd_slot(pp, qc->tag, opts);
1308 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1310 struct ahci_port_priv *pp = ap->private_data;
1311 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1312 struct ata_link *link = NULL;
1313 struct ata_queued_cmd *active_qc;
1314 struct ata_eh_info *active_ehi;
1317 /* determine active link */
1318 ata_port_for_each_link(link, ap)
1319 if (ata_link_active(link))
1324 active_qc = ata_qc_from_tag(ap, link->active_tag);
1325 active_ehi = &link->eh_info;
1327 /* record irq stat */
1328 ata_ehi_clear_desc(host_ehi);
1329 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1331 /* AHCI needs SError cleared; otherwise, it might lock up */
1332 ahci_scr_read(ap, SCR_ERROR, &serror);
1333 ahci_scr_write(ap, SCR_ERROR, serror);
1334 host_ehi->serror |= serror;
1336 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1337 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1338 irq_stat &= ~PORT_IRQ_IF_ERR;
1340 if (irq_stat & PORT_IRQ_TF_ERR) {
1341 /* If qc is active, charge it; otherwise, the active
1342 * link. There's no active qc on NCQ errors. It will
1343 * be determined by EH by reading log page 10h.
1346 active_qc->err_mask |= AC_ERR_DEV;
1348 active_ehi->err_mask |= AC_ERR_DEV;
1350 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1351 host_ehi->serror &= ~SERR_INTERNAL;
1354 if (irq_stat & PORT_IRQ_UNK_FIS) {
1355 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1357 active_ehi->err_mask |= AC_ERR_HSM;
1358 active_ehi->action |= ATA_EH_SOFTRESET;
1359 ata_ehi_push_desc(active_ehi,
1360 "unknown FIS %08x %08x %08x %08x" ,
1361 unk[0], unk[1], unk[2], unk[3]);
1364 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1365 active_ehi->err_mask |= AC_ERR_HSM;
1366 active_ehi->action |= ATA_EH_SOFTRESET;
1367 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1370 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1371 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1372 host_ehi->action |= ATA_EH_SOFTRESET;
1373 ata_ehi_push_desc(host_ehi, "host bus error");
1376 if (irq_stat & PORT_IRQ_IF_ERR) {
1377 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1378 host_ehi->action |= ATA_EH_SOFTRESET;
1379 ata_ehi_push_desc(host_ehi, "interface fatal error");
1382 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1383 ata_ehi_hotplugged(host_ehi);
1384 ata_ehi_push_desc(host_ehi, "%s",
1385 irq_stat & PORT_IRQ_CONNECT ?
1386 "connection status changed" : "PHY RDY changed");
1389 /* okay, let's hand over to EH */
1391 if (irq_stat & PORT_IRQ_FREEZE)
1392 ata_port_freeze(ap);
1397 static void ahci_port_intr(struct ata_port *ap)
1399 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1400 struct ata_eh_info *ehi = &ap->link.eh_info;
1401 struct ahci_port_priv *pp = ap->private_data;
1402 u32 status, qc_active;
1403 int rc, known_irq = 0;
1405 status = readl(port_mmio + PORT_IRQ_STAT);
1406 writel(status, port_mmio + PORT_IRQ_STAT);
1408 if (unlikely(status & PORT_IRQ_ERROR)) {
1409 ahci_error_intr(ap, status);
1413 if (status & PORT_IRQ_SDB_FIS) {
1414 /* If the 'N' bit in word 0 of the FIS is set, we just
1415 * received asynchronous notification. Tell libata
1416 * about it. Note that as the SDB FIS itself is
1417 * accessible, SNotification can be emulated by the
1418 * driver but don't bother for the time being.
1420 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1421 u32 f0 = le32_to_cpu(f[0]);
1424 sata_async_notification(ap);
1427 /* pp->active_link is valid iff any command is in flight */
1428 if (ap->qc_active && pp->active_link->sactive)
1429 qc_active = readl(port_mmio + PORT_SCR_ACT);
1431 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1433 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1437 ehi->err_mask |= AC_ERR_HSM;
1438 ehi->action |= ATA_EH_SOFTRESET;
1439 ata_port_freeze(ap);
1443 /* hmmm... a spurious interupt */
1445 /* if !NCQ, ignore. No modern ATA device has broken HSM
1446 * implementation for non-NCQ commands.
1448 if (!ap->link.sactive)
1451 if (status & PORT_IRQ_D2H_REG_FIS) {
1452 if (!pp->ncq_saw_d2h)
1453 ata_port_printk(ap, KERN_INFO,
1454 "D2H reg with I during NCQ, "
1455 "this message won't be printed again\n");
1456 pp->ncq_saw_d2h = 1;
1460 if (status & PORT_IRQ_DMAS_FIS) {
1461 if (!pp->ncq_saw_dmas)
1462 ata_port_printk(ap, KERN_INFO,
1463 "DMAS FIS during NCQ, "
1464 "this message won't be printed again\n");
1465 pp->ncq_saw_dmas = 1;
1469 if (status & PORT_IRQ_SDB_FIS) {
1470 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1472 if (le32_to_cpu(f[1])) {
1473 /* SDB FIS containing spurious completions
1474 * might be dangerous, whine and fail commands
1475 * with HSM violation. EH will turn off NCQ
1476 * after several such failures.
1478 ata_ehi_push_desc(ehi,
1479 "spurious completions during NCQ "
1480 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1481 readl(port_mmio + PORT_CMD_ISSUE),
1482 readl(port_mmio + PORT_SCR_ACT),
1483 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1484 ehi->err_mask |= AC_ERR_HSM;
1485 ehi->action |= ATA_EH_SOFTRESET;
1486 ata_port_freeze(ap);
1488 if (!pp->ncq_saw_sdb)
1489 ata_port_printk(ap, KERN_INFO,
1490 "spurious SDB FIS %08x:%08x during NCQ, "
1491 "this message won't be printed again\n",
1492 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1493 pp->ncq_saw_sdb = 1;
1499 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1500 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1501 status, ap->link.active_tag, ap->link.sactive);
1504 static void ahci_irq_clear(struct ata_port *ap)
1509 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1511 struct ata_host *host = dev_instance;
1512 struct ahci_host_priv *hpriv;
1513 unsigned int i, handled = 0;
1515 u32 irq_stat, irq_ack = 0;
1519 hpriv = host->private_data;
1520 mmio = host->iomap[AHCI_PCI_BAR];
1522 /* sigh. 0xffffffff is a valid return from h/w */
1523 irq_stat = readl(mmio + HOST_IRQ_STAT);
1524 irq_stat &= hpriv->port_map;
1528 spin_lock(&host->lock);
1530 for (i = 0; i < host->n_ports; i++) {
1531 struct ata_port *ap;
1533 if (!(irq_stat & (1 << i)))
1536 ap = host->ports[i];
1539 VPRINTK("port %u\n", i);
1541 VPRINTK("port %u (no irq)\n", i);
1542 if (ata_ratelimit())
1543 dev_printk(KERN_WARNING, host->dev,
1544 "interrupt on disabled port %u\n", i);
1547 irq_ack |= (1 << i);
1551 writel(irq_ack, mmio + HOST_IRQ_STAT);
1555 spin_unlock(&host->lock);
1559 return IRQ_RETVAL(handled);
1562 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1564 struct ata_port *ap = qc->ap;
1565 void __iomem *port_mmio = ahci_port_base(ap);
1566 struct ahci_port_priv *pp = ap->private_data;
1568 /* Keep track of the currently active link. It will be used
1569 * in completion path to determine whether NCQ phase is in
1572 pp->active_link = qc->dev->link;
1574 if (qc->tf.protocol == ATA_PROT_NCQ)
1575 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1576 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1577 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1582 static void ahci_freeze(struct ata_port *ap)
1584 void __iomem *port_mmio = ahci_port_base(ap);
1587 writel(0, port_mmio + PORT_IRQ_MASK);
1590 static void ahci_thaw(struct ata_port *ap)
1592 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1593 void __iomem *port_mmio = ahci_port_base(ap);
1595 struct ahci_port_priv *pp = ap->private_data;
1598 tmp = readl(port_mmio + PORT_IRQ_STAT);
1599 writel(tmp, port_mmio + PORT_IRQ_STAT);
1600 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1602 /* turn IRQ back on, ignore BAD_PMP if PMP isn't attached */
1603 tmp = pp->intr_mask;
1604 if (!ap->nr_pmp_links)
1605 tmp &= ~PORT_IRQ_BAD_PMP;
1606 writel(tmp, port_mmio + PORT_IRQ_MASK);
1609 static void ahci_error_handler(struct ata_port *ap)
1611 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1612 /* restart engine */
1613 ahci_stop_engine(ap);
1614 ahci_start_engine(ap);
1617 /* perform recovery */
1618 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1619 ahci_hardreset, ahci_postreset,
1620 sata_pmp_std_prereset, ahci_pmp_softreset,
1621 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1624 static void ahci_vt8251_error_handler(struct ata_port *ap)
1626 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1627 /* restart engine */
1628 ahci_stop_engine(ap);
1629 ahci_start_engine(ap);
1632 /* perform recovery */
1633 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1637 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1639 struct ata_port *ap = qc->ap;
1641 /* make DMA engine forget about the failed command */
1642 if (qc->flags & ATA_QCFLAG_FAILED)
1643 ahci_kick_engine(ap, 1);
1646 static void ahci_pmp_attach(struct ata_port *ap)
1648 void __iomem *port_mmio = ahci_port_base(ap);
1651 cmd = readl(port_mmio + PORT_CMD);
1652 cmd |= PORT_CMD_PMP;
1653 writel(cmd, port_mmio + PORT_CMD);
1656 static void ahci_pmp_detach(struct ata_port *ap)
1658 void __iomem *port_mmio = ahci_port_base(ap);
1659 struct ahci_host_priv *hpriv = ap->host->private_data;
1660 unsigned long flags;
1663 cmd = readl(port_mmio + PORT_CMD);
1664 cmd &= ~PORT_CMD_PMP;
1665 writel(cmd, port_mmio + PORT_CMD);
1667 if (hpriv->cap & HOST_CAP_NCQ) {
1668 spin_lock_irqsave(ap->lock, flags);
1669 ap->flags |= ATA_FLAG_NCQ;
1670 spin_unlock_irqrestore(ap->lock, flags);
1674 static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val)
1676 struct ata_port *ap = dev->link->ap;
1677 struct ata_taskfile tf;
1680 ahci_kick_engine(ap, 0);
1682 sata_pmp_read_init_tf(&tf, dev, pmp, reg);
1683 rc = ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1684 SATA_PMP_SCR_TIMEOUT);
1686 ahci_tf_read(ap, &tf);
1687 *r_val = sata_pmp_read_val(&tf);
1692 static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val)
1694 struct ata_port *ap = dev->link->ap;
1695 struct ata_taskfile tf;
1697 ahci_kick_engine(ap, 0);
1699 sata_pmp_write_init_tf(&tf, dev, pmp, reg, val);
1700 return ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1701 SATA_PMP_SCR_TIMEOUT);
1704 static int ahci_port_resume(struct ata_port *ap)
1707 ahci_start_port(ap);
1709 if (ap->nr_pmp_links)
1710 ahci_pmp_attach(ap);
1712 ahci_pmp_detach(ap);
1718 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1720 const char *emsg = NULL;
1723 rc = ahci_deinit_port(ap, &emsg);
1725 ahci_power_down(ap);
1727 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1728 ahci_start_port(ap);
1734 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1736 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1737 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1740 if (mesg.event == PM_EVENT_SUSPEND) {
1741 /* AHCI spec rev1.1 section 8.3.3:
1742 * Software must disable interrupts prior to requesting a
1743 * transition of the HBA to D3 state.
1745 ctl = readl(mmio + HOST_CTL);
1746 ctl &= ~HOST_IRQ_EN;
1747 writel(ctl, mmio + HOST_CTL);
1748 readl(mmio + HOST_CTL); /* flush */
1751 return ata_pci_device_suspend(pdev, mesg);
1754 static int ahci_pci_device_resume(struct pci_dev *pdev)
1756 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1759 rc = ata_pci_device_do_resume(pdev);
1763 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1764 rc = ahci_reset_controller(host);
1768 ahci_init_controller(host);
1771 ata_host_resume(host);
1777 static int ahci_port_start(struct ata_port *ap)
1779 struct device *dev = ap->host->dev;
1780 struct ahci_port_priv *pp;
1785 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1789 rc = ata_pad_alloc(ap, dev);
1793 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1797 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1800 * First item in chunk of DMA memory: 32-slot command table,
1801 * 32 bytes each in size
1804 pp->cmd_slot_dma = mem_dma;
1806 mem += AHCI_CMD_SLOT_SZ;
1807 mem_dma += AHCI_CMD_SLOT_SZ;
1810 * Second item: Received-FIS area
1813 pp->rx_fis_dma = mem_dma;
1815 mem += AHCI_RX_FIS_SZ;
1816 mem_dma += AHCI_RX_FIS_SZ;
1819 * Third item: data area for storing a single command
1820 * and its scatter-gather table
1823 pp->cmd_tbl_dma = mem_dma;
1826 * Save off initial list of interrupts to be enabled.
1827 * This could be changed later
1829 pp->intr_mask = DEF_PORT_IRQ;
1831 ap->private_data = pp;
1833 /* engage engines, captain */
1834 return ahci_port_resume(ap);
1837 static void ahci_port_stop(struct ata_port *ap)
1839 const char *emsg = NULL;
1842 /* de-initialize port */
1843 rc = ahci_deinit_port(ap, &emsg);
1845 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1848 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1853 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1854 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1856 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1858 dev_printk(KERN_ERR, &pdev->dev,
1859 "64-bit DMA enable failed\n");
1864 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1866 dev_printk(KERN_ERR, &pdev->dev,
1867 "32-bit DMA enable failed\n");
1870 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1872 dev_printk(KERN_ERR, &pdev->dev,
1873 "32-bit consistent DMA enable failed\n");
1880 static void ahci_print_info(struct ata_host *host)
1882 struct ahci_host_priv *hpriv = host->private_data;
1883 struct pci_dev *pdev = to_pci_dev(host->dev);
1884 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1885 u32 vers, cap, impl, speed;
1886 const char *speed_s;
1890 vers = readl(mmio + HOST_VERSION);
1892 impl = hpriv->port_map;
1894 speed = (cap >> 20) & 0xf;
1897 else if (speed == 2)
1902 pci_read_config_word(pdev, 0x0a, &cc);
1903 if (cc == PCI_CLASS_STORAGE_IDE)
1905 else if (cc == PCI_CLASS_STORAGE_SATA)
1907 else if (cc == PCI_CLASS_STORAGE_RAID)
1912 dev_printk(KERN_INFO, &pdev->dev,
1913 "AHCI %02x%02x.%02x%02x "
1914 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1917 (vers >> 24) & 0xff,
1918 (vers >> 16) & 0xff,
1922 ((cap >> 8) & 0x1f) + 1,
1928 dev_printk(KERN_INFO, &pdev->dev,
1934 cap & (1 << 31) ? "64bit " : "",
1935 cap & (1 << 30) ? "ncq " : "",
1936 cap & (1 << 29) ? "sntf " : "",
1937 cap & (1 << 28) ? "ilck " : "",
1938 cap & (1 << 27) ? "stag " : "",
1939 cap & (1 << 26) ? "pm " : "",
1940 cap & (1 << 25) ? "led " : "",
1942 cap & (1 << 24) ? "clo " : "",
1943 cap & (1 << 19) ? "nz " : "",
1944 cap & (1 << 18) ? "only " : "",
1945 cap & (1 << 17) ? "pmp " : "",
1946 cap & (1 << 15) ? "pio " : "",
1947 cap & (1 << 14) ? "slum " : "",
1948 cap & (1 << 13) ? "part " : ""
1952 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1954 static int printed_version;
1955 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1956 const struct ata_port_info *ppi[] = { &pi, NULL };
1957 struct device *dev = &pdev->dev;
1958 struct ahci_host_priv *hpriv;
1959 struct ata_host *host;
1964 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1966 if (!printed_version++)
1967 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1969 /* acquire resources */
1970 rc = pcim_enable_device(pdev);
1974 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1976 pcim_pin_device(pdev);
1980 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
1983 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1987 /* save initial config */
1988 ahci_save_initial_config(pdev, &pi, hpriv);
1991 if (hpriv->cap & HOST_CAP_NCQ)
1992 pi.flags |= ATA_FLAG_NCQ;
1994 if (hpriv->cap & HOST_CAP_PMP)
1995 pi.flags |= ATA_FLAG_PMP;
1997 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2000 host->iomap = pcim_iomap_table(pdev);
2001 host->private_data = hpriv;
2003 for (i = 0; i < host->n_ports; i++) {
2004 struct ata_port *ap = host->ports[i];
2005 void __iomem *port_mmio = ahci_port_base(ap);
2007 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2008 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2009 0x100 + ap->port_no * 0x80, "port");
2011 /* standard SATA port setup */
2012 if (hpriv->port_map & (1 << i))
2013 ap->ioaddr.cmd_addr = port_mmio;
2015 /* disabled/not-implemented port */
2017 ap->ops = &ata_dummy_port_ops;
2020 /* initialize adapter */
2021 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2025 rc = ahci_reset_controller(host);
2029 ahci_init_controller(host);
2030 ahci_print_info(host);
2032 pci_set_master(pdev);
2033 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2037 static int __init ahci_init(void)
2039 return pci_register_driver(&ahci_pci_driver);
2042 static void __exit ahci_exit(void)
2044 pci_unregister_driver(&ahci_pci_driver);
2048 MODULE_AUTHOR("Jeff Garzik");
2049 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2050 MODULE_LICENSE("GPL");
2051 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2052 MODULE_VERSION(DRV_VERSION);
2054 module_init(ahci_init);
2055 module_exit(ahci_exit);