2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/libata.h>
38 #include <linux/highmem.h>
42 const struct ata_port_operations ata_sff_port_ops = {
43 .inherits = &ata_base_port_ops,
45 .qc_prep = ata_sff_qc_prep,
46 .qc_issue = ata_sff_qc_issue,
48 .freeze = ata_sff_freeze,
50 .softreset = ata_sff_softreset,
51 .error_handler = ata_sff_error_handler,
52 .post_internal_cmd = ata_sff_post_internal_cmd,
54 .sff_dev_select = ata_sff_dev_select,
55 .sff_check_status = ata_sff_check_status,
56 .sff_tf_load = ata_sff_tf_load,
57 .sff_tf_read = ata_sff_tf_read,
58 .sff_exec_command = ata_sff_exec_command,
59 .sff_data_xfer = ata_sff_data_xfer,
60 .sff_irq_on = ata_sff_irq_on,
61 .sff_irq_clear = ata_sff_irq_clear,
63 .port_start = ata_sff_port_start,
66 const struct ata_port_operations ata_bmdma_port_ops = {
67 .inherits = &ata_sff_port_ops,
69 .mode_filter = ata_bmdma_mode_filter,
71 .bmdma_setup = ata_bmdma_setup,
72 .bmdma_start = ata_bmdma_start,
73 .bmdma_stop = ata_bmdma_stop,
74 .bmdma_status = ata_bmdma_status,
78 * ata_fill_sg - Fill PCI IDE PRD table
79 * @qc: Metadata associated with taskfile to be transferred
81 * Fill PCI IDE PRD (scatter-gather) table with segments
82 * associated with the current disk command.
85 * spin_lock_irqsave(host lock)
88 static void ata_fill_sg(struct ata_queued_cmd *qc)
90 struct ata_port *ap = qc->ap;
91 struct scatterlist *sg;
95 for_each_sg(qc->sg, sg, qc->n_elem, si) {
99 /* determine if physical DMA addr spans 64K boundary.
100 * Note h/w doesn't support 64-bit, so we unconditionally
101 * truncate dma_addr_t to u32.
103 addr = (u32) sg_dma_address(sg);
104 sg_len = sg_dma_len(sg);
107 offset = addr & 0xffff;
109 if ((offset + sg_len) > 0x10000)
110 len = 0x10000 - offset;
112 ap->prd[pi].addr = cpu_to_le32(addr);
113 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
114 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
122 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
126 * ata_fill_sg_dumb - Fill PCI IDE PRD table
127 * @qc: Metadata associated with taskfile to be transferred
129 * Fill PCI IDE PRD (scatter-gather) table with segments
130 * associated with the current disk command. Perform the fill
131 * so that we avoid writing any length 64K records for
132 * controllers that don't follow the spec.
135 * spin_lock_irqsave(host lock)
138 static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
140 struct ata_port *ap = qc->ap;
141 struct scatterlist *sg;
145 for_each_sg(qc->sg, sg, qc->n_elem, si) {
147 u32 sg_len, len, blen;
149 /* determine if physical DMA addr spans 64K boundary.
150 * Note h/w doesn't support 64-bit, so we unconditionally
151 * truncate dma_addr_t to u32.
153 addr = (u32) sg_dma_address(sg);
154 sg_len = sg_dma_len(sg);
157 offset = addr & 0xffff;
159 if ((offset + sg_len) > 0x10000)
160 len = 0x10000 - offset;
163 ap->prd[pi].addr = cpu_to_le32(addr);
165 /* Some PATA chipsets like the CS5530 can't
166 cope with 0x0000 meaning 64K as the spec says */
167 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
169 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
171 ap->prd[pi].flags_len = cpu_to_le32(blen);
172 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
180 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
184 * ata_sff_qc_prep - Prepare taskfile for submission
185 * @qc: Metadata associated with taskfile to be prepared
187 * Prepare ATA taskfile for submission.
190 * spin_lock_irqsave(host lock)
192 void ata_sff_qc_prep(struct ata_queued_cmd *qc)
194 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
201 * ata_sff_dumb_qc_prep - Prepare taskfile for submission
202 * @qc: Metadata associated with taskfile to be prepared
204 * Prepare ATA taskfile for submission.
207 * spin_lock_irqsave(host lock)
209 void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
211 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
214 ata_fill_sg_dumb(qc);
218 * ata_sff_check_status - Read device status reg & clear interrupt
219 * @ap: port where the device is
221 * Reads ATA taskfile status register for currently-selected device
222 * and return its value. This also clears pending interrupts
226 * Inherited from caller.
228 u8 ata_sff_check_status(struct ata_port *ap)
230 return ioread8(ap->ioaddr.status_addr);
234 * ata_sff_altstatus - Read device alternate status reg
235 * @ap: port where the device is
237 * Reads ATA taskfile alternate status register for
238 * currently-selected device and return its value.
240 * Note: may NOT be used as the check_altstatus() entry in
241 * ata_port_operations.
244 * Inherited from caller.
246 u8 ata_sff_altstatus(struct ata_port *ap)
248 if (ap->ops->sff_check_altstatus)
249 return ap->ops->sff_check_altstatus(ap);
251 return ioread8(ap->ioaddr.altstatus_addr);
255 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
256 * @ap: port containing status register to be polled
257 * @tmout_pat: impatience timeout
258 * @tmout: overall timeout
260 * Sleep until ATA Status register bit BSY clears,
261 * or a timeout occurs.
264 * Kernel thread context (may sleep).
267 * 0 on success, -errno otherwise.
269 int ata_sff_busy_sleep(struct ata_port *ap,
270 unsigned long tmout_pat, unsigned long tmout)
272 unsigned long timer_start, timeout;
275 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
276 timer_start = jiffies;
277 timeout = timer_start + tmout_pat;
278 while (status != 0xff && (status & ATA_BUSY) &&
279 time_before(jiffies, timeout)) {
281 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
284 if (status != 0xff && (status & ATA_BUSY))
285 ata_port_printk(ap, KERN_WARNING,
286 "port is slow to respond, please be patient "
287 "(Status 0x%x)\n", status);
289 timeout = timer_start + tmout;
290 while (status != 0xff && (status & ATA_BUSY) &&
291 time_before(jiffies, timeout)) {
293 status = ap->ops->sff_check_status(ap);
299 if (status & ATA_BUSY) {
300 ata_port_printk(ap, KERN_ERR, "port failed to respond "
301 "(%lu secs, Status 0x%x)\n",
310 * ata_sff_wait_ready - sleep until BSY clears, or timeout
311 * @ap: port containing status register to be polled
312 * @deadline: deadline jiffies for the operation
314 * Sleep until ATA Status register bit BSY clears, or timeout
318 * Kernel thread context (may sleep).
321 * 0 on success, -errno otherwise.
323 int ata_sff_wait_ready(struct ata_port *ap, unsigned long deadline)
325 unsigned long start = jiffies;
329 u8 status = ap->ops->sff_check_status(ap);
330 unsigned long now = jiffies;
332 if (!(status & ATA_BUSY))
334 if (!ata_link_online(&ap->link) && status == 0xff)
336 if (time_after(now, deadline))
339 if (!warned && time_after(now, start + 5 * HZ) &&
340 (deadline - now > 3 * HZ)) {
341 ata_port_printk(ap, KERN_WARNING,
342 "port is slow to respond, please be patient "
343 "(Status 0x%x)\n", status);
352 * ata_sff_dev_select - Select device 0/1 on ATA bus
353 * @ap: ATA channel to manipulate
354 * @device: ATA device (numbered from zero) to select
356 * Use the method defined in the ATA specification to
357 * make either device 0, or device 1, active on the
358 * ATA channel. Works with both PIO and MMIO.
360 * May be used as the dev_select() entry in ata_port_operations.
365 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
370 tmp = ATA_DEVICE_OBS;
372 tmp = ATA_DEVICE_OBS | ATA_DEV1;
374 iowrite8(tmp, ap->ioaddr.device_addr);
375 ata_sff_pause(ap); /* needed; also flushes, for mmio */
379 * ata_dev_select - Select device 0/1 on ATA bus
380 * @ap: ATA channel to manipulate
381 * @device: ATA device (numbered from zero) to select
382 * @wait: non-zero to wait for Status register BSY bit to clear
383 * @can_sleep: non-zero if context allows sleeping
385 * Use the method defined in the ATA specification to
386 * make either device 0, or device 1, active on the
389 * This is a high-level version of ata_sff_dev_select(), which
390 * additionally provides the services of inserting the proper
391 * pauses and status polling, where needed.
396 void ata_dev_select(struct ata_port *ap, unsigned int device,
397 unsigned int wait, unsigned int can_sleep)
399 if (ata_msg_probe(ap))
400 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
401 "device %u, wait %u\n", device, wait);
406 ap->ops->sff_dev_select(ap, device);
409 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
416 * ata_sff_irq_on - Enable interrupts on a port.
417 * @ap: Port on which interrupts are enabled.
419 * Enable interrupts on a legacy IDE device using MMIO or PIO,
420 * wait for idle, clear any pending interrupts.
423 * Inherited from caller.
425 u8 ata_sff_irq_on(struct ata_port *ap)
427 struct ata_ioports *ioaddr = &ap->ioaddr;
430 ap->ctl &= ~ATA_NIEN;
431 ap->last_ctl = ap->ctl;
433 if (ioaddr->ctl_addr)
434 iowrite8(ap->ctl, ioaddr->ctl_addr);
435 tmp = ata_wait_idle(ap);
437 ap->ops->sff_irq_clear(ap);
443 * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
444 * @ap: Port associated with this ATA transaction.
446 * Clear interrupt and error flags in DMA status register.
448 * May be used as the irq_clear() entry in ata_port_operations.
451 * spin_lock_irqsave(host lock)
453 void ata_sff_irq_clear(struct ata_port *ap)
455 void __iomem *mmio = ap->ioaddr.bmdma_addr;
460 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
464 * ata_sff_tf_load - send taskfile registers to host controller
465 * @ap: Port to which output is sent
466 * @tf: ATA taskfile register set
468 * Outputs ATA taskfile to standard ATA host controller.
471 * Inherited from caller.
473 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
475 struct ata_ioports *ioaddr = &ap->ioaddr;
476 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
478 if (tf->ctl != ap->last_ctl) {
479 if (ioaddr->ctl_addr)
480 iowrite8(tf->ctl, ioaddr->ctl_addr);
481 ap->last_ctl = tf->ctl;
485 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
486 WARN_ON(!ioaddr->ctl_addr);
487 iowrite8(tf->hob_feature, ioaddr->feature_addr);
488 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
489 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
490 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
491 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
492 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
501 iowrite8(tf->feature, ioaddr->feature_addr);
502 iowrite8(tf->nsect, ioaddr->nsect_addr);
503 iowrite8(tf->lbal, ioaddr->lbal_addr);
504 iowrite8(tf->lbam, ioaddr->lbam_addr);
505 iowrite8(tf->lbah, ioaddr->lbah_addr);
506 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
514 if (tf->flags & ATA_TFLAG_DEVICE) {
515 iowrite8(tf->device, ioaddr->device_addr);
516 VPRINTK("device 0x%X\n", tf->device);
523 * ata_sff_tf_read - input device's ATA taskfile shadow registers
524 * @ap: Port from which input is read
525 * @tf: ATA taskfile register set for storing input
527 * Reads ATA taskfile registers for currently-selected device
528 * into @tf. Assumes the device has a fully SFF compliant task file
529 * layout and behaviour. If you device does not (eg has a different
530 * status method) then you will need to provide a replacement tf_read
533 * Inherited from caller.
535 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
537 struct ata_ioports *ioaddr = &ap->ioaddr;
539 tf->command = ata_sff_check_status(ap);
540 tf->feature = ioread8(ioaddr->error_addr);
541 tf->nsect = ioread8(ioaddr->nsect_addr);
542 tf->lbal = ioread8(ioaddr->lbal_addr);
543 tf->lbam = ioread8(ioaddr->lbam_addr);
544 tf->lbah = ioread8(ioaddr->lbah_addr);
545 tf->device = ioread8(ioaddr->device_addr);
547 if (tf->flags & ATA_TFLAG_LBA48) {
548 if (likely(ioaddr->ctl_addr)) {
549 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
550 tf->hob_feature = ioread8(ioaddr->error_addr);
551 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
552 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
553 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
554 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
555 iowrite8(tf->ctl, ioaddr->ctl_addr);
556 ap->last_ctl = tf->ctl;
563 * ata_sff_exec_command - issue ATA command to host controller
564 * @ap: port to which command is being issued
565 * @tf: ATA taskfile register set
567 * Issues ATA command, with proper synchronization with interrupt
568 * handler / other threads.
571 * spin_lock_irqsave(host lock)
573 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
575 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
577 iowrite8(tf->command, ap->ioaddr.command_addr);
582 * ata_tf_to_host - issue ATA taskfile to host controller
583 * @ap: port to which command is being issued
584 * @tf: ATA taskfile register set
586 * Issues ATA taskfile register set to ATA host controller,
587 * with proper synchronization with interrupt handler and
591 * spin_lock_irqsave(host lock)
593 static inline void ata_tf_to_host(struct ata_port *ap,
594 const struct ata_taskfile *tf)
596 ap->ops->sff_tf_load(ap, tf);
597 ap->ops->sff_exec_command(ap, tf);
601 * ata_sff_data_xfer - Transfer data by PIO
602 * @dev: device to target
604 * @buflen: buffer length
607 * Transfer data from/to the device data register by PIO.
610 * Inherited from caller.
615 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
616 unsigned int buflen, int rw)
618 struct ata_port *ap = dev->link->ap;
619 void __iomem *data_addr = ap->ioaddr.data_addr;
620 unsigned int words = buflen >> 1;
622 /* Transfer multiple of 2 bytes */
624 ioread16_rep(data_addr, buf, words);
626 iowrite16_rep(data_addr, buf, words);
628 /* Transfer trailing 1 byte, if any. */
629 if (unlikely(buflen & 0x01)) {
630 __le16 align_buf[1] = { 0 };
631 unsigned char *trailing_buf = buf + buflen - 1;
634 align_buf[0] = cpu_to_le16(ioread16(data_addr));
635 memcpy(trailing_buf, align_buf, 1);
637 memcpy(align_buf, trailing_buf, 1);
638 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
647 * ata_sff_data_xfer_noirq - Transfer data by PIO
648 * @dev: device to target
650 * @buflen: buffer length
653 * Transfer data from/to the device data register by PIO. Do the
654 * transfer with interrupts disabled.
657 * Inherited from caller.
662 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
663 unsigned int buflen, int rw)
666 unsigned int consumed;
668 local_irq_save(flags);
669 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
670 local_irq_restore(flags);
676 * ata_pio_sector - Transfer a sector of data.
677 * @qc: Command on going
679 * Transfer qc->sect_size bytes of data from/to the ATA device.
682 * Inherited from caller.
684 static void ata_pio_sector(struct ata_queued_cmd *qc)
686 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
687 struct ata_port *ap = qc->ap;
692 if (qc->curbytes == qc->nbytes - qc->sect_size)
693 ap->hsm_task_state = HSM_ST_LAST;
695 page = sg_page(qc->cursg);
696 offset = qc->cursg->offset + qc->cursg_ofs;
698 /* get the current page and offset */
699 page = nth_page(page, (offset >> PAGE_SHIFT));
702 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
704 if (PageHighMem(page)) {
707 /* FIXME: use a bounce buffer */
708 local_irq_save(flags);
709 buf = kmap_atomic(page, KM_IRQ0);
711 /* do the actual data transfer */
712 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
715 kunmap_atomic(buf, KM_IRQ0);
716 local_irq_restore(flags);
718 buf = page_address(page);
719 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
723 qc->curbytes += qc->sect_size;
724 qc->cursg_ofs += qc->sect_size;
726 if (qc->cursg_ofs == qc->cursg->length) {
727 qc->cursg = sg_next(qc->cursg);
733 * ata_pio_sectors - Transfer one or many sectors.
734 * @qc: Command on going
736 * Transfer one or many sectors of data from/to the
737 * ATA device for the DRQ request.
740 * Inherited from caller.
742 static void ata_pio_sectors(struct ata_queued_cmd *qc)
744 if (is_multi_taskfile(&qc->tf)) {
745 /* READ/WRITE MULTIPLE */
748 WARN_ON(qc->dev->multi_count == 0);
750 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
751 qc->dev->multi_count);
757 ata_sff_altstatus(qc->ap); /* flush */
761 * atapi_send_cdb - Write CDB bytes to hardware
762 * @ap: Port to which ATAPI device is attached.
763 * @qc: Taskfile currently active
765 * When device has indicated its readiness to accept
766 * a CDB, this function is called. Send the CDB.
771 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
774 DPRINTK("send cdb\n");
775 WARN_ON(qc->dev->cdb_len < 12);
777 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
778 ata_sff_altstatus(ap); /* flush */
780 switch (qc->tf.protocol) {
782 ap->hsm_task_state = HSM_ST;
784 case ATAPI_PROT_NODATA:
785 ap->hsm_task_state = HSM_ST_LAST;
788 ap->hsm_task_state = HSM_ST_LAST;
790 ap->ops->bmdma_start(qc);
796 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
797 * @qc: Command on going
798 * @bytes: number of bytes
800 * Transfer Transfer data from/to the ATAPI device.
803 * Inherited from caller.
806 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
808 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
809 struct ata_port *ap = qc->ap;
810 struct ata_device *dev = qc->dev;
811 struct ata_eh_info *ehi = &dev->link->eh_info;
812 struct scatterlist *sg;
815 unsigned int offset, count, consumed;
820 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
821 "buf=%u cur=%u bytes=%u",
822 qc->nbytes, qc->curbytes, bytes);
827 offset = sg->offset + qc->cursg_ofs;
829 /* get the current page and offset */
830 page = nth_page(page, (offset >> PAGE_SHIFT));
833 /* don't overrun current sg */
834 count = min(sg->length - qc->cursg_ofs, bytes);
836 /* don't cross page boundaries */
837 count = min(count, (unsigned int)PAGE_SIZE - offset);
839 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
841 if (PageHighMem(page)) {
844 /* FIXME: use bounce buffer */
845 local_irq_save(flags);
846 buf = kmap_atomic(page, KM_IRQ0);
848 /* do the actual data transfer */
849 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
851 kunmap_atomic(buf, KM_IRQ0);
852 local_irq_restore(flags);
854 buf = page_address(page);
855 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
858 bytes -= min(bytes, consumed);
859 qc->curbytes += count;
860 qc->cursg_ofs += count;
862 if (qc->cursg_ofs == sg->length) {
863 qc->cursg = sg_next(qc->cursg);
867 /* consumed can be larger than count only for the last transfer */
868 WARN_ON(qc->cursg && count != consumed);
876 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
877 * @qc: Command on going
879 * Transfer Transfer data from/to the ATAPI device.
882 * Inherited from caller.
884 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
886 struct ata_port *ap = qc->ap;
887 struct ata_device *dev = qc->dev;
888 struct ata_eh_info *ehi = &dev->link->eh_info;
889 unsigned int ireason, bc_lo, bc_hi, bytes;
890 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
892 /* Abuse qc->result_tf for temp storage of intermediate TF
893 * here to save some kernel stack usage.
894 * For normal completion, qc->result_tf is not relevant. For
895 * error, qc->result_tf is later overwritten by ata_qc_complete().
896 * So, the correctness of qc->result_tf is not affected.
898 ap->ops->sff_tf_read(ap, &qc->result_tf);
899 ireason = qc->result_tf.nsect;
900 bc_lo = qc->result_tf.lbam;
901 bc_hi = qc->result_tf.lbah;
902 bytes = (bc_hi << 8) | bc_lo;
904 /* shall be cleared to zero, indicating xfer of data */
905 if (unlikely(ireason & (1 << 0)))
908 /* make sure transfer direction matches expected */
909 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
910 if (unlikely(do_write != i_write))
913 if (unlikely(!bytes))
916 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
918 if (unlikely(__atapi_pio_bytes(qc, bytes)))
920 ata_sff_altstatus(ap); /* flush */
925 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
928 qc->err_mask |= AC_ERR_HSM;
929 ap->hsm_task_state = HSM_ST_ERR;
933 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
934 * @ap: the target ata_port
938 * 1 if ok in workqueue, 0 otherwise.
940 static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
942 if (qc->tf.flags & ATA_TFLAG_POLLING)
945 if (ap->hsm_task_state == HSM_ST_FIRST) {
946 if (qc->tf.protocol == ATA_PROT_PIO &&
947 (qc->tf.flags & ATA_TFLAG_WRITE))
950 if (ata_is_atapi(qc->tf.protocol) &&
951 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
959 * ata_hsm_qc_complete - finish a qc running on standard HSM
960 * @qc: Command to complete
961 * @in_wq: 1 if called from workqueue, 0 otherwise
963 * Finish @qc which is running on standard HSM.
966 * If @in_wq is zero, spin_lock_irqsave(host lock).
967 * Otherwise, none on entry and grabs host lock.
969 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
971 struct ata_port *ap = qc->ap;
974 if (ap->ops->error_handler) {
976 spin_lock_irqsave(ap->lock, flags);
978 /* EH might have kicked in while host lock is
981 qc = ata_qc_from_tag(ap, qc->tag);
983 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
984 ap->ops->sff_irq_on(ap);
990 spin_unlock_irqrestore(ap->lock, flags);
992 if (likely(!(qc->err_mask & AC_ERR_HSM)))
999 spin_lock_irqsave(ap->lock, flags);
1000 ap->ops->sff_irq_on(ap);
1001 ata_qc_complete(qc);
1002 spin_unlock_irqrestore(ap->lock, flags);
1004 ata_qc_complete(qc);
1009 * ata_sff_hsm_move - move the HSM to the next state.
1010 * @ap: the target ata_port
1012 * @status: current device status
1013 * @in_wq: 1 if called from workqueue, 0 otherwise
1016 * 1 when poll next status needed, 0 otherwise.
1018 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1019 u8 status, int in_wq)
1021 unsigned long flags = 0;
1024 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1026 /* Make sure ata_sff_qc_issue() does not throw things
1027 * like DMA polling into the workqueue. Notice that
1028 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1030 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
1033 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1034 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1036 switch (ap->hsm_task_state) {
1038 /* Send first data block or PACKET CDB */
1040 /* If polling, we will stay in the work queue after
1041 * sending the data. Otherwise, interrupt handler
1042 * takes over after sending the data.
1044 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1046 /* check device status */
1047 if (unlikely((status & ATA_DRQ) == 0)) {
1048 /* handle BSY=0, DRQ=0 as error */
1049 if (likely(status & (ATA_ERR | ATA_DF)))
1050 /* device stops HSM for abort/error */
1051 qc->err_mask |= AC_ERR_DEV;
1053 /* HSM violation. Let EH handle this */
1054 qc->err_mask |= AC_ERR_HSM;
1056 ap->hsm_task_state = HSM_ST_ERR;
1060 /* Device should not ask for data transfer (DRQ=1)
1061 * when it finds something wrong.
1062 * We ignore DRQ here and stop the HSM by
1063 * changing hsm_task_state to HSM_ST_ERR and
1064 * let the EH abort the command or reset the device.
1066 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1067 /* Some ATAPI tape drives forget to clear the ERR bit
1068 * when doing the next command (mostly request sense).
1069 * We ignore ERR here to workaround and proceed sending
1072 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1073 ata_port_printk(ap, KERN_WARNING,
1074 "DRQ=1 with device error, "
1075 "dev_stat 0x%X\n", status);
1076 qc->err_mask |= AC_ERR_HSM;
1077 ap->hsm_task_state = HSM_ST_ERR;
1082 /* Send the CDB (atapi) or the first data block (ata pio out).
1083 * During the state transition, interrupt handler shouldn't
1084 * be invoked before the data transfer is complete and
1085 * hsm_task_state is changed. Hence, the following locking.
1088 spin_lock_irqsave(ap->lock, flags);
1090 if (qc->tf.protocol == ATA_PROT_PIO) {
1091 /* PIO data out protocol.
1092 * send first data block.
1095 /* ata_pio_sectors() might change the state
1096 * to HSM_ST_LAST. so, the state is changed here
1097 * before ata_pio_sectors().
1099 ap->hsm_task_state = HSM_ST;
1100 ata_pio_sectors(qc);
1103 atapi_send_cdb(ap, qc);
1106 spin_unlock_irqrestore(ap->lock, flags);
1108 /* if polling, ata_pio_task() handles the rest.
1109 * otherwise, interrupt handler takes over from here.
1114 /* complete command or read/write the data register */
1115 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1116 /* ATAPI PIO protocol */
1117 if ((status & ATA_DRQ) == 0) {
1118 /* No more data to transfer or device error.
1119 * Device error will be tagged in HSM_ST_LAST.
1121 ap->hsm_task_state = HSM_ST_LAST;
1125 /* Device should not ask for data transfer (DRQ=1)
1126 * when it finds something wrong.
1127 * We ignore DRQ here and stop the HSM by
1128 * changing hsm_task_state to HSM_ST_ERR and
1129 * let the EH abort the command or reset the device.
1131 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1132 ata_port_printk(ap, KERN_WARNING, "DRQ=1 with "
1133 "device error, dev_stat 0x%X\n",
1135 qc->err_mask |= AC_ERR_HSM;
1136 ap->hsm_task_state = HSM_ST_ERR;
1140 atapi_pio_bytes(qc);
1142 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1143 /* bad ireason reported by device */
1147 /* ATA PIO protocol */
1148 if (unlikely((status & ATA_DRQ) == 0)) {
1149 /* handle BSY=0, DRQ=0 as error */
1150 if (likely(status & (ATA_ERR | ATA_DF)))
1151 /* device stops HSM for abort/error */
1152 qc->err_mask |= AC_ERR_DEV;
1154 /* HSM violation. Let EH handle this.
1155 * Phantom devices also trigger this
1156 * condition. Mark hint.
1158 qc->err_mask |= AC_ERR_HSM |
1161 ap->hsm_task_state = HSM_ST_ERR;
1165 /* For PIO reads, some devices may ask for
1166 * data transfer (DRQ=1) alone with ERR=1.
1167 * We respect DRQ here and transfer one
1168 * block of junk data before changing the
1169 * hsm_task_state to HSM_ST_ERR.
1171 * For PIO writes, ERR=1 DRQ=1 doesn't make
1172 * sense since the data block has been
1173 * transferred to the device.
1175 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1176 /* data might be corrputed */
1177 qc->err_mask |= AC_ERR_DEV;
1179 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1180 ata_pio_sectors(qc);
1181 status = ata_wait_idle(ap);
1184 if (status & (ATA_BUSY | ATA_DRQ))
1185 qc->err_mask |= AC_ERR_HSM;
1187 /* ata_pio_sectors() might change the
1188 * state to HSM_ST_LAST. so, the state
1189 * is changed after ata_pio_sectors().
1191 ap->hsm_task_state = HSM_ST_ERR;
1195 ata_pio_sectors(qc);
1197 if (ap->hsm_task_state == HSM_ST_LAST &&
1198 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1200 status = ata_wait_idle(ap);
1209 if (unlikely(!ata_ok(status))) {
1210 qc->err_mask |= __ac_err_mask(status);
1211 ap->hsm_task_state = HSM_ST_ERR;
1215 /* no more data to transfer */
1216 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1217 ap->print_id, qc->dev->devno, status);
1219 WARN_ON(qc->err_mask);
1221 ap->hsm_task_state = HSM_ST_IDLE;
1223 /* complete taskfile transaction */
1224 ata_hsm_qc_complete(qc, in_wq);
1230 /* make sure qc->err_mask is available to
1231 * know what's wrong and recover
1233 WARN_ON(qc->err_mask == 0);
1235 ap->hsm_task_state = HSM_ST_IDLE;
1237 /* complete taskfile transaction */
1238 ata_hsm_qc_complete(qc, in_wq);
1250 void ata_pio_task(struct work_struct *work)
1252 struct ata_port *ap =
1253 container_of(work, struct ata_port, port_task.work);
1254 struct ata_queued_cmd *qc = ap->port_task_data;
1259 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
1262 * This is purely heuristic. This is a fast path.
1263 * Sometimes when we enter, BSY will be cleared in
1264 * a chk-status or two. If not, the drive is probably seeking
1265 * or something. Snooze for a couple msecs, then
1266 * chk-status again. If still busy, queue delayed work.
1268 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1269 if (status & ATA_BUSY) {
1271 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1272 if (status & ATA_BUSY) {
1273 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1279 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1281 /* another command or interrupt handler
1282 * may be running at this point.
1289 * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
1290 * @qc: command to issue to device
1292 * Using various libata functions and hooks, this function
1293 * starts an ATA command. ATA commands are grouped into
1294 * classes called "protocols", and issuing each type of protocol
1295 * is slightly different.
1297 * May be used as the qc_issue() entry in ata_port_operations.
1300 * spin_lock_irqsave(host lock)
1303 * Zero on success, AC_ERR_* mask on failure
1305 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1307 struct ata_port *ap = qc->ap;
1309 /* Use polling pio if the LLD doesn't handle
1310 * interrupt driven pio and atapi CDB interrupt.
1312 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1313 switch (qc->tf.protocol) {
1315 case ATA_PROT_NODATA:
1316 case ATAPI_PROT_PIO:
1317 case ATAPI_PROT_NODATA:
1318 qc->tf.flags |= ATA_TFLAG_POLLING;
1320 case ATAPI_PROT_DMA:
1321 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1322 /* see ata_dma_blacklisted() */
1330 /* select the device */
1331 ata_dev_select(ap, qc->dev->devno, 1, 0);
1333 /* start the command */
1334 switch (qc->tf.protocol) {
1335 case ATA_PROT_NODATA:
1336 if (qc->tf.flags & ATA_TFLAG_POLLING)
1337 ata_qc_set_polling(qc);
1339 ata_tf_to_host(ap, &qc->tf);
1340 ap->hsm_task_state = HSM_ST_LAST;
1342 if (qc->tf.flags & ATA_TFLAG_POLLING)
1343 ata_pio_queue_task(ap, qc, 0);
1348 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1350 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1351 ap->ops->bmdma_setup(qc); /* set up bmdma */
1352 ap->ops->bmdma_start(qc); /* initiate bmdma */
1353 ap->hsm_task_state = HSM_ST_LAST;
1357 if (qc->tf.flags & ATA_TFLAG_POLLING)
1358 ata_qc_set_polling(qc);
1360 ata_tf_to_host(ap, &qc->tf);
1362 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1363 /* PIO data out protocol */
1364 ap->hsm_task_state = HSM_ST_FIRST;
1365 ata_pio_queue_task(ap, qc, 0);
1367 /* always send first data block using
1368 * the ata_pio_task() codepath.
1371 /* PIO data in protocol */
1372 ap->hsm_task_state = HSM_ST;
1374 if (qc->tf.flags & ATA_TFLAG_POLLING)
1375 ata_pio_queue_task(ap, qc, 0);
1377 /* if polling, ata_pio_task() handles the rest.
1378 * otherwise, interrupt handler takes over from here.
1384 case ATAPI_PROT_PIO:
1385 case ATAPI_PROT_NODATA:
1386 if (qc->tf.flags & ATA_TFLAG_POLLING)
1387 ata_qc_set_polling(qc);
1389 ata_tf_to_host(ap, &qc->tf);
1391 ap->hsm_task_state = HSM_ST_FIRST;
1393 /* send cdb by polling if no cdb interrupt */
1394 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1395 (qc->tf.flags & ATA_TFLAG_POLLING))
1396 ata_pio_queue_task(ap, qc, 0);
1399 case ATAPI_PROT_DMA:
1400 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1402 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1403 ap->ops->bmdma_setup(qc); /* set up bmdma */
1404 ap->hsm_task_state = HSM_ST_FIRST;
1406 /* send cdb by polling if no cdb interrupt */
1407 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1408 ata_pio_queue_task(ap, qc, 0);
1413 return AC_ERR_SYSTEM;
1420 * ata_sff_host_intr - Handle host interrupt for given (port, task)
1421 * @ap: Port on which interrupt arrived (possibly...)
1422 * @qc: Taskfile currently active in engine
1424 * Handle host interrupt for given queued command. Currently,
1425 * only DMA interrupts are handled. All other commands are
1426 * handled via polling with interrupts disabled (nIEN bit).
1429 * spin_lock_irqsave(host lock)
1432 * One if interrupt was handled, zero if not (shared irq).
1434 inline unsigned int ata_sff_host_intr(struct ata_port *ap,
1435 struct ata_queued_cmd *qc)
1437 struct ata_eh_info *ehi = &ap->link.eh_info;
1438 u8 status, host_stat = 0;
1440 VPRINTK("ata%u: protocol %d task_state %d\n",
1441 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1443 /* Check whether we are expecting interrupt in this state */
1444 switch (ap->hsm_task_state) {
1446 /* Some pre-ATAPI-4 devices assert INTRQ
1447 * at this state when ready to receive CDB.
1450 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1451 * The flag was turned on only for atapi devices. No
1452 * need to check ata_is_atapi(qc->tf.protocol) again.
1454 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1458 if (qc->tf.protocol == ATA_PROT_DMA ||
1459 qc->tf.protocol == ATAPI_PROT_DMA) {
1460 /* check status of DMA engine */
1461 host_stat = ap->ops->bmdma_status(ap);
1462 VPRINTK("ata%u: host_stat 0x%X\n",
1463 ap->print_id, host_stat);
1465 /* if it's not our irq... */
1466 if (!(host_stat & ATA_DMA_INTR))
1469 /* before we do anything else, clear DMA-Start bit */
1470 ap->ops->bmdma_stop(qc);
1472 if (unlikely(host_stat & ATA_DMA_ERR)) {
1473 /* error when transfering data to/from memory */
1474 qc->err_mask |= AC_ERR_HOST_BUS;
1475 ap->hsm_task_state = HSM_ST_ERR;
1485 /* check altstatus */
1486 status = ata_sff_altstatus(ap);
1487 if (status & ATA_BUSY)
1490 /* check main status, clearing INTRQ */
1491 status = ap->ops->sff_check_status(ap);
1492 if (unlikely(status & ATA_BUSY))
1495 /* ack bmdma irq events */
1496 ap->ops->sff_irq_clear(ap);
1498 ata_sff_hsm_move(ap, qc, status, 0);
1500 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1501 qc->tf.protocol == ATAPI_PROT_DMA))
1502 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1504 return 1; /* irq handled */
1507 ap->stats.idle_irq++;
1510 if ((ap->stats.idle_irq % 1000) == 0) {
1511 ap->ops->sff_check_status(ap);
1512 ap->ops->sff_irq_clear(ap);
1513 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1517 return 0; /* irq not handled */
1521 * ata_sff_interrupt - Default ATA host interrupt handler
1522 * @irq: irq line (unused)
1523 * @dev_instance: pointer to our ata_host information structure
1525 * Default interrupt handler for PCI IDE devices. Calls
1526 * ata_sff_host_intr() for each port that is not disabled.
1529 * Obtains host lock during operation.
1532 * IRQ_NONE or IRQ_HANDLED.
1534 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1536 struct ata_host *host = dev_instance;
1538 unsigned int handled = 0;
1539 unsigned long flags;
1541 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1542 spin_lock_irqsave(&host->lock, flags);
1544 for (i = 0; i < host->n_ports; i++) {
1545 struct ata_port *ap;
1547 ap = host->ports[i];
1549 !(ap->flags & ATA_FLAG_DISABLED)) {
1550 struct ata_queued_cmd *qc;
1552 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1553 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1554 (qc->flags & ATA_QCFLAG_ACTIVE))
1555 handled |= ata_sff_host_intr(ap, qc);
1559 spin_unlock_irqrestore(&host->lock, flags);
1561 return IRQ_RETVAL(handled);
1565 * ata_sff_freeze - Freeze SFF controller port
1566 * @ap: port to freeze
1568 * Freeze BMDMA controller port.
1571 * Inherited from caller.
1573 void ata_sff_freeze(struct ata_port *ap)
1575 struct ata_ioports *ioaddr = &ap->ioaddr;
1577 ap->ctl |= ATA_NIEN;
1578 ap->last_ctl = ap->ctl;
1580 if (ioaddr->ctl_addr)
1581 iowrite8(ap->ctl, ioaddr->ctl_addr);
1583 /* Under certain circumstances, some controllers raise IRQ on
1584 * ATA_NIEN manipulation. Also, many controllers fail to mask
1585 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1587 ap->ops->sff_check_status(ap);
1589 ap->ops->sff_irq_clear(ap);
1593 * ata_sff_thaw - Thaw SFF controller port
1596 * Thaw SFF controller port.
1599 * Inherited from caller.
1601 void ata_sff_thaw(struct ata_port *ap)
1603 /* clear & re-enable interrupts */
1604 ap->ops->sff_check_status(ap);
1605 ap->ops->sff_irq_clear(ap);
1606 ap->ops->sff_irq_on(ap);
1610 * ata_devchk - PATA device presence detection
1611 * @ap: ATA channel to examine
1612 * @device: Device to examine (starting at zero)
1614 * This technique was originally described in
1615 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1616 * later found its way into the ATA/ATAPI spec.
1618 * Write a pattern to the ATA shadow registers,
1619 * and if a device is present, it will respond by
1620 * correctly storing and echoing back the
1621 * ATA shadow register contents.
1626 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1628 struct ata_ioports *ioaddr = &ap->ioaddr;
1631 ap->ops->sff_dev_select(ap, device);
1633 iowrite8(0x55, ioaddr->nsect_addr);
1634 iowrite8(0xaa, ioaddr->lbal_addr);
1636 iowrite8(0xaa, ioaddr->nsect_addr);
1637 iowrite8(0x55, ioaddr->lbal_addr);
1639 iowrite8(0x55, ioaddr->nsect_addr);
1640 iowrite8(0xaa, ioaddr->lbal_addr);
1642 nsect = ioread8(ioaddr->nsect_addr);
1643 lbal = ioread8(ioaddr->lbal_addr);
1645 if ((nsect == 0x55) && (lbal == 0xaa))
1646 return 1; /* we found a device */
1648 return 0; /* nothing found */
1652 * ata_sff_dev_classify - Parse returned ATA device signature
1653 * @dev: ATA device to classify (starting at zero)
1654 * @present: device seems present
1655 * @r_err: Value of error register on completion
1657 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1658 * an ATA/ATAPI-defined set of values is placed in the ATA
1659 * shadow registers, indicating the results of device detection
1662 * Select the ATA device, and read the values from the ATA shadow
1663 * registers. Then parse according to the Error register value,
1664 * and the spec-defined values examined by ata_dev_classify().
1670 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1672 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1675 struct ata_port *ap = dev->link->ap;
1676 struct ata_taskfile tf;
1680 ap->ops->sff_dev_select(ap, dev->devno);
1682 memset(&tf, 0, sizeof(tf));
1684 ap->ops->sff_tf_read(ap, &tf);
1689 /* see if device passed diags: continue and warn later */
1691 /* diagnostic fail : do nothing _YET_ */
1692 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1695 else if ((dev->devno == 0) && (err == 0x81))
1698 return ATA_DEV_NONE;
1700 /* determine if device is ATA or ATAPI */
1701 class = ata_dev_classify(&tf);
1703 if (class == ATA_DEV_UNKNOWN) {
1704 /* If the device failed diagnostic, it's likely to
1705 * have reported incorrect device signature too.
1706 * Assume ATA device if the device seems present but
1707 * device signature is invalid with diagnostic
1710 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1711 class = ATA_DEV_ATA;
1713 class = ATA_DEV_NONE;
1714 } else if ((class == ATA_DEV_ATA) &&
1715 (ap->ops->sff_check_status(ap) == 0))
1716 class = ATA_DEV_NONE;
1721 static int ata_bus_post_reset(struct ata_port *ap, unsigned int devmask,
1722 unsigned long deadline)
1724 struct ata_ioports *ioaddr = &ap->ioaddr;
1725 unsigned int dev0 = devmask & (1 << 0);
1726 unsigned int dev1 = devmask & (1 << 1);
1729 /* if device 0 was found in ata_devchk, wait for its
1733 rc = ata_sff_wait_ready(ap, deadline);
1741 /* if device 1 was found in ata_devchk, wait for register
1742 * access briefly, then wait for BSY to clear.
1747 ap->ops->sff_dev_select(ap, 1);
1749 /* Wait for register access. Some ATAPI devices fail
1750 * to set nsect/lbal after reset, so don't waste too
1751 * much time on it. We're gonna wait for !BSY anyway.
1753 for (i = 0; i < 2; i++) {
1756 nsect = ioread8(ioaddr->nsect_addr);
1757 lbal = ioread8(ioaddr->lbal_addr);
1758 if ((nsect == 1) && (lbal == 1))
1760 msleep(50); /* give drive a breather */
1763 rc = ata_sff_wait_ready(ap, deadline);
1771 /* is all this really necessary? */
1772 ap->ops->sff_dev_select(ap, 0);
1774 ap->ops->sff_dev_select(ap, 1);
1776 ap->ops->sff_dev_select(ap, 0);
1782 * ata_sff_wait_after_reset - wait before checking status after reset
1783 * @ap: port containing status register to be polled
1784 * @deadline: deadline jiffies for the operation
1786 * After reset, we need to pause a while before reading status.
1787 * Also, certain combination of controller and device report 0xff
1788 * for some duration (e.g. until SATA PHY is up and running)
1789 * which is interpreted as empty port in ATA world. This
1790 * function also waits for such devices to get out of 0xff
1794 * Kernel thread context (may sleep).
1796 void ata_sff_wait_after_reset(struct ata_port *ap, unsigned long deadline)
1798 unsigned long until = jiffies + ATA_TMOUT_FF_WAIT;
1800 if (time_before(until, deadline))
1803 /* Spec mandates ">= 2ms" before checking status. We wait
1804 * 150ms, because that was the magic delay used for ATAPI
1805 * devices in Hale Landis's ATADRVR, for the period of time
1806 * between when the ATA command register is written, and then
1807 * status is checked. Because waiting for "a while" before
1808 * checking status is fine, post SRST, we perform this magic
1809 * delay here as well.
1811 * Old drivers/ide uses the 2mS rule and then waits for ready.
1815 /* Wait for 0xff to clear. Some SATA devices take a long time
1816 * to clear 0xff after reset. For example, HHD424020F7SV00
1817 * iVDR needs >= 800ms while. Quantum GoVault needs even more
1820 * Note that some PATA controllers (pata_ali) explode if
1821 * status register is read more than once when there's no
1824 if (ap->flags & ATA_FLAG_SATA) {
1826 u8 status = ap->ops->sff_check_status(ap);
1828 if (status != 0xff || time_after(jiffies, deadline))
1836 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1837 unsigned long deadline)
1839 struct ata_ioports *ioaddr = &ap->ioaddr;
1841 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1843 /* software reset. causes dev0 to be selected */
1844 iowrite8(ap->ctl, ioaddr->ctl_addr);
1845 udelay(20); /* FIXME: flush */
1846 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1847 udelay(20); /* FIXME: flush */
1848 iowrite8(ap->ctl, ioaddr->ctl_addr);
1850 /* wait a while before checking status */
1851 ata_sff_wait_after_reset(ap, deadline);
1853 /* Before we perform post reset processing we want to see if
1854 * the bus shows 0xFF because the odd clown forgets the D7
1855 * pulldown resistor.
1857 if (ap->ops->sff_check_status(ap) == 0xFF)
1860 return ata_bus_post_reset(ap, devmask, deadline);
1864 * ata_sff_softreset - reset host port via ATA SRST
1865 * @link: ATA link to reset
1866 * @classes: resulting classes of attached devices
1867 * @deadline: deadline jiffies for the operation
1869 * Reset host port using ATA SRST.
1872 * Kernel thread context (may sleep)
1875 * 0 on success, -errno otherwise.
1877 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
1878 unsigned long deadline)
1880 struct ata_port *ap = link->ap;
1881 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1882 unsigned int devmask = 0;
1888 if (ata_link_offline(link)) {
1889 classes[0] = ATA_DEV_NONE;
1893 /* determine if device 0/1 are present */
1894 if (ata_devchk(ap, 0))
1895 devmask |= (1 << 0);
1896 if (slave_possible && ata_devchk(ap, 1))
1897 devmask |= (1 << 1);
1899 /* select device 0 again */
1900 ap->ops->sff_dev_select(ap, 0);
1902 /* issue bus reset */
1903 DPRINTK("about to softreset, devmask=%x\n", devmask);
1904 rc = ata_bus_softreset(ap, devmask, deadline);
1905 /* if link is occupied, -ENODEV too is an error */
1906 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1907 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1911 /* determine by signature whether we have ATA or ATAPI devices */
1912 classes[0] = ata_sff_dev_classify(&link->device[0],
1913 devmask & (1 << 0), &err);
1914 if (slave_possible && err != 0x81)
1915 classes[1] = ata_sff_dev_classify(&link->device[1],
1916 devmask & (1 << 1), &err);
1919 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
1924 * sata_sff_hardreset - reset host port via SATA phy reset
1925 * @link: link to reset
1926 * @class: resulting class of attached device
1927 * @deadline: deadline jiffies for the operation
1929 * SATA phy-reset host port using DET bits of SControl register,
1930 * wait for !BSY and classify the attached device.
1933 * Kernel thread context (may sleep)
1936 * 0 on success, -errno otherwise.
1938 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
1939 unsigned long deadline)
1941 struct ata_port *ap = link->ap;
1942 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1948 rc = sata_link_hardreset(link, timing, deadline);
1950 ata_link_printk(link, KERN_ERR,
1951 "COMRESET failed (errno=%d)\n", rc);
1955 /* TODO: phy layer with polling, timeouts, etc. */
1956 if (ata_link_offline(link)) {
1957 *class = ATA_DEV_NONE;
1958 DPRINTK("EXIT, link offline\n");
1962 /* wait a while before checking status */
1963 ata_sff_wait_after_reset(ap, deadline);
1965 /* If PMP is supported, we have to do follow-up SRST. Note
1966 * that some PMPs don't send D2H Reg FIS after hardreset at
1967 * all if the first port is empty. Wait for it just for a
1968 * second and request follow-up SRST.
1970 if (ap->flags & ATA_FLAG_PMP) {
1971 ata_sff_wait_ready(ap, jiffies + HZ);
1975 rc = ata_sff_wait_ready(ap, deadline);
1976 /* link occupied, -ENODEV too is an error */
1978 ata_link_printk(link, KERN_ERR,
1979 "COMRESET failed (errno=%d)\n", rc);
1983 ap->ops->sff_dev_select(ap, 0); /* probably unnecessary */
1985 *class = ata_sff_dev_classify(link->device, 1, NULL);
1987 DPRINTK("EXIT, class=%u\n", *class);
1992 * ata_sff_error_handler - Stock error handler for BMDMA controller
1993 * @ap: port to handle error for
1995 * Stock error handler for SFF controller. It can handle both
1996 * PATA and SATA controllers. Many controllers should be able to
1997 * use this EH as-is or with some added handling before and
2001 * Kernel thread context (may sleep)
2003 void ata_sff_error_handler(struct ata_port *ap)
2005 ata_reset_fn_t softreset = ap->ops->softreset;
2006 ata_reset_fn_t hardreset = ap->ops->hardreset;
2007 struct ata_queued_cmd *qc;
2008 unsigned long flags;
2011 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2012 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2015 /* reset PIO HSM and stop DMA engine */
2016 spin_lock_irqsave(ap->lock, flags);
2018 ap->hsm_task_state = HSM_ST_IDLE;
2020 if (ap->ioaddr.bmdma_addr &&
2021 qc && (qc->tf.protocol == ATA_PROT_DMA ||
2022 qc->tf.protocol == ATAPI_PROT_DMA)) {
2025 host_stat = ap->ops->bmdma_status(ap);
2027 /* BMDMA controllers indicate host bus error by
2028 * setting DMA_ERR bit and timing out. As it wasn't
2029 * really a timeout event, adjust error mask and
2030 * cancel frozen state.
2032 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2033 qc->err_mask = AC_ERR_HOST_BUS;
2037 ap->ops->bmdma_stop(qc);
2040 ata_sff_altstatus(ap);
2041 ap->ops->sff_check_status(ap);
2042 ap->ops->sff_irq_clear(ap);
2044 spin_unlock_irqrestore(ap->lock, flags);
2047 ata_eh_thaw_port(ap);
2049 /* PIO and DMA engines have been stopped, perform recovery */
2051 /* ata_sff_softreset and sata_sff_hardreset are inherited to
2052 * all SFF drivers from ata_sff_port_ops. Ignore softreset if
2053 * ctl isn't accessible. Ignore hardreset if SCR access isn't
2056 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2058 if (hardreset == sata_sff_hardreset && !sata_scr_valid(&ap->link))
2061 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2062 ap->ops->postreset);
2066 * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
2067 * @qc: internal command to clean up
2070 * Kernel thread context (may sleep)
2072 void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
2074 if (qc->ap->ioaddr.bmdma_addr)
2079 * ata_sff_port_start - Set port up for dma.
2080 * @ap: Port to initialize
2082 * Called just after data structures for each port are
2083 * initialized. Allocates space for PRD table if the device
2084 * is DMA capable SFF.
2086 * May be used as the port_start() entry in ata_port_operations.
2089 * Inherited from caller.
2091 int ata_sff_port_start(struct ata_port *ap)
2093 if (ap->ioaddr.bmdma_addr)
2094 return ata_port_start(ap);
2099 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2100 * @ioaddr: IO address structure to be initialized
2102 * Utility function which initializes data_addr, error_addr,
2103 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2104 * device_addr, status_addr, and command_addr to standard offsets
2105 * relative to cmd_addr.
2107 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2109 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2111 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2112 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2113 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2114 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2115 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2116 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2117 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2118 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2119 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2120 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2123 unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
2124 unsigned long xfer_mask)
2126 /* Filter out DMA modes if the device has been configured by
2127 the BIOS as PIO only */
2129 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
2130 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
2135 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2136 * @qc: Info associated with this ATA transaction.
2139 * spin_lock_irqsave(host lock)
2141 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2143 struct ata_port *ap = qc->ap;
2144 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2147 /* load PRD table addr. */
2148 mb(); /* make sure PRD table writes are visible to controller */
2149 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2151 /* specify data direction, triple-check start bit is clear */
2152 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2153 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2155 dmactl |= ATA_DMA_WR;
2156 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2158 /* issue r/w command */
2159 ap->ops->sff_exec_command(ap, &qc->tf);
2163 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2164 * @qc: Info associated with this ATA transaction.
2167 * spin_lock_irqsave(host lock)
2169 void ata_bmdma_start(struct ata_queued_cmd *qc)
2171 struct ata_port *ap = qc->ap;
2174 /* start host DMA transaction */
2175 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2176 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2178 /* Strictly, one may wish to issue an ioread8() here, to
2179 * flush the mmio write. However, control also passes
2180 * to the hardware at this point, and it will interrupt
2181 * us when we are to resume control. So, in effect,
2182 * we don't care when the mmio write flushes.
2183 * Further, a read of the DMA status register _immediately_
2184 * following the write may not be what certain flaky hardware
2185 * is expected, so I think it is best to not add a readb()
2186 * without first all the MMIO ATA cards/mobos.
2187 * Or maybe I'm just being paranoid.
2189 * FIXME: The posting of this write means I/O starts are
2190 * unneccessarily delayed for MMIO
2195 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2196 * @qc: Command we are ending DMA for
2198 * Clears the ATA_DMA_START flag in the dma control register
2200 * May be used as the bmdma_stop() entry in ata_port_operations.
2203 * spin_lock_irqsave(host lock)
2205 void ata_bmdma_stop(struct ata_queued_cmd *qc)
2207 struct ata_port *ap = qc->ap;
2208 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2210 /* clear start/stop bit */
2211 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2212 mmio + ATA_DMA_CMD);
2214 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2215 ata_sff_altstatus(ap); /* dummy read */
2219 * ata_bmdma_status - Read PCI IDE BMDMA status
2220 * @ap: Port associated with this ATA transaction.
2222 * Read and return BMDMA status register.
2224 * May be used as the bmdma_status() entry in ata_port_operations.
2227 * spin_lock_irqsave(host lock)
2229 u8 ata_bmdma_status(struct ata_port *ap)
2231 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2235 * ata_bus_reset - reset host port and associated ATA channel
2236 * @ap: port to reset
2238 * This is typically the first time we actually start issuing
2239 * commands to the ATA channel. We wait for BSY to clear, then
2240 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2241 * result. Determine what devices, if any, are on the channel
2242 * by looking at the device 0/1 error register. Look at the signature
2243 * stored in each device's taskfile registers, to determine if
2244 * the device is ATA or ATAPI.
2247 * PCI/etc. bus probe sem.
2248 * Obtains host lock.
2251 * Sets ATA_FLAG_DISABLED if bus reset fails.
2254 * This function is only for drivers which still use old EH and
2255 * will be removed soon.
2257 void ata_bus_reset(struct ata_port *ap)
2259 struct ata_device *device = ap->link.device;
2260 struct ata_ioports *ioaddr = &ap->ioaddr;
2261 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2263 unsigned int dev0, dev1 = 0, devmask = 0;
2266 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2268 /* determine if device 0/1 are present */
2269 if (ap->flags & ATA_FLAG_SATA_RESET)
2272 dev0 = ata_devchk(ap, 0);
2274 dev1 = ata_devchk(ap, 1);
2278 devmask |= (1 << 0);
2280 devmask |= (1 << 1);
2282 /* select device 0 again */
2283 ap->ops->sff_dev_select(ap, 0);
2285 /* issue bus reset */
2286 if (ap->flags & ATA_FLAG_SRST) {
2287 rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ);
2288 if (rc && rc != -ENODEV)
2293 * determine by signature whether we have ATA or ATAPI devices
2295 device[0].class = ata_sff_dev_classify(&device[0], dev0, &err);
2296 if ((slave_possible) && (err != 0x81))
2297 device[1].class = ata_sff_dev_classify(&device[1], dev1, &err);
2299 /* is double-select really necessary? */
2300 if (device[1].class != ATA_DEV_NONE)
2301 ap->ops->sff_dev_select(ap, 1);
2302 if (device[0].class != ATA_DEV_NONE)
2303 ap->ops->sff_dev_select(ap, 0);
2305 /* if no devices were detected, disable this port */
2306 if ((device[0].class == ATA_DEV_NONE) &&
2307 (device[1].class == ATA_DEV_NONE))
2310 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2311 /* set up device control for ATA_FLAG_SATA_RESET */
2312 iowrite8(ap->ctl, ioaddr->ctl_addr);
2319 ata_port_printk(ap, KERN_ERR, "disabling port\n");
2320 ata_port_disable(ap);
2328 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
2331 * Some PCI ATA devices report simplex mode but in fact can be told to
2332 * enter non simplex mode. This implements the necessary logic to
2333 * perform the task on such devices. Calling it on other devices will
2334 * have -undefined- behaviour.
2336 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
2338 unsigned long bmdma = pci_resource_start(pdev, 4);
2344 simplex = inb(bmdma + 0x02);
2345 outb(simplex & 0x60, bmdma + 0x02);
2346 simplex = inb(bmdma + 0x02);
2353 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
2354 * @host: target ATA host
2356 * Acquire PCI BMDMA resources and initialize @host accordingly.
2359 * Inherited from calling layer (may sleep).
2362 * 0 on success, -errno otherwise.
2364 int ata_pci_bmdma_init(struct ata_host *host)
2366 struct device *gdev = host->dev;
2367 struct pci_dev *pdev = to_pci_dev(gdev);
2370 /* No BAR4 allocation: No DMA */
2371 if (pci_resource_start(pdev, 4) == 0)
2374 /* TODO: If we get no DMA mask we should fall back to PIO */
2375 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
2378 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
2382 /* request and iomap DMA region */
2383 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
2385 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
2388 host->iomap = pcim_iomap_table(pdev);
2390 for (i = 0; i < 2; i++) {
2391 struct ata_port *ap = host->ports[i];
2392 void __iomem *bmdma = host->iomap[4] + 8 * i;
2394 if (ata_port_is_dummy(ap))
2397 ap->ioaddr.bmdma_addr = bmdma;
2398 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
2399 (ioread8(bmdma + 2) & 0x80))
2400 host->flags |= ATA_HOST_SIMPLEX;
2402 ata_port_desc(ap, "bmdma 0x%llx",
2403 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
2409 static int ata_resources_present(struct pci_dev *pdev, int port)
2413 /* Check the PCI resources for this channel are enabled */
2415 for (i = 0; i < 2; i ++) {
2416 if (pci_resource_start(pdev, port + i) == 0 ||
2417 pci_resource_len(pdev, port + i) == 0)
2424 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2425 * @host: target ATA host
2427 * Acquire native PCI ATA resources for @host and initialize the
2428 * first two ports of @host accordingly. Ports marked dummy are
2429 * skipped and allocation failure makes the port dummy.
2431 * Note that native PCI resources are valid even for legacy hosts
2432 * as we fix up pdev resources array early in boot, so this
2433 * function can be used for both native and legacy SFF hosts.
2436 * Inherited from calling layer (may sleep).
2439 * 0 if at least one port is initialized, -ENODEV if no port is
2442 int ata_pci_sff_init_host(struct ata_host *host)
2444 struct device *gdev = host->dev;
2445 struct pci_dev *pdev = to_pci_dev(gdev);
2446 unsigned int mask = 0;
2449 /* request, iomap BARs and init port addresses accordingly */
2450 for (i = 0; i < 2; i++) {
2451 struct ata_port *ap = host->ports[i];
2453 void __iomem * const *iomap;
2455 if (ata_port_is_dummy(ap))
2458 /* Discard disabled ports. Some controllers show
2459 * their unused channels this way. Disabled ports are
2462 if (!ata_resources_present(pdev, i)) {
2463 ap->ops = &ata_dummy_port_ops;
2467 rc = pcim_iomap_regions(pdev, 0x3 << base,
2468 dev_driver_string(gdev));
2470 dev_printk(KERN_WARNING, gdev,
2471 "failed to request/iomap BARs for port %d "
2472 "(errno=%d)\n", i, rc);
2474 pcim_pin_device(pdev);
2475 ap->ops = &ata_dummy_port_ops;
2478 host->iomap = iomap = pcim_iomap_table(pdev);
2480 ap->ioaddr.cmd_addr = iomap[base];
2481 ap->ioaddr.altstatus_addr =
2482 ap->ioaddr.ctl_addr = (void __iomem *)
2483 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2484 ata_sff_std_ports(&ap->ioaddr);
2486 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2487 (unsigned long long)pci_resource_start(pdev, base),
2488 (unsigned long long)pci_resource_start(pdev, base + 1));
2494 dev_printk(KERN_ERR, gdev, "no available native port\n");
2502 * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
2503 * @pdev: target PCI device
2504 * @ppi: array of port_info, must be enough for two ports
2505 * @r_host: out argument for the initialized ATA host
2507 * Helper to allocate ATA host for @pdev, acquire all native PCI
2508 * resources and initialize it accordingly in one go.
2511 * Inherited from calling layer (may sleep).
2514 * 0 on success, -errno otherwise.
2516 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2517 const struct ata_port_info * const * ppi,
2518 struct ata_host **r_host)
2520 struct ata_host *host;
2523 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2526 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2528 dev_printk(KERN_ERR, &pdev->dev,
2529 "failed to allocate ATA host\n");
2534 rc = ata_pci_sff_init_host(host);
2538 /* init DMA related stuff */
2539 rc = ata_pci_bmdma_init(host);
2543 devres_remove_group(&pdev->dev, NULL);
2548 /* This is necessary because PCI and iomap resources are
2549 * merged and releasing the top group won't release the
2550 * acquired resources if some of those have been acquired
2551 * before entering this function.
2553 pcim_iounmap_regions(pdev, 0xf);
2555 devres_release_group(&pdev->dev, NULL);
2560 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2561 * @host: target SFF ATA host
2562 * @irq_handler: irq_handler used when requesting IRQ(s)
2563 * @sht: scsi_host_template to use when registering the host
2565 * This is the counterpart of ata_host_activate() for SFF ATA
2566 * hosts. This separate helper is necessary because SFF hosts
2567 * use two separate interrupts in legacy mode.
2570 * Inherited from calling layer (may sleep).
2573 * 0 on success, -errno otherwise.
2575 int ata_pci_sff_activate_host(struct ata_host *host,
2576 irq_handler_t irq_handler,
2577 struct scsi_host_template *sht)
2579 struct device *dev = host->dev;
2580 struct pci_dev *pdev = to_pci_dev(dev);
2581 const char *drv_name = dev_driver_string(host->dev);
2582 int legacy_mode = 0, rc;
2584 rc = ata_host_start(host);
2588 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2591 /* TODO: What if one channel is in native mode ... */
2592 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2593 mask = (1 << 2) | (1 << 0);
2594 if ((tmp8 & mask) != mask)
2596 #if defined(CONFIG_NO_ATA_LEGACY)
2597 /* Some platforms with PCI limits cannot address compat
2598 port space. In that case we punt if their firmware has
2599 left a device in compatibility mode */
2601 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2607 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2610 if (!legacy_mode && pdev->irq) {
2611 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2612 IRQF_SHARED, drv_name, host);
2616 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2617 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2618 } else if (legacy_mode) {
2619 if (!ata_port_is_dummy(host->ports[0])) {
2620 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2621 irq_handler, IRQF_SHARED,
2626 ata_port_desc(host->ports[0], "irq %d",
2627 ATA_PRIMARY_IRQ(pdev));
2630 if (!ata_port_is_dummy(host->ports[1])) {
2631 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2632 irq_handler, IRQF_SHARED,
2637 ata_port_desc(host->ports[1], "irq %d",
2638 ATA_SECONDARY_IRQ(pdev));
2642 rc = ata_host_register(host, sht);
2645 devres_remove_group(dev, NULL);
2647 devres_release_group(dev, NULL);
2653 * ata_pci_sff_init_one - Initialize/register PCI IDE host controller
2654 * @pdev: Controller to be initialized
2655 * @ppi: array of port_info, must be enough for two ports
2656 * @sht: scsi_host_template to use when registering the host
2657 * @host_priv: host private_data
2659 * This is a helper function which can be called from a driver's
2660 * xxx_init_one() probe function if the hardware uses traditional
2661 * IDE taskfile registers.
2663 * This function calls pci_enable_device(), reserves its register
2664 * regions, sets the dma mask, enables bus master mode, and calls
2668 * Nobody makes a single channel controller that appears solely as
2669 * the secondary legacy port on PCI.
2672 * Inherited from PCI layer (may sleep).
2675 * Zero on success, negative on errno-based value on error.
2677 int ata_pci_sff_init_one(struct pci_dev *pdev,
2678 const struct ata_port_info * const * ppi,
2679 struct scsi_host_template *sht, void *host_priv)
2681 struct device *dev = &pdev->dev;
2682 const struct ata_port_info *pi = NULL;
2683 struct ata_host *host = NULL;
2688 /* look up the first valid port_info */
2689 for (i = 0; i < 2 && ppi[i]; i++) {
2690 if (ppi[i]->port_ops != &ata_dummy_port_ops) {
2697 dev_printk(KERN_ERR, &pdev->dev,
2698 "no valid port_info specified\n");
2702 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2705 rc = pcim_enable_device(pdev);
2709 /* prepare and activate SFF host */
2710 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2713 host->private_data = host_priv;
2715 pci_set_master(pdev);
2716 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2719 devres_remove_group(&pdev->dev, NULL);
2721 devres_release_group(&pdev->dev, NULL);
2726 #endif /* CONFIG_PCI */
2728 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
2729 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2730 EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
2731 EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
2732 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
2733 EXPORT_SYMBOL_GPL(ata_sff_check_status);
2734 EXPORT_SYMBOL_GPL(ata_sff_altstatus);
2735 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
2736 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
2737 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
2738 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
2739 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
2740 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
2741 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
2742 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
2743 EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
2744 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
2745 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
2746 EXPORT_SYMBOL_GPL(ata_sff_host_intr);
2747 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
2748 EXPORT_SYMBOL_GPL(ata_sff_freeze);
2749 EXPORT_SYMBOL_GPL(ata_sff_thaw);
2750 EXPORT_SYMBOL_GPL(ata_sff_prereset);
2751 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
2752 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2753 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2754 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2755 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2756 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2757 EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
2758 EXPORT_SYMBOL_GPL(ata_sff_port_start);
2759 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2760 EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
2761 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2762 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2763 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2764 EXPORT_SYMBOL_GPL(ata_bmdma_status);
2765 EXPORT_SYMBOL_GPL(ata_bus_reset);
2767 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
2768 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
2769 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2770 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2771 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2772 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2773 #endif /* CONFIG_PCI */