2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 * An ATA driver for the legacy ATA ports.
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
29 * Unsupported but docs exist:
30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
33 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
34 * on PC class systems. There are three hybrid devices that are exceptions
35 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
36 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
38 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
39 * opti82c465mv/promise 20230c/20630
41 * Use the autospeed and pio_mask options with:
42 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
43 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
44 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
45 * Winbond W83759A, Promise PDC20230-B
47 * For now use autospeed and pio_mask as above with the W83759A. This may
51 * Merge existing pata_qdi driver
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <scsi/scsi_host.h>
62 #include <linux/ata.h>
63 #include <linux/libata.h>
64 #include <linux/platform_device.h>
66 #define DRV_NAME "pata_legacy"
67 #define DRV_VERSION "0.5.3"
71 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
72 static int legacy_irq[NR_HOST] = { 15, 14, 11, 10, 8, 12 };
79 struct platform_device *platform_dev;
83 static struct legacy_data legacy_data[NR_HOST];
84 static struct ata_host *legacy_host[NR_HOST];
85 static int nr_legacy_host;
88 static int probe_all; /* Set to check all ISA port ranges */
89 static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */
90 static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */
91 static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */
92 static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */
93 static int autospeed; /* Chip present which snoops speed changes */
94 static int pio_mask = 0x1F; /* PIO range for autospeed devices */
97 * legacy_set_mode - mode setting
99 * @unused: Device that failed when error is returned
101 * Use a non standard set_mode function. We don't want to be tuned.
103 * The BIOS configured everything. Our job is not to fiddle. Just use
104 * whatever PIO the hardware is using and leave it at that. When we
105 * get some kind of nice user driven API for control then we can
106 * expand on this as per hdparm in the base kernel.
109 static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused)
113 for (i = 0; i < ATA_MAX_DEVICES; i++) {
114 struct ata_device *dev = &ap->device[i];
115 if (ata_dev_enabled(dev)) {
116 dev->pio_mode = XFER_PIO_0;
117 dev->xfer_mode = XFER_PIO_0;
118 dev->xfer_shift = ATA_SHIFT_PIO;
119 dev->flags |= ATA_DFLAG_PIO;
125 static struct scsi_host_template legacy_sht = {
126 .module = THIS_MODULE,
128 .ioctl = ata_scsi_ioctl,
129 .queuecommand = ata_scsi_queuecmd,
130 .can_queue = ATA_DEF_QUEUE,
131 .this_id = ATA_SHT_THIS_ID,
132 .sg_tablesize = LIBATA_MAX_PRD,
133 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
134 .emulated = ATA_SHT_EMULATED,
135 .use_clustering = ATA_SHT_USE_CLUSTERING,
136 .proc_name = DRV_NAME,
137 .dma_boundary = ATA_DMA_BOUNDARY,
138 .slave_configure = ata_scsi_slave_config,
139 .slave_destroy = ata_scsi_slave_destroy,
140 .bios_param = ata_std_bios_param,
144 * These ops are used if the user indicates the hardware
145 * snoops the commands to decide on the mode and handles the
146 * mode selection "magically" itself. Several legacy controllers
147 * do this. The mode range can be set if it is not 0x1F by setting
151 static struct ata_port_operations simple_port_ops = {
152 .port_disable = ata_port_disable,
153 .tf_load = ata_tf_load,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .exec_command = ata_exec_command,
157 .dev_select = ata_std_dev_select,
159 .freeze = ata_bmdma_freeze,
160 .thaw = ata_bmdma_thaw,
161 .error_handler = ata_bmdma_error_handler,
162 .post_internal_cmd = ata_bmdma_post_internal_cmd,
164 .qc_prep = ata_qc_prep,
165 .qc_issue = ata_qc_issue_prot,
167 .data_xfer = ata_data_xfer_noirq,
169 .irq_handler = ata_interrupt,
170 .irq_clear = ata_bmdma_irq_clear,
171 .irq_on = ata_irq_on,
172 .irq_ack = ata_irq_ack,
174 .port_start = ata_port_start,
177 static struct ata_port_operations legacy_port_ops = {
178 .set_mode = legacy_set_mode,
180 .port_disable = ata_port_disable,
181 .tf_load = ata_tf_load,
182 .tf_read = ata_tf_read,
183 .check_status = ata_check_status,
184 .exec_command = ata_exec_command,
185 .dev_select = ata_std_dev_select,
187 .error_handler = ata_bmdma_error_handler,
189 .qc_prep = ata_qc_prep,
190 .qc_issue = ata_qc_issue_prot,
192 .data_xfer = ata_data_xfer_noirq,
194 .irq_handler = ata_interrupt,
195 .irq_clear = ata_bmdma_irq_clear,
196 .irq_on = ata_irq_on,
197 .irq_ack = ata_irq_ack,
199 .port_start = ata_port_start,
203 * Promise 20230C and 20620 support
205 * This controller supports PIO0 to PIO2. We set PIO timings conservatively to
206 * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to
207 * controller and PIO'd to the host and not supported.
210 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
213 int pio = adev->pio_mode - XFER_PIO_0;
217 /* Safe as UP only. Force I/Os to occur together */
219 local_irq_save(flags);
221 /* Unlock the control interface */
225 outb(inb(0x1F2) | 0x80, 0x1F2);
232 while((inb(0x1F2) & 0x80) && --tries);
234 local_irq_restore(flags);
236 outb(inb(0x1F4) & 0x07, 0x1F4);
239 rt &= 0x07 << (3 * adev->devno);
241 rt |= (1 + 3 * pio) << (3 * adev->devno);
244 outb(inb(0x1F2) | 0x01, 0x1F2);
250 static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
252 struct ata_port *ap = adev->ap;
253 int slop = buflen & 3;
256 if (ata_id_has_dword_io(adev->id)) {
257 local_irq_save(flags);
259 /* Perform the 32bit I/O synchronization sequence */
260 ioread8(ap->ioaddr.nsect_addr);
261 ioread8(ap->ioaddr.nsect_addr);
262 ioread8(ap->ioaddr.nsect_addr);
267 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
269 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
271 if (unlikely(slop)) {
274 memcpy(&pad, buf + buflen - slop, slop);
275 pad = le32_to_cpu(pad);
276 iowrite32(pad, ap->ioaddr.data_addr);
278 pad = ioread32(ap->ioaddr.data_addr);
279 pad = cpu_to_le16(pad);
280 memcpy(buf + buflen - slop, &pad, slop);
283 local_irq_restore(flags);
286 ata_data_xfer_noirq(adev, buf, buflen, write_data);
289 static struct ata_port_operations pdc20230_port_ops = {
290 .set_piomode = pdc20230_set_piomode,
292 .port_disable = ata_port_disable,
293 .tf_load = ata_tf_load,
294 .tf_read = ata_tf_read,
295 .check_status = ata_check_status,
296 .exec_command = ata_exec_command,
297 .dev_select = ata_std_dev_select,
299 .error_handler = ata_bmdma_error_handler,
301 .qc_prep = ata_qc_prep,
302 .qc_issue = ata_qc_issue_prot,
304 .data_xfer = pdc_data_xfer_vlb,
306 .irq_handler = ata_interrupt,
307 .irq_clear = ata_bmdma_irq_clear,
308 .irq_on = ata_irq_on,
309 .irq_ack = ata_irq_ack,
311 .port_start = ata_port_start,
315 * Holtek 6560A support
317 * This controller supports PIO0 to PIO2 (no IORDY even though higher timings
321 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
326 /* Get the timing data in cycles. For now play safe at 50Mhz */
327 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
329 active = FIT(t.active, 2, 15);
330 recover = FIT(t.recover, 4, 15);
337 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
338 ioread8(ap->ioaddr.status_addr);
341 static struct ata_port_operations ht6560a_port_ops = {
342 .set_piomode = ht6560a_set_piomode,
344 .port_disable = ata_port_disable,
345 .tf_load = ata_tf_load,
346 .tf_read = ata_tf_read,
347 .check_status = ata_check_status,
348 .exec_command = ata_exec_command,
349 .dev_select = ata_std_dev_select,
351 .error_handler = ata_bmdma_error_handler,
353 .qc_prep = ata_qc_prep,
354 .qc_issue = ata_qc_issue_prot,
356 .data_xfer = ata_data_xfer, /* Check vlb/noirq */
358 .irq_handler = ata_interrupt,
359 .irq_clear = ata_bmdma_irq_clear,
360 .irq_on = ata_irq_on,
361 .irq_ack = ata_irq_ack,
363 .port_start = ata_port_start,
367 * Holtek 6560B support
369 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting
370 * unless we see an ATAPI device in which case we force it off.
372 * FIXME: need to implement 2nd channel support.
375 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
380 /* Get the timing data in cycles. For now play safe at 50Mhz */
381 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
383 active = FIT(t.active, 2, 15);
384 recover = FIT(t.recover, 2, 16);
392 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
394 if (adev->class != ATA_DEV_ATA) {
395 u8 rconf = inb(0x3E6);
401 ioread8(ap->ioaddr.status_addr);
404 static struct ata_port_operations ht6560b_port_ops = {
405 .set_piomode = ht6560b_set_piomode,
407 .port_disable = ata_port_disable,
408 .tf_load = ata_tf_load,
409 .tf_read = ata_tf_read,
410 .check_status = ata_check_status,
411 .exec_command = ata_exec_command,
412 .dev_select = ata_std_dev_select,
414 .error_handler = ata_bmdma_error_handler,
416 .qc_prep = ata_qc_prep,
417 .qc_issue = ata_qc_issue_prot,
419 .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */
421 .irq_handler = ata_interrupt,
422 .irq_clear = ata_bmdma_irq_clear,
423 .irq_on = ata_irq_on,
424 .irq_ack = ata_irq_ack,
426 .port_start = ata_port_start,
430 * Opti core chipset helpers
434 * opti_syscfg - read OPTI chipset configuration
435 * @reg: Configuration register to read
437 * Returns the value of an OPTI system board configuration register.
440 static u8 opti_syscfg(u8 reg)
445 /* Uniprocessor chipset and must force cycles adjancent */
446 local_irq_save(flags);
449 local_irq_restore(flags);
456 * This controller supports PIO0 to PIO3.
459 static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev)
461 u8 active, recover, setup;
463 struct ata_device *pair = ata_dev_pair(adev);
465 int khz[4] = { 50000, 40000, 33000, 25000 };
468 /* Enter configuration mode */
469 ioread16(ap->ioaddr.error_addr);
470 ioread16(ap->ioaddr.error_addr);
471 iowrite8(3, ap->ioaddr.nsect_addr);
473 /* Read VLB clock strapping */
474 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
476 /* Get the timing data in cycles */
477 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
479 /* Setup timing is shared */
481 struct ata_timing tp;
482 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
484 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
487 active = FIT(t.active, 2, 17) - 2;
488 recover = FIT(t.recover, 1, 16) - 1;
489 setup = FIT(t.setup, 1, 4) - 1;
491 /* Select the right timing bank for write timing */
492 rc = ioread8(ap->ioaddr.lbal_addr);
494 rc |= (adev->devno << 7);
495 iowrite8(rc, ap->ioaddr.lbal_addr);
497 /* Write the timings */
498 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
500 /* Select the right bank for read timings, also
501 load the shared timings for address */
502 rc = ioread8(ap->ioaddr.device_addr);
504 rc |= adev->devno; /* Index select */
505 rc |= (setup << 4) | 0x04;
506 iowrite8(rc, ap->ioaddr.device_addr);
508 /* Load the read timings */
509 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
511 /* Ensure the timing register mode is right */
512 rc = ioread8(ap->ioaddr.lbal_addr);
515 iowrite8(rc, ap->ioaddr.lbal_addr);
517 /* Exit command mode */
518 iowrite8(0x83, ap->ioaddr.nsect_addr);
522 static struct ata_port_operations opti82c611a_port_ops = {
523 .set_piomode = opti82c611a_set_piomode,
525 .port_disable = ata_port_disable,
526 .tf_load = ata_tf_load,
527 .tf_read = ata_tf_read,
528 .check_status = ata_check_status,
529 .exec_command = ata_exec_command,
530 .dev_select = ata_std_dev_select,
532 .error_handler = ata_bmdma_error_handler,
534 .qc_prep = ata_qc_prep,
535 .qc_issue = ata_qc_issue_prot,
537 .data_xfer = ata_data_xfer,
539 .irq_handler = ata_interrupt,
540 .irq_clear = ata_bmdma_irq_clear,
541 .irq_on = ata_irq_on,
542 .irq_ack = ata_irq_ack,
544 .port_start = ata_port_start,
550 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
551 * version is dual channel but doesn't have a lot of unique registers.
554 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
556 u8 active, recover, setup;
558 struct ata_device *pair = ata_dev_pair(adev);
560 int khz[4] = { 50000, 40000, 33000, 25000 };
565 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
567 /* Enter configuration mode */
568 ioread16(ap->ioaddr.error_addr);
569 ioread16(ap->ioaddr.error_addr);
570 iowrite8(3, ap->ioaddr.nsect_addr);
572 /* Read VLB clock strapping */
573 clock = 1000000000 / khz[sysclk];
575 /* Get the timing data in cycles */
576 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
578 /* Setup timing is shared */
580 struct ata_timing tp;
581 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
583 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
586 active = FIT(t.active, 2, 17) - 2;
587 recover = FIT(t.recover, 1, 16) - 1;
588 setup = FIT(t.setup, 1, 4) - 1;
590 /* Select the right timing bank for write timing */
591 rc = ioread8(ap->ioaddr.lbal_addr);
593 rc |= (adev->devno << 7);
594 iowrite8(rc, ap->ioaddr.lbal_addr);
596 /* Write the timings */
597 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
599 /* Select the right bank for read timings, also
600 load the shared timings for address */
601 rc = ioread8(ap->ioaddr.device_addr);
603 rc |= adev->devno; /* Index select */
604 rc |= (setup << 4) | 0x04;
605 iowrite8(rc, ap->ioaddr.device_addr);
607 /* Load the read timings */
608 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
610 /* Ensure the timing register mode is right */
611 rc = ioread8(ap->ioaddr.lbal_addr);
614 iowrite8(rc, ap->ioaddr.lbal_addr);
616 /* Exit command mode */
617 iowrite8(0x83, ap->ioaddr.nsect_addr);
619 /* We need to know this for quad device on the MVB */
620 ap->host->private_data = ap;
624 * opt82c465mv_qc_issue_prot - command issue
625 * @qc: command pending
627 * Called when the libata layer is about to issue a command. We wrap
628 * this interface so that we can load the correct ATA timings. The
629 * MVB has a single set of timing registers and these are shared
630 * across channels. As there are two registers we really ought to
631 * track the last two used values as a sort of register window. For
632 * now we just reload on a channel switch. On the single channel
633 * setup this condition never fires so we do nothing extra.
635 * FIXME: dual channel needs ->serialize support
638 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
640 struct ata_port *ap = qc->ap;
641 struct ata_device *adev = qc->dev;
643 /* If timings are set and for the wrong channel (2nd test is
644 due to a libata shortcoming and will eventually go I hope) */
645 if (ap->host->private_data != ap->host
646 && ap->host->private_data != NULL)
647 opti82c46x_set_piomode(ap, adev);
649 return ata_qc_issue_prot(qc);
652 static struct ata_port_operations opti82c46x_port_ops = {
653 .set_piomode = opti82c46x_set_piomode,
655 .port_disable = ata_port_disable,
656 .tf_load = ata_tf_load,
657 .tf_read = ata_tf_read,
658 .check_status = ata_check_status,
659 .exec_command = ata_exec_command,
660 .dev_select = ata_std_dev_select,
662 .error_handler = ata_bmdma_error_handler,
664 .qc_prep = ata_qc_prep,
665 .qc_issue = opti82c46x_qc_issue_prot,
667 .data_xfer = ata_data_xfer,
669 .irq_handler = ata_interrupt,
670 .irq_clear = ata_bmdma_irq_clear,
671 .irq_on = ata_irq_on,
672 .irq_ack = ata_irq_ack,
674 .port_start = ata_port_start,
679 * legacy_init_one - attach a legacy interface
681 * @io: I/O port start
682 * @ctrl: control port
683 * @irq: interrupt line
685 * Register an ISA bus IDE interface. Such interfaces are PIO and we
686 * assume do not support IRQ sharing.
689 static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq)
691 struct legacy_data *ld = &legacy_data[nr_legacy_host];
692 struct ata_probe_ent ae;
693 struct platform_device *pdev;
694 struct ata_port_operations *ops = &legacy_port_ops;
695 void __iomem *io_addr, *ctrl_addr;
696 int pio_modes = pio_mask;
697 u32 mask = (1 << port);
700 pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0);
702 return PTR_ERR(pdev);
705 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
706 devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL)
710 io_addr = devm_ioport_map(&pdev->dev, io, 8);
711 ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1);
712 if (!io_addr || !ctrl_addr)
715 if (ht6560a & mask) {
716 ops = &ht6560a_port_ops;
719 if (ht6560b & mask) {
720 ops = &ht6560b_port_ops;
723 if (opti82c611a & mask) {
724 ops = &opti82c611a_port_ops;
727 if (opti82c46x & mask) {
728 ops = &opti82c46x_port_ops;
732 /* Probe for automatically detectable controllers */
734 if (io == 0x1F0 && ops == &legacy_port_ops) {
737 local_irq_save(flags);
741 outb(inb(0x1F2) | 0x80, 0x1F2);
748 if ((inb(0x1F2) & 0x80) == 0) {
749 /* PDC20230c or 20630 ? */
750 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n");
752 ops = &pdc20230_port_ops;
759 if (inb(0x1F2) == 0x00) {
760 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n");
763 local_irq_restore(flags);
767 /* Chip does mode setting by command snooping */
768 if (ops == &legacy_port_ops && (autospeed & mask))
769 ops = &simple_port_ops;
770 memset(&ae, 0, sizeof(struct ata_probe_ent));
771 INIT_LIST_HEAD(&ae.node);
774 ae.sht = &legacy_sht;
776 ae.pio_mask = pio_modes;
779 ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
780 ae.port[0].cmd_addr = io_addr;
781 ae.port[0].altstatus_addr = ctrl_addr;
782 ae.port[0].ctl_addr = ctrl_addr;
783 ata_std_ports(&ae.port[0]);
784 ae.private_data = ld;
787 if (!ata_device_add(&ae))
790 legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev);
791 ld->platform_dev = pdev;
795 platform_device_unregister(pdev);
800 * legacy_check_special_cases - ATA special cases
801 * @p: PCI device to check
802 * @master: set this if we find an ATA master
803 * @master: set this if we find an ATA secondary
805 * A small number of vendors implemented early PCI ATA interfaces on bridge logic
806 * without the ATA interface being PCI visible. Where we have a matching PCI driver
807 * we must skip the relevant device here. If we don't know about it then the legacy
808 * driver is the right driver anyway.
811 static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary)
813 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
814 if (p->vendor == 0x1078 && p->device == 0x0000) {
815 *primary = *secondary = 1;
818 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
819 if (p->vendor == 0x1078 && p->device == 0x0002) {
820 *primary = *secondary = 1;
823 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
824 if (p->vendor == 0x8086 && p->device == 0x1234) {
826 pci_read_config_word(p, 0x6C, &r);
827 if (r & 0x8000) { /* ATA port enabled */
839 * legacy_init - attach legacy interfaces
841 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
842 * Right now we do not scan the ide0 and ide1 address but should do so
843 * for non PCI systems or systems with no PCI IDE legacy mode devices.
844 * If you fix that note there are special cases to consider like VLB
845 * drivers and CS5510/20.
848 static __init int legacy_init(void)
854 int last_port = NR_HOST;
856 struct pci_dev *p = NULL;
858 for_each_pci_dev(p) {
860 /* Check for any overlap of the system ATA mappings. Native mode controllers
861 stuck on these addresses or some devices in 'raid' mode won't be found by
862 the storage class test */
863 for (r = 0; r < 6; r++) {
864 if (pci_resource_start(p, r) == 0x1f0)
866 if (pci_resource_start(p, r) == 0x170)
869 /* Check for special cases */
870 legacy_check_special_cases(p, &primary, &secondary);
872 /* If PCI bus is present then don't probe for tertiary legacy ports */
877 /* If an OPTI 82C46X is present find out where the channels are */
879 static const char *optis[4] = {
884 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
886 opti82c46x = 3; /* Assume master and slave first */
887 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
889 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
890 ctrl = opti_syscfg(0xAC);
891 /* Check enabled and this port is the 465MV port. On the
892 MVB we may have two channels */
895 opti82c46x = 2; /* Slave */
897 opti82c46x = 1; /* Master */
899 opti82c46x = 3; /* Master and Slave */
905 for (i = 0; i < last_port; i++) {
906 /* Skip primary if we have seen a PCI one */
907 if (i == 0 && primary == 1)
909 /* Skip secondary if we have seen a PCI one */
910 if (i == 1 && secondary == 1)
912 if (legacy_init_one(i, legacy_port[i],
913 legacy_port[i] + 0x0206,
922 static __exit void legacy_exit(void)
926 for (i = 0; i < nr_legacy_host; i++) {
927 struct legacy_data *ld = &legacy_data[i];
929 ata_host_detach(legacy_host[i]);
930 platform_device_unregister(ld->platform_dev);
932 release_region(ld->timing, 2);
936 MODULE_AUTHOR("Alan Cox");
937 MODULE_DESCRIPTION("low-level driver for legacy ATA");
938 MODULE_LICENSE("GPL");
939 MODULE_VERSION(DRV_VERSION);
941 module_param(probe_all, int, 0);
942 module_param(autospeed, int, 0);
943 module_param(ht6560a, int, 0);
944 module_param(ht6560b, int, 0);
945 module_param(opti82c611a, int, 0);
946 module_param(opti82c46x, int, 0);
947 module_param(pio_mask, int, 0);
949 module_init(legacy_init);
950 module_exit(legacy_exit);