drivers/ata/sata_sx4.c

   1 /*
   2  *  sata_sx4.c - Promise SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2004 Red Hat, Inc.
   9  *
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; see the file COPYING.  If not, write to
  23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  *
  26  *  libata documentation is available via 'make {ps|pdf}docs',
  27  *  as Documentation/DocBook/libata.*
  28  *
  29  *  Hardware documentation available under NDA.
  30  *
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <linux/init.h>
  37 #include <linux/blkdev.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/device.h>
  41 #include <scsi/scsi_host.h>
  42 #include <scsi/scsi_cmnd.h>
  43 #include <linux/libata.h>
  44 #include "sata_promise.h"
  45
  46 #define DRV_NAME        "sata_sx4"
  47 #define DRV_VERSION     "0.11"
  48
  49
  50 enum {
  51         PDC_MMIO_BAR            = 3,
  52         PDC_DIMM_BAR            = 4,
  53
  54         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
  55
  56         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
  57         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
  58         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
  59         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
  60
  61         PDC_20621_SEQCTL        = 0x400,
  62         PDC_20621_SEQMASK       = 0x480,
  63         PDC_20621_GENERAL_CTL   = 0x484,
  64         PDC_20621_PAGE_SIZE     = (32 * 1024),
  65
  66         /* chosen, not constant, values; we design our own DIMM mem map */
  67         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
  68         PDC_20621_DIMM_BASE     = 0x00200000,
  69         PDC_20621_DIMM_DATA     = (64 * 1024),
  70         PDC_DIMM_DATA_STEP      = (256 * 1024),
  71         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
  72         PDC_DIMM_HOST_PRD       = (6 * 1024),
  73         PDC_DIMM_HOST_PKT       = (128 * 0),
  74         PDC_DIMM_HPKT_PRD       = (128 * 1),
  75         PDC_DIMM_ATA_PKT        = (128 * 2),
  76         PDC_DIMM_APKT_PRD       = (128 * 3),
  77         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
  78         PDC_PAGE_WINDOW         = 0x40,
  79         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
  80                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  81         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  82
  83         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
  84
  85         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  86                                   (1<<23),
  87
  88         board_20621             = 0,    /* FastTrak S150 SX4 */
  89
  90         PDC_MASK_INT            = (1 << 10), /* HDMA/ATA mask int */
  91         PDC_RESET               = (1 << 11), /* HDMA/ATA reset */
  92
  93         PDC_MAX_HDMA            = 32,
  94         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
  95
  96         PDC_DIMM0_SPD_DEV_ADDRESS       = 0x50,
  97         PDC_DIMM1_SPD_DEV_ADDRESS       = 0x51,
  98         PDC_I2C_CONTROL                 = 0x48,
  99         PDC_I2C_ADDR_DATA               = 0x4C,
 100         PDC_DIMM0_CONTROL               = 0x80,
 101         PDC_DIMM1_CONTROL               = 0x84,
 102         PDC_SDRAM_CONTROL               = 0x88,
 103         PDC_I2C_WRITE                   = 0,            /* master -> slave */
 104         PDC_I2C_READ                    = (1 << 6),     /* master <- slave */
 105         PDC_I2C_START                   = (1 << 7),     /* start I2C proto */
 106         PDC_I2C_MASK_INT                = (1 << 5),     /* mask I2C interrupt */
 107         PDC_I2C_COMPLETE                = (1 << 16),    /* I2C normal compl. */
 108         PDC_I2C_NO_ACK                  = (1 << 20),    /* slave no-ack addr */
 109         PDC_DIMM_SPD_SUBADDRESS_START   = 0x00,
 110         PDC_DIMM_SPD_SUBADDRESS_END     = 0x7F,
 111         PDC_DIMM_SPD_ROW_NUM            = 3,
 112         PDC_DIMM_SPD_COLUMN_NUM         = 4,
 113         PDC_DIMM_SPD_MODULE_ROW         = 5,
 114         PDC_DIMM_SPD_TYPE               = 11,
 115         PDC_DIMM_SPD_FRESH_RATE         = 12,
 116         PDC_DIMM_SPD_BANK_NUM           = 17,
 117         PDC_DIMM_SPD_CAS_LATENCY        = 18,
 118         PDC_DIMM_SPD_ATTRIBUTE          = 21,
 119         PDC_DIMM_SPD_ROW_PRE_CHARGE     = 27,
 120         PDC_DIMM_SPD_ROW_ACTIVE_DELAY   = 28,
 121         PDC_DIMM_SPD_RAS_CAS_DELAY      = 29,
 122         PDC_DIMM_SPD_ACTIVE_PRECHARGE   = 30,
 123         PDC_DIMM_SPD_SYSTEM_FREQ        = 126,
 124         PDC_CTL_STATUS                  = 0x08,
 125         PDC_DIMM_WINDOW_CTLR            = 0x0C,
 126         PDC_TIME_CONTROL                = 0x3C,
 127         PDC_TIME_PERIOD                 = 0x40,
 128         PDC_TIME_COUNTER                = 0x44,
 129         PDC_GENERAL_CTLR                = 0x484,
 130         PCI_PLL_INIT                    = 0x8A531824,
 131         PCI_X_TCOUNT                    = 0xEE1E5CFF,
 132
 133         /* PDC_TIME_CONTROL bits */
 134         PDC_TIMER_BUZZER                = (1 << 10),
 135         PDC_TIMER_MODE_PERIODIC         = 0,            /* bits 9:8 == 00 */
 136         PDC_TIMER_MODE_ONCE             = (1 << 8),     /* bits 9:8 == 01 */
 137         PDC_TIMER_ENABLE                = (1 << 7),
 138         PDC_TIMER_MASK_INT              = (1 << 5),
 139         PDC_TIMER_SEQ_MASK              = 0x1f,         /* SEQ ID for timer */
 140         PDC_TIMER_DEFAULT               = PDC_TIMER_MODE_ONCE |
 141                                           PDC_TIMER_ENABLE |
 142                                           PDC_TIMER_MASK_INT,
 143 };
 144
 145
 146 struct pdc_port_priv {
 147         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
 148         u8                      *pkt;
 149         dma_addr_t              pkt_dma;
 150 };
 151
 152 struct pdc_host_priv {
 153         unsigned int            doing_hdma;
 154         unsigned int            hdma_prod;
 155         unsigned int            hdma_cons;
 156         struct {
 157                 struct ata_queued_cmd *qc;
 158                 unsigned int    seq;
 159                 unsigned long   pkt_ofs;
 160         } hdma[32];
 161 };
 162
 163
 164 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 165 static void pdc_eng_timeout(struct ata_port *ap);
 166 static void pdc_20621_phy_reset (struct ata_port *ap);
 167 static int pdc_port_start(struct ata_port *ap);
 168 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
 169 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 170 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 171 static unsigned int pdc20621_dimm_init(struct ata_host *host);
 172 static int pdc20621_detect_dimm(struct ata_host *host);
 173 static unsigned int pdc20621_i2c_read(struct ata_host *host,
 174                                       u32 device, u32 subaddr, u32 *pdata);
 175 static int pdc20621_prog_dimm0(struct ata_host *host);
 176 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
 177 #ifdef ATA_VERBOSE_DEBUG
 178 static void pdc20621_get_from_dimm(struct ata_host *host,
 179                                    void *psource, u32 offset, u32 size);
 180 #endif
 181 static void pdc20621_put_to_dimm(struct ata_host *host,
 182                                  void *psource, u32 offset, u32 size);
 183 static void pdc20621_irq_clear(struct ata_port *ap);
 184 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
 185
 186
 187 static struct scsi_host_template pdc_sata_sht = {
 188         .module                 = THIS_MODULE,
 189         .name                   = DRV_NAME,
 190         .ioctl                  = ata_scsi_ioctl,
 191         .queuecommand           = ata_scsi_queuecmd,
 192         .can_queue              = ATA_DEF_QUEUE,
 193         .this_id                = ATA_SHT_THIS_ID,
 194         .sg_tablesize           = LIBATA_MAX_PRD,
 195         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 196         .emulated               = ATA_SHT_EMULATED,
 197         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 198         .proc_name              = DRV_NAME,
 199         .dma_boundary           = ATA_DMA_BOUNDARY,
 200         .slave_configure        = ata_scsi_slave_config,
 201         .slave_destroy          = ata_scsi_slave_destroy,
 202         .bios_param             = ata_std_bios_param,
 203 };
 204
 205 static const struct ata_port_operations pdc_20621_ops = {
 206         .port_disable           = ata_port_disable,
 207         .tf_load                = pdc_tf_load_mmio,
 208         .tf_read                = ata_tf_read,
 209         .check_status           = ata_check_status,
 210         .exec_command           = pdc_exec_command_mmio,
 211         .dev_select             = ata_std_dev_select,
 212         .phy_reset              = pdc_20621_phy_reset,
 213         .qc_prep                = pdc20621_qc_prep,
 214         .qc_issue               = pdc20621_qc_issue_prot,
 215         .data_xfer              = ata_data_xfer,
 216         .eng_timeout            = pdc_eng_timeout,
 217         .irq_clear              = pdc20621_irq_clear,
 218         .irq_on                 = ata_irq_on,
 219         .irq_ack                = ata_irq_ack,
 220         .port_start             = pdc_port_start,
 221 };
 222
 223 static const struct ata_port_info pdc_port_info[] = {
 224         /* board_20621 */
 225         {
 226                 .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 227                                   ATA_FLAG_SRST | ATA_FLAG_MMIO |
 228                                   ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
 229                 .pio_mask       = 0x1f, /* pio0-4 */
 230                 .mwdma_mask     = 0x07, /* mwdma0-2 */
 231                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
 232                 .port_ops       = &pdc_20621_ops,
 233         },
 234
 235 };
 236
 237 static const struct pci_device_id pdc_sata_pci_tbl[] = {
 238         { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
 239
 240         { }     /* terminate list */
 241 };
 242
 243 static struct pci_driver pdc_sata_pci_driver = {
 244         .name                   = DRV_NAME,
 245         .id_table               = pdc_sata_pci_tbl,
 246         .probe                  = pdc_sata_init_one,
 247         .remove                 = ata_pci_remove_one,
 248 };
 249
 250
 251 static int pdc_port_start(struct ata_port *ap)
 252 {
 253         struct device *dev = ap->host->dev;
 254         struct pdc_port_priv *pp;
 255         int rc;
 256
 257         rc = ata_port_start(ap);
 258         if (rc)
 259                 return rc;
 260
 261         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
 262         if (!pp)
 263                 return -ENOMEM;
 264
 265         pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
 266         if (!pp->pkt)
 267                 return -ENOMEM;
 268
 269         ap->private_data = pp;
 270
 271         return 0;
 272 }
 273
 274 static void pdc_20621_phy_reset (struct ata_port *ap)
 275 {
 276         VPRINTK("ENTER\n");
 277         ap->cbl = ATA_CBL_SATA;
 278         ata_port_probe(ap);
 279         ata_bus_reset(ap);
 280 }
 281
 282 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
 283                                            unsigned int portno,
 284                                            unsigned int total_len)
 285 {
 286         u32 addr;
 287         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
 288         u32 *buf32 = (u32 *) buf;
 289
 290         /* output ATA packet S/G table */
 291         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 292                (PDC_DIMM_DATA_STEP * portno);
 293         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
 294         buf32[dw] = cpu_to_le32(addr);
 295         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 296
 297         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
 298                 PDC_20621_DIMM_BASE +
 299                        (PDC_DIMM_WINDOW_STEP * portno) +
 300                        PDC_DIMM_APKT_PRD,
 301                 buf32[dw], buf32[dw + 1]);
 302 }
 303
 304 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
 305                                             unsigned int portno,
 306                                             unsigned int total_len)
 307 {
 308         u32 addr;
 309         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
 310         u32 *buf32 = (u32 *) buf;
 311
 312         /* output Host DMA packet S/G table */
 313         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 314                (PDC_DIMM_DATA_STEP * portno);
 315
 316         buf32[dw] = cpu_to_le32(addr);
 317         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 318
 319         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
 320                 PDC_20621_DIMM_BASE +
 321                        (PDC_DIMM_WINDOW_STEP * portno) +
 322                        PDC_DIMM_HPKT_PRD,
 323                 buf32[dw], buf32[dw + 1]);
 324 }
 325
 326 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 327                                             unsigned int devno, u8 *buf,
 328                                             unsigned int portno)
 329 {
 330         unsigned int i, dw;
 331         u32 *buf32 = (u32 *) buf;
 332         u8 dev_reg;
 333
 334         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 335                                (PDC_DIMM_WINDOW_STEP * portno) +
 336                                PDC_DIMM_APKT_PRD;
 337         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 338
 339         i = PDC_DIMM_ATA_PKT;
 340
 341         /*
 342          * Set up ATA packet
 343          */
 344         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 345                 buf[i++] = PDC_PKT_READ;
 346         else if (tf->protocol == ATA_PROT_NODATA)
 347                 buf[i++] = PDC_PKT_NODATA;
 348         else
 349                 buf[i++] = 0;
 350         buf[i++] = 0;                   /* reserved */
 351         buf[i++] = portno + 1;          /* seq. id */
 352         buf[i++] = 0xff;                /* delay seq. id */
 353
 354         /* dimm dma S/G, and next-pkt */
 355         dw = i >> 2;
 356         if (tf->protocol == ATA_PROT_NODATA)
 357                 buf32[dw] = 0;
 358         else
 359                 buf32[dw] = cpu_to_le32(dimm_sg);
 360         buf32[dw + 1] = 0;
 361         i += 8;
 362
 363         if (devno == 0)
 364                 dev_reg = ATA_DEVICE_OBS;
 365         else
 366                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
 367
 368         /* select device */
 369         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
 370         buf[i++] = dev_reg;
 371
 372         /* device control register */
 373         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
 374         buf[i++] = tf->ctl;
 375
 376         return i;
 377 }
 378
 379 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 380                                      unsigned int portno)
 381 {
 382         unsigned int dw;
 383         u32 tmp, *buf32 = (u32 *) buf;
 384
 385         unsigned int host_sg = PDC_20621_DIMM_BASE +
 386                                (PDC_DIMM_WINDOW_STEP * portno) +
 387                                PDC_DIMM_HOST_PRD;
 388         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 389                                (PDC_DIMM_WINDOW_STEP * portno) +
 390                                PDC_DIMM_HPKT_PRD;
 391         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 392         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 393
 394         dw = PDC_DIMM_HOST_PKT >> 2;
 395
 396         /*
 397          * Set up Host DMA packet
 398          */
 399         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 400                 tmp = PDC_PKT_READ;
 401         else
 402                 tmp = 0;
 403         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
 404         tmp |= (0xff << 24);                    /* delay seq. id */
 405         buf32[dw + 0] = cpu_to_le32(tmp);
 406         buf32[dw + 1] = cpu_to_le32(host_sg);
 407         buf32[dw + 2] = cpu_to_le32(dimm_sg);
 408         buf32[dw + 3] = 0;
 409
 410         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
 411                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
 412                         PDC_DIMM_HOST_PKT,
 413                 buf32[dw + 0],
 414                 buf32[dw + 1],
 415                 buf32[dw + 2],
 416                 buf32[dw + 3]);
 417 }
 418
 419 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
 420 {
 421         struct scatterlist *sg;
 422         struct ata_port *ap = qc->ap;
 423         struct pdc_port_priv *pp = ap->private_data;
 424         void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
 425         void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
 426         unsigned int portno = ap->port_no;
 427         unsigned int i, idx, total_len = 0, sgt_len;
 428         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
 429
 430         WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
 431
 432         VPRINTK("ata%u: ENTER\n", ap->print_id);
 433
 434         /* hard-code chip #0 */
 435         mmio += PDC_CHIP0_OFS;
 436
 437         /*
 438          * Build S/G table
 439          */
 440         idx = 0;
 441         ata_for_each_sg(sg, qc) {
 442                 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
 443                 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
 444                 total_len += sg_dma_len(sg);
 445         }
 446         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
 447         sgt_len = idx * 4;
 448
 449         /*
 450          * Build ATA, host DMA packets
 451          */
 452         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 453         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
 454
 455         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 456         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 457
 458         if (qc->tf.flags & ATA_TFLAG_LBA48)
 459                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 460         else
 461                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 462
 463         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 464
 465         /* copy three S/G tables and two packets to DIMM MMIO window */
 466         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 467                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 468         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
 469                     PDC_DIMM_HOST_PRD,
 470                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
 471
 472         /* force host FIFO dump */
 473         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 474
 475         readl(dimm_mmio);       /* MMIO PCI posting flush */
 476
 477         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
 478 }
 479
 480 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
 481 {
 482         struct ata_port *ap = qc->ap;
 483         struct pdc_port_priv *pp = ap->private_data;
 484         void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
 485         void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
 486         unsigned int portno = ap->port_no;
 487         unsigned int i;
 488
 489         VPRINTK("ata%u: ENTER\n", ap->print_id);
 490
 491         /* hard-code chip #0 */
 492         mmio += PDC_CHIP0_OFS;
 493
 494         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 495
 496         if (qc->tf.flags & ATA_TFLAG_LBA48)
 497                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 498         else
 499                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 500
 501         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 502
 503         /* copy three S/G tables and two packets to DIMM MMIO window */
 504         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 505                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 506
 507         /* force host FIFO dump */
 508         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 509
 510         readl(dimm_mmio);       /* MMIO PCI posting flush */
 511
 512         VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
 513 }
 514
 515 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
 516 {
 517         switch (qc->tf.protocol) {
 518         case ATA_PROT_DMA:
 519                 pdc20621_dma_prep(qc);
 520                 break;
 521         case ATA_PROT_NODATA:
 522                 pdc20621_nodata_prep(qc);
 523                 break;
 524         default:
 525                 break;
 526         }
 527 }
 528
 529 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
 530                                  unsigned int seq,
 531                                  u32 pkt_ofs)
 532 {
 533         struct ata_port *ap = qc->ap;
 534         struct ata_host *host = ap->host;
 535         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 536
 537         /* hard-code chip #0 */
 538         mmio += PDC_CHIP0_OFS;
 539
 540         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 541         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 542
 543         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
 544         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
 545 }
 546
 547 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
 548                                 unsigned int seq,
 549                                 u32 pkt_ofs)
 550 {
 551         struct ata_port *ap = qc->ap;
 552         struct pdc_host_priv *pp = ap->host->private_data;
 553         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
 554
 555         if (!pp->doing_hdma) {
 556                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
 557                 pp->doing_hdma = 1;
 558                 return;
 559         }
 560
 561         pp->hdma[idx].qc = qc;
 562         pp->hdma[idx].seq = seq;
 563         pp->hdma[idx].pkt_ofs = pkt_ofs;
 564         pp->hdma_prod++;
 565 }
 566
 567 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 568 {
 569         struct ata_port *ap = qc->ap;
 570         struct pdc_host_priv *pp = ap->host->private_data;
 571         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
 572
 573         /* if nothing on queue, we're done */
 574         if (pp->hdma_prod == pp->hdma_cons) {
 575                 pp->doing_hdma = 0;
 576                 return;
 577         }
 578
 579         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
 580                              pp->hdma[idx].pkt_ofs);
 581         pp->hdma_cons++;
 582 }
 583
 584 #ifdef ATA_VERBOSE_DEBUG
 585 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 586 {
 587         struct ata_port *ap = qc->ap;
 588         unsigned int port_no = ap->port_no;
 589         void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
 590
 591         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 592         dimm_mmio += PDC_DIMM_HOST_PKT;
 593
 594         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
 595         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
 596         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
 597         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
 598 }
 599 #else
 600 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
 601 #endif /* ATA_VERBOSE_DEBUG */
 602
 603 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 604 {
 605         struct ata_port *ap = qc->ap;
 606         struct ata_host *host = ap->host;
 607         unsigned int port_no = ap->port_no;
 608         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 609         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 610         u8 seq = (u8) (port_no + 1);
 611         unsigned int port_ofs;
 612
 613         /* hard-code chip #0 */
 614         mmio += PDC_CHIP0_OFS;
 615
 616         VPRINTK("ata%u: ENTER\n", ap->print_id);
 617
 618         wmb();                  /* flush PRD, pkt writes */
 619
 620         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 621
 622         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
 623         if (rw && qc->tf.protocol == ATA_PROT_DMA) {
 624                 seq += 4;
 625
 626                 pdc20621_dump_hdma(qc);
 627                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
 628                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
 629                         port_ofs + PDC_DIMM_HOST_PKT,
 630                         port_ofs + PDC_DIMM_HOST_PKT,
 631                         seq);
 632         } else {
 633                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 634                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 635
 636                 writel(port_ofs + PDC_DIMM_ATA_PKT,
 637                        ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 638                 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 639                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
 640                         port_ofs + PDC_DIMM_ATA_PKT,
 641                         port_ofs + PDC_DIMM_ATA_PKT,
 642                         seq);
 643         }
 644 }
 645
 646 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
 647 {
 648         switch (qc->tf.protocol) {
 649         case ATA_PROT_DMA:
 650         case ATA_PROT_NODATA:
 651                 pdc20621_packet_start(qc);
 652                 return 0;
 653
 654         case ATA_PROT_ATAPI_DMA:
 655                 BUG();
 656                 break;
 657
 658         default:
 659                 break;
 660         }
 661
 662         return ata_qc_issue_prot(qc);
 663 }
 664
 665 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
 666                                           struct ata_queued_cmd *qc,
 667                                           unsigned int doing_hdma,
 668                                           void __iomem *mmio)
 669 {
 670         unsigned int port_no = ap->port_no;
 671         unsigned int port_ofs =
 672                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 673         u8 status;
 674         unsigned int handled = 0;
 675
 676         VPRINTK("ENTER\n");
 677
 678         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
 679             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 680
 681                 /* step two - DMA from DIMM to host */
 682                 if (doing_hdma) {
 683                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
 684                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 685                         /* get drive status; clear intr; complete txn */
 686                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 687                         ata_qc_complete(qc);
 688                         pdc20621_pop_hdma(qc);
 689                 }
 690
 691                 /* step one - exec ATA command */
 692                 else {
 693                         u8 seq = (u8) (port_no + 1 + 4);
 694                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
 695                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 696
 697                         /* submit hdma pkt */
 698                         pdc20621_dump_hdma(qc);
 699                         pdc20621_push_hdma(qc, seq,
 700                                            port_ofs + PDC_DIMM_HOST_PKT);
 701                 }
 702                 handled = 1;
 703
 704         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
 705
 706                 /* step one - DMA from host to DIMM */
 707                 if (doing_hdma) {
 708                         u8 seq = (u8) (port_no + 1);
 709                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
 710                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 711
 712                         /* submit ata pkt */
 713                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 714                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
 715                         writel(port_ofs + PDC_DIMM_ATA_PKT,
 716                                ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 717                         readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 718                 }
 719
 720                 /* step two - execute ATA command */
 721                 else {
 722                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
 723                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 724                         /* get drive status; clear intr; complete txn */
 725                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 726                         ata_qc_complete(qc);
 727                         pdc20621_pop_hdma(qc);
 728                 }
 729                 handled = 1;
 730
 731         /* command completion, but no data xfer */
 732         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
 733
 734                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 735                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
 736                 qc->err_mask |= ac_err_mask(status);
 737                 ata_qc_complete(qc);
 738                 handled = 1;
 739
 740         } else {
 741                 ap->stats.idle_irq++;
 742         }
 743
 744         return handled;
 745 }
 746
 747 static void pdc20621_irq_clear(struct ata_port *ap)
 748 {
 749         struct ata_host *host = ap->host;
 750         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 751
 752         mmio += PDC_CHIP0_OFS;
 753
 754         readl(mmio + PDC_20621_SEQMASK);
 755 }
 756
 757 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
 758 {
 759         struct ata_host *host = dev_instance;
 760         struct ata_port *ap;
 761         u32 mask = 0;
 762         unsigned int i, tmp, port_no;
 763         unsigned int handled = 0;
 764         void __iomem *mmio_base;
 765
 766         VPRINTK("ENTER\n");
 767
 768         if (!host || !host->iomap[PDC_MMIO_BAR]) {
 769                 VPRINTK("QUICK EXIT\n");
 770                 return IRQ_NONE;
 771         }
 772
 773         mmio_base = host->iomap[PDC_MMIO_BAR];
 774
 775         /* reading should also clear interrupts */
 776         mmio_base += PDC_CHIP0_OFS;
 777         mask = readl(mmio_base + PDC_20621_SEQMASK);
 778         VPRINTK("mask == 0x%x\n", mask);
 779
 780         if (mask == 0xffffffff) {
 781                 VPRINTK("QUICK EXIT 2\n");
 782                 return IRQ_NONE;
 783         }
 784         mask &= 0xffff;         /* only 16 tags possible */
 785         if (!mask) {
 786                 VPRINTK("QUICK EXIT 3\n");
 787                 return IRQ_NONE;
 788         }
 789
 790         spin_lock(&host->lock);
 791
 792         for (i = 1; i < 9; i++) {
 793                 port_no = i - 1;
 794                 if (port_no > 3)
 795                         port_no -= 4;
 796                 if (port_no >= host->n_ports)
 797                         ap = NULL;
 798                 else
 799                         ap = host->ports[port_no];
 800                 tmp = mask & (1 << i);
 801                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
 802                 if (tmp && ap &&
 803                     !(ap->flags & ATA_FLAG_DISABLED)) {
 804                         struct ata_queued_cmd *qc;
 805
 806                         qc = ata_qc_from_tag(ap, ap->active_tag);
 807                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
 808                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
 809                                                               mmio_base);
 810                 }
 811         }
 812
 813         spin_unlock(&host->lock);
 814
 815         VPRINTK("mask == 0x%x\n", mask);
 816
 817         VPRINTK("EXIT\n");
 818
 819         return IRQ_RETVAL(handled);
 820 }
 821
 822 static void pdc_eng_timeout(struct ata_port *ap)
 823 {
 824         u8 drv_stat;
 825         struct ata_host *host = ap->host;
 826         struct ata_queued_cmd *qc;
 827         unsigned long flags;
 828
 829         DPRINTK("ENTER\n");
 830
 831         spin_lock_irqsave(&host->lock, flags);
 832
 833         qc = ata_qc_from_tag(ap, ap->active_tag);
 834
 835         switch (qc->tf.protocol) {
 836         case ATA_PROT_DMA:
 837         case ATA_PROT_NODATA:
 838                 ata_port_printk(ap, KERN_ERR, "command timeout\n");
 839                 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
 840                 break;
 841
 842         default:
 843                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 844
 845                 ata_port_printk(ap, KERN_ERR,
 846                                 "unknown timeout, cmd 0x%x stat 0x%x\n",
 847                                 qc->tf.command, drv_stat);
 848
 849                 qc->err_mask |= ac_err_mask(drv_stat);
 850                 break;
 851         }
 852
 853         spin_unlock_irqrestore(&host->lock, flags);
 854         ata_eh_qc_complete(qc);
 855         DPRINTK("EXIT\n");
 856 }
 857
 858 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 859 {
 860         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 861                  tf->protocol == ATA_PROT_NODATA);
 862         ata_tf_load(ap, tf);
 863 }
 864
 865
 866 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 867 {
 868         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 869                  tf->protocol == ATA_PROT_NODATA);
 870         ata_exec_command(ap, tf);
 871 }
 872
 873
 874 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
 875 {
 876         port->cmd_addr          = base;
 877         port->data_addr         = base;
 878         port->feature_addr      =
 879         port->error_addr        = base + 0x4;
 880         port->nsect_addr        = base + 0x8;
 881         port->lbal_addr         = base + 0xc;
 882         port->lbam_addr         = base + 0x10;
 883         port->lbah_addr         = base + 0x14;
 884         port->device_addr       = base + 0x18;
 885         port->command_addr      =
 886         port->status_addr       = base + 0x1c;
 887         port->altstatus_addr    =
 888         port->ctl_addr          = base + 0x38;
 889 }
 890
 891
 892 #ifdef ATA_VERBOSE_DEBUG
 893 static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
 894                                    u32 offset, u32 size)
 895 {
 896         u32 window_size;
 897         u16 idx;
 898         u8 page_mask;
 899         long dist;
 900         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 901         void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
 902
 903         /* hard-code chip #0 */
 904         mmio += PDC_CHIP0_OFS;
 905
 906         page_mask = 0x00;
 907         window_size = 0x2000 * 4; /* 32K byte uchar size */
 908         idx = (u16) (offset / window_size);
 909
 910         writel(0x01, mmio + PDC_GENERAL_CTLR);
 911         readl(mmio + PDC_GENERAL_CTLR);
 912         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 913         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 914
 915         offset -= (idx * window_size);
 916         idx++;
 917         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
 918                 (long) (window_size - offset);
 919         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
 920                       dist);
 921
 922         psource += dist;
 923         size -= dist;
 924         for (; (long) size >= (long) window_size ;) {
 925                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 926                 readl(mmio + PDC_GENERAL_CTLR);
 927                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 928                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 929                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 930                               window_size / 4);
 931                 psource += window_size;
 932                 size -= window_size;
 933                 idx ++;
 934         }
 935
 936         if (size) {
 937                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 938                 readl(mmio + PDC_GENERAL_CTLR);
 939                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 940                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 941                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 942                               size / 4);
 943         }
 944 }
 945 #endif
 946
 947
 948 static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
 949                                  u32 offset, u32 size)
 950 {
 951         u32 window_size;
 952         u16 idx;
 953         u8 page_mask;
 954         long dist;
 955         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 956         void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
 957
 958         /* hard-code chip #0 */
 959         mmio += PDC_CHIP0_OFS;
 960
 961         page_mask = 0x00;
 962         window_size = 0x2000 * 4;       /* 32K byte uchar size */
 963         idx = (u16) (offset / window_size);
 964
 965         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 966         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 967         offset -= (idx * window_size);
 968         idx++;
 969         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
 970                 (long) (window_size - offset);
 971         memcpy_toio(dimm_mmio + offset / 4, psource, dist);
 972         writel(0x01, mmio + PDC_GENERAL_CTLR);
 973         readl(mmio + PDC_GENERAL_CTLR);
 974
 975         psource += dist;
 976         size -= dist;
 977         for (; (long) size >= (long) window_size ;) {
 978                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 979                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 980                 memcpy_toio(dimm_mmio, psource, window_size / 4);
 981                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 982                 readl(mmio + PDC_GENERAL_CTLR);
 983                 psource += window_size;
 984                 size -= window_size;
 985                 idx ++;
 986         }
 987
 988         if (size) {
 989                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 990                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 991                 memcpy_toio(dimm_mmio, psource, size / 4);
 992                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 993                 readl(mmio + PDC_GENERAL_CTLR);
 994         }
 995 }
 996
 997
 998 static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
 999                                       u32 subaddr, u32 *pdata)
1000 {
1001         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1002         u32 i2creg  = 0;
1003         u32 status;
1004         u32 count =0;
1005
1006         /* hard-code chip #0 */
1007         mmio += PDC_CHIP0_OFS;
1008
1009         i2creg |= device << 24;
1010         i2creg |= subaddr << 16;
1011
1012         /* Set the device and subaddress */
1013         writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1014         readl(mmio + PDC_I2C_ADDR_DATA);
1015
1016         /* Write Control to perform read operation, mask int */
1017         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1018                mmio + PDC_I2C_CONTROL);
1019
1020         for (count = 0; count <= 1000; count ++) {
1021                 status = readl(mmio + PDC_I2C_CONTROL);
1022                 if (status & PDC_I2C_COMPLETE) {
1023                         status = readl(mmio + PDC_I2C_ADDR_DATA);
1024                         break;
1025                 } else if (count == 1000)
1026                         return 0;
1027         }
1028
1029         *pdata = (status >> 8) & 0x000000ff;
1030         return 1;
1031 }
1032
1033
1034 static int pdc20621_detect_dimm(struct ata_host *host)
1035 {
1036         u32 data=0 ;
1037         if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1038                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1039                 if (data == 100)
1040                         return 100;
1041         } else
1042                 return 0;
1043
1044         if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1045                 if(data <= 0x75)
1046                         return 133;
1047         } else
1048                 return 0;
1049
1050         return 0;
1051 }
1052
1053
1054 static int pdc20621_prog_dimm0(struct ata_host *host)
1055 {
1056         u32 spd0[50];
1057         u32 data = 0;
1058         int size, i;
1059         u8 bdimmsize;
1060         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1061         static const struct {
1062                 unsigned int reg;
1063                 unsigned int ofs;
1064         } pdc_i2c_read_data [] = {
1065                 { PDC_DIMM_SPD_TYPE, 11 },
1066                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1067                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1068                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1069                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1070                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1071                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1072                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1073                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1074                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1075                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1076                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1077         };
1078
1079         /* hard-code chip #0 */
1080         mmio += PDC_CHIP0_OFS;
1081
1082         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1083                 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1084                                   pdc_i2c_read_data[i].reg,
1085                                   &spd0[pdc_i2c_read_data[i].ofs]);
1086
1087         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1088         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1089                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1090         data |= (((((spd0[29] > spd0[28])
1091                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1092         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1093
1094         if (spd0[18] & 0x08)
1095                 data |= ((0x03) << 14);
1096         else if (spd0[18] & 0x04)
1097                 data |= ((0x02) << 14);
1098         else if (spd0[18] & 0x01)
1099                 data |= ((0x01) << 14);
1100         else
1101                 data |= (0 << 14);
1102
1103         /*
1104            Calculate the size of bDIMMSize (power of 2) and
1105            merge the DIMM size by program start/end address.
1106         */
1107
1108         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1109         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1110         data |= (((size / 16) - 1) << 16);
1111         data |= (0 << 23);
1112         data |= 8;
1113         writel(data, mmio + PDC_DIMM0_CONTROL);
1114         readl(mmio + PDC_DIMM0_CONTROL);
1115         return size;
1116 }
1117
1118
1119 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1120 {
1121         u32 data, spd0;
1122         int error, i;
1123         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1124
1125         /* hard-code chip #0 */
1126         mmio += PDC_CHIP0_OFS;
1127
1128         /*
1129           Set To Default : DIMM Module Global Control Register (0x022259F1)
1130           DIMM Arbitration Disable (bit 20)
1131           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1132           Refresh Enable (bit 17)
1133         */
1134
1135         data = 0x022259F1;
1136         writel(data, mmio + PDC_SDRAM_CONTROL);
1137         readl(mmio + PDC_SDRAM_CONTROL);
1138
1139         /* Turn on for ECC */
1140         pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1141                           PDC_DIMM_SPD_TYPE, &spd0);
1142         if (spd0 == 0x02) {
1143                 data |= (0x01 << 16);
1144                 writel(data, mmio + PDC_SDRAM_CONTROL);
1145                 readl(mmio + PDC_SDRAM_CONTROL);
1146                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1147         }
1148
1149         /* DIMM Initialization Select/Enable (bit 18/19) */
1150         data &= (~(1<<18));
1151         data |= (1<<19);
1152         writel(data, mmio + PDC_SDRAM_CONTROL);
1153
1154         error = 1;
1155         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1156                 data = readl(mmio + PDC_SDRAM_CONTROL);
1157                 if (!(data & (1<<19))) {
1158                         error = 0;
1159                         break;
1160                 }
1161                 msleep(i*100);
1162         }
1163         return error;
1164 }
1165
1166
1167 static unsigned int pdc20621_dimm_init(struct ata_host *host)
1168 {
1169         int speed, size, length;
1170         u32 addr,spd0,pci_status;
1171         u32 tmp=0;
1172         u32 time_period=0;
1173         u32 tcount=0;
1174         u32 ticks=0;
1175         u32 clock=0;
1176         u32 fparam=0;
1177         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1178
1179         /* hard-code chip #0 */
1180         mmio += PDC_CHIP0_OFS;
1181
1182         /* Initialize PLL based upon PCI Bus Frequency */
1183
1184         /* Initialize Time Period Register */
1185         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1186         time_period = readl(mmio + PDC_TIME_PERIOD);
1187         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1188
1189         /* Enable timer */
1190         writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1191         readl(mmio + PDC_TIME_CONTROL);
1192
1193         /* Wait 3 seconds */
1194         msleep(3000);
1195
1196         /*
1197            When timer is enabled, counter is decreased every internal
1198            clock cycle.
1199         */
1200
1201         tcount = readl(mmio + PDC_TIME_COUNTER);
1202         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1203
1204         /*
1205            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1206            register should be >= (0xffffffff - 3x10^8).
1207         */
1208         if(tcount >= PCI_X_TCOUNT) {
1209                 ticks = (time_period - tcount);
1210                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1211
1212                 clock = (ticks / 300000);
1213                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1214
1215                 clock = (clock * 33);
1216                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1217
1218                 /* PLL F Param (bit 22:16) */
1219                 fparam = (1400000 / clock) - 2;
1220                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1221
1222                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1223                 pci_status = (0x8a001824 | (fparam << 16));
1224         } else
1225                 pci_status = PCI_PLL_INIT;
1226
1227         /* Initialize PLL. */
1228         VPRINTK("pci_status: 0x%x\n", pci_status);
1229         writel(pci_status, mmio + PDC_CTL_STATUS);
1230         readl(mmio + PDC_CTL_STATUS);
1231
1232         /*
1233            Read SPD of DIMM by I2C interface,
1234            and program the DIMM Module Controller.
1235         */
1236         if (!(speed = pdc20621_detect_dimm(host))) {
1237                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1238                 return 1;       /* DIMM error */
1239         }
1240         VPRINTK("Local DIMM Speed = %d\n", speed);
1241
1242         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1243         size = pdc20621_prog_dimm0(host);
1244         VPRINTK("Local DIMM Size = %dMB\n",size);
1245
1246         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1247         if (pdc20621_prog_dimm_global(host)) {
1248                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1249                 return 1;
1250         }
1251
1252 #ifdef ATA_VERBOSE_DEBUG
1253         {
1254                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1255                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1256                                  '1','.','1','0',
1257                                 '9','8','0','3','1','6','1','2',0,0};
1258                 u8 test_parttern2[40] = {0};
1259
1260                 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x10040, 40);
1261                 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x40, 40);
1262
1263                 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x10040, 40);
1264                 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
1265                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1266                        test_parttern2[1], &(test_parttern2[2]));
1267                 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x10040,
1268                                        40);
1269                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1270                        test_parttern2[1], &(test_parttern2[2]));
1271
1272                 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x40, 40);
1273                 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
1274                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1275                        test_parttern2[1], &(test_parttern2[2]));
1276         }
1277 #endif
1278
1279         /* ECC initiliazation. */
1280
1281         pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1282                           PDC_DIMM_SPD_TYPE, &spd0);
1283         if (spd0 == 0x02) {
1284                 VPRINTK("Start ECC initialization\n");
1285                 addr = 0;
1286                 length = size * 1024 * 1024;
1287                 while (addr < length) {
1288                         pdc20621_put_to_dimm(host, (void *) &tmp, addr,
1289                                              sizeof(u32));
1290                         addr += sizeof(u32);
1291                 }
1292                 VPRINTK("Finish ECC initialization\n");
1293         }
1294         return 0;
1295 }
1296
1297
1298 static void pdc_20621_init(struct ata_host *host)
1299 {
1300         u32 tmp;
1301         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1302
1303         /* hard-code chip #0 */
1304         mmio += PDC_CHIP0_OFS;
1305
1306         /*
1307          * Select page 0x40 for our 32k DIMM window
1308          */
1309         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1310         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1311         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1312
1313         /*
1314          * Reset Host DMA
1315          */
1316         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1317         tmp |= PDC_RESET;
1318         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1319         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1320
1321         udelay(10);
1322
1323         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1324         tmp &= ~PDC_RESET;
1325         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1326         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1327 }
1328
1329 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1330 {
1331         static int printed_version;
1332         const struct ata_port_info *ppi[] =
1333                 { &pdc_port_info[ent->driver_data], NULL };
1334         struct ata_host *host;
1335         void __iomem *base;
1336         struct pdc_host_priv *hpriv;
1337         int rc;
1338
1339         if (!printed_version++)
1340                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1341
1342         /* allocate host */
1343         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1344         hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1345         if (!host || !hpriv)
1346                 return -ENOMEM;
1347
1348         host->private_data = hpriv;
1349
1350         /* acquire resources and fill host */
1351         rc = pcim_enable_device(pdev);
1352         if (rc)
1353                 return rc;
1354
1355         rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1356                                 DRV_NAME);
1357         if (rc == -EBUSY)
1358                 pcim_pin_device(pdev);
1359         if (rc)
1360                 return rc;
1361         host->iomap = pcim_iomap_table(pdev);
1362
1363         base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1364         pdc_sata_setup_port(&host->ports[0]->ioaddr, base + 0x200);
1365         pdc_sata_setup_port(&host->ports[1]->ioaddr, base + 0x280);
1366         pdc_sata_setup_port(&host->ports[2]->ioaddr, base + 0x300);
1367         pdc_sata_setup_port(&host->ports[3]->ioaddr, base + 0x380);
1368
1369         /* configure and activate */
1370         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1371         if (rc)
1372                 return rc;
1373         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1374         if (rc)
1375                 return rc;
1376
1377         if (pdc20621_dimm_init(host))
1378                 return -ENOMEM;
1379         pdc_20621_init(host);
1380
1381         pci_set_master(pdev);
1382         return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1383                                  IRQF_SHARED, &pdc_sata_sht);
1384 }
1385
1386
1387 static int __init pdc_sata_init(void)
1388 {
1389         return pci_register_driver(&pdc_sata_pci_driver);
1390 }
1391
1392
1393 static void __exit pdc_sata_exit(void)
1394 {
1395         pci_unregister_driver(&pdc_sata_pci_driver);
1396 }
1397
1398
1399 MODULE_AUTHOR("Jeff Garzik");
1400 MODULE_DESCRIPTION("Promise SATA low-level driver");
1401 MODULE_LICENSE("GPL");
1402 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1403 MODULE_VERSION(DRV_VERSION);
1404
1405 module_init(pdc_sata_init);
1406 module_exit(pdc_sata_exit);