drivers/char/agp/sis-agp.c

   1 /*
   2  * SiS AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/agp_backend.h>
   9 #include <linux/delay.h>
  10 #include "agp.h"
  11
  12 #define SIS_ATTBASE     0x90
  13 #define SIS_APSIZE      0x94
  14 #define SIS_TLBCNTRL    0x97
  15 #define SIS_TLBFLUSH    0x98
  16
  17 static int __devinitdata agp_sis_force_delay = 0;
  18 static int __devinitdata agp_sis_agp_spec = -1;
  19
  20 static int sis_fetch_size(void)
  21 {
  22         u8 temp_size;
  23         int i;
  24         struct aper_size_info_8 *values;
  25
  26         pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
  27         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
  28         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
  29                 if ((temp_size == values[i].size_value) ||
  30                     ((temp_size & ~(0x07)) ==
  31                      (values[i].size_value & ~(0x07)))) {
  32                         agp_bridge->previous_size =
  33                             agp_bridge->current_size = (void *) (values + i);
  34
  35                         agp_bridge->aperture_size_idx = i;
  36                         return values[i].size;
  37                 }
  38         }
  39
  40         return 0;
  41 }
  42
  43 static void sis_tlbflush(struct agp_memory *mem)
  44 {
  45         pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
  46 }
  47
  48 static int sis_configure(void)
  49 {
  50         u32 temp;
  51         struct aper_size_info_8 *current_size;
  52
  53         current_size = A_SIZE_8(agp_bridge->current_size);
  54         pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
  55         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  56         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  57         pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
  58                                agp_bridge->gatt_bus_addr);
  59         pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
  60                               current_size->size_value);
  61         return 0;
  62 }
  63
  64 static void sis_cleanup(void)
  65 {
  66         struct aper_size_info_8 *previous_size;
  67
  68         previous_size = A_SIZE_8(agp_bridge->previous_size);
  69         pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
  70                               (previous_size->size_value & ~(0x03)));
  71 }
  72
  73 static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode)
  74 {
  75         struct pci_dev *device = NULL;
  76         u32 command;
  77         int rate;
  78
  79         printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n",
  80                 agp_bridge->major_version,
  81                 agp_bridge->minor_version,
  82                 pci_name(agp_bridge->dev));
  83
  84         pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command);
  85         command = agp_collect_device_status(bridge, mode, command);
  86         command |= AGPSTAT_AGP_ENABLE;
  87         rate = (command & 0x7) << 2;
  88
  89         for_each_pci_dev(device) {
  90                 u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
  91                 if (!agp)
  92                         continue;
  93
  94                 printk(KERN_INFO PFX "Putting AGP V3 device at %s into %dx mode\n",
  95                         pci_name(device), rate);
  96
  97                 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command);
  98
  99                 /*
 100                  * Weird: on some sis chipsets any rate change in the target
 101                  * command register triggers a 5ms screwup during which the master
 102                  * cannot be configured
 103                  */
 104                 if (device->device == bridge->dev->device) {
 105                         printk(KERN_INFO PFX "SiS delay workaround: giving bridge time to recover.\n");
 106                         msleep(10);
 107                 }
 108         }
 109 }
 110
 111 static const struct aper_size_info_8 sis_generic_sizes[7] =
 112 {
 113         {256, 65536, 6, 99},
 114         {128, 32768, 5, 83},
 115         {64, 16384, 4, 67},
 116         {32, 8192, 3, 51},
 117         {16, 4096, 2, 35},
 118         {8, 2048, 1, 19},
 119         {4, 1024, 0, 3}
 120 };
 121
 122 static struct agp_bridge_driver sis_driver = {
 123         .owner                  = THIS_MODULE,
 124         .aperture_sizes         = sis_generic_sizes,
 125         .size_type              = U8_APER_SIZE,
 126         .num_aperture_sizes     = 7,
 127         .configure              = sis_configure,
 128         .fetch_size             = sis_fetch_size,
 129         .cleanup                = sis_cleanup,
 130         .tlb_flush              = sis_tlbflush,
 131         .mask_memory            = agp_generic_mask_memory,
 132         .masks                  = NULL,
 133         .agp_enable             = agp_generic_enable,
 134         .cache_flush            = global_cache_flush,
 135         .create_gatt_table      = agp_generic_create_gatt_table,
 136         .free_gatt_table        = agp_generic_free_gatt_table,
 137         .insert_memory          = agp_generic_insert_memory,
 138         .remove_memory          = agp_generic_remove_memory,
 139         .alloc_by_type          = agp_generic_alloc_by_type,
 140         .free_by_type           = agp_generic_free_by_type,
 141         .agp_alloc_page         = agp_generic_alloc_page,
 142         .agp_destroy_page       = agp_generic_destroy_page,
 143         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 144 };
 145
 146 // chipsets that require the 'delay hack'
 147 static int sis_broken_chipsets[] __devinitdata = {
 148         PCI_DEVICE_ID_SI_648,
 149         PCI_DEVICE_ID_SI_746,
 150         0 // terminator
 151 };
 152
 153 static void __devinit sis_get_driver(struct agp_bridge_data *bridge)
 154 {
 155         int i;
 156
 157         for (i=0; sis_broken_chipsets[i]!=0; ++i)
 158                 if (bridge->dev->device==sis_broken_chipsets[i])
 159                         break;
 160
 161         if (sis_broken_chipsets[i] || agp_sis_force_delay)
 162                 sis_driver.agp_enable=sis_delayed_enable;
 163
 164         // sis chipsets that indicate less than agp3.5
 165         // are not actually fully agp3 compliant
 166         if ((agp_bridge->major_version == 3 && agp_bridge->minor_version >= 5
 167              && agp_sis_agp_spec!=0) || agp_sis_agp_spec==1) {
 168                 sis_driver.aperture_sizes = agp3_generic_sizes;
 169                 sis_driver.size_type = U16_APER_SIZE;
 170                 sis_driver.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES;
 171                 sis_driver.configure = agp3_generic_configure;
 172                 sis_driver.fetch_size = agp3_generic_fetch_size;
 173                 sis_driver.cleanup = agp3_generic_cleanup;
 174                 sis_driver.tlb_flush = agp3_generic_tlbflush;
 175         }
 176 }
 177
 178
 179 static int __devinit agp_sis_probe(struct pci_dev *pdev,
 180                                    const struct pci_device_id *ent)
 181 {
 182         struct agp_bridge_data *bridge;
 183         u8 cap_ptr;
 184
 185         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 186         if (!cap_ptr)
 187                 return -ENODEV;
 188
 189
 190         printk(KERN_INFO PFX "Detected SiS chipset - id:%i\n", pdev->device);
 191         bridge = agp_alloc_bridge();
 192         if (!bridge)
 193                 return -ENOMEM;
 194
 195         bridge->driver = &sis_driver;
 196         bridge->dev = pdev;
 197         bridge->capndx = cap_ptr;
 198
 199         get_agp_version(bridge);
 200
 201         /* Fill in the mode register */
 202         pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
 203         sis_get_driver(bridge);
 204
 205         pci_set_drvdata(pdev, bridge);
 206         return agp_add_bridge(bridge);
 207 }
 208
 209 static void __devexit agp_sis_remove(struct pci_dev *pdev)
 210 {
 211         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 212
 213         agp_remove_bridge(bridge);
 214         agp_put_bridge(bridge);
 215 }
 216
 217 #ifdef CONFIG_PM
 218
 219 static int agp_sis_suspend(struct pci_dev *pdev, pm_message_t state)
 220 {
 221         pci_save_state(pdev);
 222         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 223
 224         return 0;
 225 }
 226
 227 static int agp_sis_resume(struct pci_dev *pdev)
 228 {
 229         pci_set_power_state(pdev, PCI_D0);
 230         pci_restore_state(pdev);
 231
 232         return sis_driver.configure();
 233 }
 234
 235 #endif /* CONFIG_PM */
 236
 237 static struct pci_device_id agp_sis_pci_table[] = {
 238         {
 239                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 240                 .class_mask     = ~0,
 241                 .vendor         = PCI_VENDOR_ID_SI,
 242                 .device         = PCI_DEVICE_ID_SI_5591_AGP,
 243                 .subvendor      = PCI_ANY_ID,
 244                 .subdevice      = PCI_ANY_ID,
 245         },
 246         {
 247                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 248                 .class_mask     = ~0,
 249                 .vendor         = PCI_VENDOR_ID_SI,
 250                 .device         = PCI_DEVICE_ID_SI_530,
 251                 .subvendor      = PCI_ANY_ID,
 252                 .subdevice      = PCI_ANY_ID,
 253         },
 254         {
 255                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 256                 .class_mask     = ~0,
 257                 .vendor         = PCI_VENDOR_ID_SI,
 258                 .device         = PCI_DEVICE_ID_SI_540,
 259                 .subvendor      = PCI_ANY_ID,
 260                 .subdevice      = PCI_ANY_ID,
 261         },
 262         {
 263                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 264                 .class_mask     = ~0,
 265                 .vendor         = PCI_VENDOR_ID_SI,
 266                 .device         = PCI_DEVICE_ID_SI_550,
 267                 .subvendor      = PCI_ANY_ID,
 268                 .subdevice      = PCI_ANY_ID,
 269         },
 270         {
 271                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 272                 .class_mask     = ~0,
 273                 .vendor         = PCI_VENDOR_ID_SI,
 274                 .device         = PCI_DEVICE_ID_SI_620,
 275                 .subvendor      = PCI_ANY_ID,
 276                 .subdevice      = PCI_ANY_ID,
 277         },
 278         {
 279                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 280                 .class_mask     = ~0,
 281                 .vendor         = PCI_VENDOR_ID_SI,
 282                 .device         = PCI_DEVICE_ID_SI_630,
 283                 .subvendor      = PCI_ANY_ID,
 284                 .subdevice      = PCI_ANY_ID,
 285         },
 286         {
 287                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 288                 .class_mask     = ~0,
 289                 .vendor         = PCI_VENDOR_ID_SI,
 290                 .device         = PCI_DEVICE_ID_SI_635,
 291                 .subvendor      = PCI_ANY_ID,
 292                 .subdevice      = PCI_ANY_ID,
 293         },
 294         {
 295                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 296                 .class_mask     = ~0,
 297                 .vendor         = PCI_VENDOR_ID_SI,
 298                 .device         = PCI_DEVICE_ID_SI_645,
 299                 .subvendor      = PCI_ANY_ID,
 300                 .subdevice      = PCI_ANY_ID,
 301         },
 302         {
 303                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 304                 .class_mask     = ~0,
 305                 .vendor         = PCI_VENDOR_ID_SI,
 306                 .device         = PCI_DEVICE_ID_SI_646,
 307                 .subvendor      = PCI_ANY_ID,
 308                 .subdevice      = PCI_ANY_ID,
 309         },
 310         {
 311                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 312                 .class_mask     = ~0,
 313                 .vendor         = PCI_VENDOR_ID_SI,
 314                 .device         = PCI_DEVICE_ID_SI_648,
 315                 .subvendor      = PCI_ANY_ID,
 316                 .subdevice      = PCI_ANY_ID,
 317         },
 318         {
 319                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 320                 .class_mask     = ~0,
 321                 .vendor         = PCI_VENDOR_ID_SI,
 322                 .device         = PCI_DEVICE_ID_SI_650,
 323                 .subvendor      = PCI_ANY_ID,
 324                 .subdevice      = PCI_ANY_ID,
 325         },
 326         {
 327                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 328                 .class_mask     = ~0,
 329                 .vendor         = PCI_VENDOR_ID_SI,
 330                 .device         = PCI_DEVICE_ID_SI_651,
 331                 .subvendor      = PCI_ANY_ID,
 332                 .subdevice      = PCI_ANY_ID,
 333         },
 334         {
 335                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 336                 .class_mask     = ~0,
 337                 .vendor         = PCI_VENDOR_ID_SI,
 338                 .device         = PCI_DEVICE_ID_SI_655,
 339                 .subvendor      = PCI_ANY_ID,
 340                 .subdevice      = PCI_ANY_ID,
 341         },
 342         {
 343                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 344                 .class_mask     = ~0,
 345                 .vendor         = PCI_VENDOR_ID_SI,
 346                 .device         = PCI_DEVICE_ID_SI_661,
 347                 .subvendor      = PCI_ANY_ID,
 348                 .subdevice      = PCI_ANY_ID,
 349         },
 350         {
 351                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 352                 .class_mask     = ~0,
 353                 .vendor         = PCI_VENDOR_ID_SI,
 354                 .device         = PCI_DEVICE_ID_SI_730,
 355                 .subvendor      = PCI_ANY_ID,
 356                 .subdevice      = PCI_ANY_ID,
 357         },
 358         {
 359                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 360                 .class_mask     = ~0,
 361                 .vendor         = PCI_VENDOR_ID_SI,
 362                 .device         = PCI_DEVICE_ID_SI_735,
 363                 .subvendor      = PCI_ANY_ID,
 364                 .subdevice      = PCI_ANY_ID,
 365         },
 366         {
 367                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 368                 .class_mask     = ~0,
 369                 .vendor         = PCI_VENDOR_ID_SI,
 370                 .device         = PCI_DEVICE_ID_SI_740,
 371                 .subvendor      = PCI_ANY_ID,
 372                 .subdevice      = PCI_ANY_ID,
 373         },
 374         {
 375                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 376                 .class_mask     = ~0,
 377                 .vendor         = PCI_VENDOR_ID_SI,
 378                 .device         = PCI_DEVICE_ID_SI_741,
 379                 .subvendor      = PCI_ANY_ID,
 380                 .subdevice      = PCI_ANY_ID,
 381         },
 382         {
 383                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 384                 .class_mask     = ~0,
 385                 .vendor         = PCI_VENDOR_ID_SI,
 386                 .device         = PCI_DEVICE_ID_SI_745,
 387                 .subvendor      = PCI_ANY_ID,
 388                 .subdevice      = PCI_ANY_ID,
 389         },
 390         {
 391                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 392                 .class_mask     = ~0,
 393                 .vendor         = PCI_VENDOR_ID_SI,
 394                 .device         = PCI_DEVICE_ID_SI_746,
 395                 .subvendor      = PCI_ANY_ID,
 396                 .subdevice      = PCI_ANY_ID,
 397         },
 398         {
 399                 .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 400                 .class_mask     = ~0,
 401                 .vendor         = PCI_VENDOR_ID_SI,
 402                 .device         = PCI_DEVICE_ID_SI_760,
 403                 .subvendor      = PCI_ANY_ID,
 404                 .subdevice      = PCI_ANY_ID,
 405         },
 406         { }
 407 };
 408
 409 MODULE_DEVICE_TABLE(pci, agp_sis_pci_table);
 410
 411 static struct pci_driver agp_sis_pci_driver = {
 412         .name           = "agpgart-sis",
 413         .id_table       = agp_sis_pci_table,
 414         .probe          = agp_sis_probe,
 415         .remove         = agp_sis_remove,
 416 #ifdef CONFIG_PM
 417         .suspend        = agp_sis_suspend,
 418         .resume         = agp_sis_resume,
 419 #endif
 420 };
 421
 422 static int __init agp_sis_init(void)
 423 {
 424         if (agp_off)
 425                 return -EINVAL;
 426         return pci_register_driver(&agp_sis_pci_driver);
 427 }
 428
 429 static void __exit agp_sis_cleanup(void)
 430 {
 431         pci_unregister_driver(&agp_sis_pci_driver);
 432 }
 433
 434 module_init(agp_sis_init);
 435 module_exit(agp_sis_cleanup);
 436
 437 module_param(agp_sis_force_delay, bool, 0);
 438 MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack");
 439 module_param(agp_sis_agp_spec, int, 0);
 440 MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect");
 441 MODULE_LICENSE("GPL and additional rights");