drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/errno.h>
  51 #include <linux/signal.h>
  52 #include <linux/sched.h>
  53 #include <linux/timer.h>
  54 #include <linux/interrupt.h>
  55 #include <linux/pci.h>
  56 #include <linux/tty.h>
  57 #include <linux/tty_flip.h>
  58 #include <linux/serial.h>
  59 #include <linux/major.h>
  60 #include <linux/string.h>
  61 #include <linux/fcntl.h>
  62 #include <linux/ptrace.h>
  63 #include <linux/ioport.h>
  64 #include <linux/mm.h>
  65 #include <linux/slab.h>
  66 #include <linux/netdevice.h>
  67 #include <linux/vmalloc.h>
  68 #include <linux/init.h>
  69 #include <linux/delay.h>
  70 #include <linux/ioctl.h>
  71 #include <linux/termios.h>
  72 #include <linux/bitops.h>
  73 #include <linux/workqueue.h>
  74 #include <linux/hdlc.h>
  75 #include <linux/synclink.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/io.h>
  79 #include <asm/irq.h>
  80 #include <asm/dma.h>
  81 #include <asm/types.h>
  82 #include <asm/uaccess.h>
  83
  84 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  85 #define SYNCLINK_GENERIC_HDLC 1
  86 #else
  87 #define SYNCLINK_GENERIC_HDLC 0
  88 #endif
  89
  90 /*
  91  * module identification
  92  */
  93 static char *driver_name     = "SyncLink GT";
  94 static char *driver_version  = "$Revision: 4.50 $";
  95 static char *tty_driver_name = "synclink_gt";
  96 static char *tty_dev_prefix  = "ttySLG";
  97 MODULE_LICENSE("GPL");
  98 #define MGSL_MAGIC 0x5401
  99 #define MAX_DEVICES 32
 100
 101 static struct pci_device_id pci_table[] = {
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {0,}, /* terminate list */
 107 };
 108 MODULE_DEVICE_TABLE(pci, pci_table);
 109
 110 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 111 static void remove_one(struct pci_dev *dev);
 112 static struct pci_driver pci_driver = {
 113         .name           = "synclink_gt",
 114         .id_table       = pci_table,
 115         .probe          = init_one,
 116         .remove         = __devexit_p(remove_one),
 117 };
 118
 119 static bool pci_registered;
 120
 121 /*
 122  * module configuration and status
 123  */
 124 static struct slgt_info *slgt_device_list;
 125 static int slgt_device_count;
 126
 127 static int ttymajor;
 128 static int debug_level;
 129 static int maxframe[MAX_DEVICES];
 130
 131 module_param(ttymajor, int, 0);
 132 module_param(debug_level, int, 0);
 133 module_param_array(maxframe, int, NULL, 0);
 134
 135 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 136 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 137 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 138
 139 /*
 140  * tty support and callbacks
 141  */
 142 static struct tty_driver *serial_driver;
 143
 144 static int  open(struct tty_struct *tty, struct file * filp);
 145 static void close(struct tty_struct *tty, struct file * filp);
 146 static void hangup(struct tty_struct *tty);
 147 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 148
 149 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 150 static int put_char(struct tty_struct *tty, unsigned char ch);
 151 static void send_xchar(struct tty_struct *tty, char ch);
 152 static void wait_until_sent(struct tty_struct *tty, int timeout);
 153 static int  write_room(struct tty_struct *tty);
 154 static void flush_chars(struct tty_struct *tty);
 155 static void flush_buffer(struct tty_struct *tty);
 156 static void tx_hold(struct tty_struct *tty);
 157 static void tx_release(struct tty_struct *tty);
 158
 159 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 160 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 161 static int  chars_in_buffer(struct tty_struct *tty);
 162 static void throttle(struct tty_struct * tty);
 163 static void unthrottle(struct tty_struct * tty);
 164 static int set_break(struct tty_struct *tty, int break_state);
 165
 166 /*
 167  * generic HDLC support and callbacks
 168  */
 169 #if SYNCLINK_GENERIC_HDLC
 170 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 171 static void hdlcdev_tx_done(struct slgt_info *info);
 172 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 173 static int  hdlcdev_init(struct slgt_info *info);
 174 static void hdlcdev_exit(struct slgt_info *info);
 175 #endif
 176
 177
 178 /*
 179  * device specific structures, macros and functions
 180  */
 181
 182 #define SLGT_MAX_PORTS 4
 183 #define SLGT_REG_SIZE  256
 184
 185 /*
 186  * conditional wait facility
 187  */
 188 struct cond_wait {
 189         struct cond_wait *next;
 190         wait_queue_head_t q;
 191         wait_queue_t wait;
 192         unsigned int data;
 193 };
 194 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 195 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 196 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 197 static void flush_cond_wait(struct cond_wait **head);
 198
 199 /*
 200  * DMA buffer descriptor and access macros
 201  */
 202 struct slgt_desc
 203 {
 204         __le16 count;
 205         __le16 status;
 206         __le32 pbuf;  /* physical address of data buffer */
 207         __le32 next;  /* physical address of next descriptor */
 208
 209         /* driver book keeping */
 210         char *buf;          /* virtual  address of data buffer */
 211         unsigned int pdesc; /* physical address of this descriptor */
 212         dma_addr_t buf_dma_addr;
 213         unsigned short buf_count;
 214 };
 215
 216 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 217 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 218 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 219 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 220 #define desc_count(a)      (le16_to_cpu((a).count))
 221 #define desc_status(a)     (le16_to_cpu((a).status))
 222 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 223 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 224 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 225 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 226 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 227
 228 struct _input_signal_events {
 229         int ri_up;
 230         int ri_down;
 231         int dsr_up;
 232         int dsr_down;
 233         int dcd_up;
 234         int dcd_down;
 235         int cts_up;
 236         int cts_down;
 237 };
 238
 239 /*
 240  * device instance data structure
 241  */
 242 struct slgt_info {
 243         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 244         struct tty_port port;
 245
 246         struct slgt_info *next_device;  /* device list link */
 247
 248         int magic;
 249
 250         char device_name[25];
 251         struct pci_dev *pdev;
 252
 253         int port_count;  /* count of ports on adapter */
 254         int adapter_num; /* adapter instance number */
 255         int port_num;    /* port instance number */
 256
 257         /* array of pointers to port contexts on this adapter */
 258         struct slgt_info *port_array[SLGT_MAX_PORTS];
 259
 260         int                     line;           /* tty line instance number */
 261
 262         struct mgsl_icount      icount;
 263
 264         int                     timeout;
 265         int                     x_char;         /* xon/xoff character */
 266         unsigned int            read_status_mask;
 267         unsigned int            ignore_status_mask;
 268
 269         wait_queue_head_t       status_event_wait_q;
 270         wait_queue_head_t       event_wait_q;
 271         struct timer_list       tx_timer;
 272         struct timer_list       rx_timer;
 273
 274         unsigned int            gpio_present;
 275         struct cond_wait        *gpio_wait_q;
 276
 277         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 278
 279         struct work_struct task;
 280         u32 pending_bh;
 281         bool bh_requested;
 282         bool bh_running;
 283
 284         int isr_overflow;
 285         bool irq_requested;     /* true if IRQ requested */
 286         bool irq_occurred;      /* for diagnostics use */
 287
 288         /* device configuration */
 289
 290         unsigned int bus_type;
 291         unsigned int irq_level;
 292         unsigned long irq_flags;
 293
 294         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 295         u32 phys_reg_addr;
 296         bool reg_addr_requested;
 297
 298         MGSL_PARAMS params;       /* communications parameters */
 299         u32 idle_mode;
 300         u32 max_frame_size;       /* as set by device config */
 301
 302         unsigned int rbuf_fill_level;
 303         unsigned int if_mode;
 304
 305         /* device status */
 306
 307         bool rx_enabled;
 308         bool rx_restart;
 309
 310         bool tx_enabled;
 311         bool tx_active;
 312
 313         unsigned char signals;    /* serial signal states */
 314         int init_error;  /* initialization error */
 315
 316         unsigned char *tx_buf;
 317         int tx_count;
 318
 319         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 320         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 321         bool drop_rts_on_tx_done;
 322         struct  _input_signal_events    input_signal_events;
 323
 324         int dcd_chkcount;       /* check counts to prevent */
 325         int cts_chkcount;       /* too many IRQs if a signal */
 326         int dsr_chkcount;       /* is floating */
 327         int ri_chkcount;
 328
 329         char *bufs;             /* virtual address of DMA buffer lists */
 330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332         unsigned int rbuf_count;
 333         struct slgt_desc *rbufs;
 334         unsigned int rbuf_current;
 335         unsigned int rbuf_index;
 336
 337         unsigned int tbuf_count;
 338         struct slgt_desc *tbufs;
 339         unsigned int tbuf_current;
 340         unsigned int tbuf_start;
 341
 342         unsigned char *tmp_rbuf;
 343         unsigned int tmp_rbuf_count;
 344
 345         /* SPPP/Cisco HDLC device parts */
 346
 347         int netcount;
 348         spinlock_t netlock;
 349 #if SYNCLINK_GENERIC_HDLC
 350         struct net_device *netdev;
 351 #endif
 352
 353 };
 354
 355 static MGSL_PARAMS default_params = {
 356         .mode            = MGSL_MODE_HDLC,
 357         .loopback        = 0,
 358         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 359         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 360         .clock_speed     = 0,
 361         .addr_filter     = 0xff,
 362         .crc_type        = HDLC_CRC_16_CCITT,
 363         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 364         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 365         .data_rate       = 9600,
 366         .data_bits       = 8,
 367         .stop_bits       = 1,
 368         .parity          = ASYNC_PARITY_NONE
 369 };
 370
 371
 372 #define BH_RECEIVE  1
 373 #define BH_TRANSMIT 2
 374 #define BH_STATUS   4
 375 #define IO_PIN_SHUTDOWN_LIMIT 100
 376
 377 #define DMABUFSIZE 256
 378 #define DESC_LIST_SIZE 4096
 379
 380 #define MASK_PARITY  BIT1
 381 #define MASK_FRAMING BIT0
 382 #define MASK_BREAK   BIT14
 383 #define MASK_OVERRUN BIT4
 384
 385 #define GSR   0x00 /* global status */
 386 #define JCR   0x04 /* JTAG control */
 387 #define IODR  0x08 /* GPIO direction */
 388 #define IOER  0x0c /* GPIO interrupt enable */
 389 #define IOVR  0x10 /* GPIO value */
 390 #define IOSR  0x14 /* GPIO interrupt status */
 391 #define TDR   0x80 /* tx data */
 392 #define RDR   0x80 /* rx data */
 393 #define TCR   0x82 /* tx control */
 394 #define TIR   0x84 /* tx idle */
 395 #define TPR   0x85 /* tx preamble */
 396 #define RCR   0x86 /* rx control */
 397 #define VCR   0x88 /* V.24 control */
 398 #define CCR   0x89 /* clock control */
 399 #define BDR   0x8a /* baud divisor */
 400 #define SCR   0x8c /* serial control */
 401 #define SSR   0x8e /* serial status */
 402 #define RDCSR 0x90 /* rx DMA control/status */
 403 #define TDCSR 0x94 /* tx DMA control/status */
 404 #define RDDAR 0x98 /* rx DMA descriptor address */
 405 #define TDDAR 0x9c /* tx DMA descriptor address */
 406
 407 #define RXIDLE      BIT14
 408 #define RXBREAK     BIT14
 409 #define IRQ_TXDATA  BIT13
 410 #define IRQ_TXIDLE  BIT12
 411 #define IRQ_TXUNDER BIT11 /* HDLC */
 412 #define IRQ_RXDATA  BIT10
 413 #define IRQ_RXIDLE  BIT9  /* HDLC */
 414 #define IRQ_RXBREAK BIT9  /* async */
 415 #define IRQ_RXOVER  BIT8
 416 #define IRQ_DSR     BIT7
 417 #define IRQ_CTS     BIT6
 418 #define IRQ_DCD     BIT5
 419 #define IRQ_RI      BIT4
 420 #define IRQ_ALL     0x3ff0
 421 #define IRQ_MASTER  BIT0
 422
 423 #define slgt_irq_on(info, mask) \
 424         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 425 #define slgt_irq_off(info, mask) \
 426         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 427
 428 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 429 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 430 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 431 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 432 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 434
 435 static void  msc_set_vcr(struct slgt_info *info);
 436
 437 static int  startup(struct slgt_info *info);
 438 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 439 static void shutdown(struct slgt_info *info);
 440 static void program_hw(struct slgt_info *info);
 441 static void change_params(struct slgt_info *info);
 442
 443 static int  register_test(struct slgt_info *info);
 444 static int  irq_test(struct slgt_info *info);
 445 static int  loopback_test(struct slgt_info *info);
 446 static int  adapter_test(struct slgt_info *info);
 447
 448 static void reset_adapter(struct slgt_info *info);
 449 static void reset_port(struct slgt_info *info);
 450 static void async_mode(struct slgt_info *info);
 451 static void sync_mode(struct slgt_info *info);
 452
 453 static void rx_stop(struct slgt_info *info);
 454 static void rx_start(struct slgt_info *info);
 455 static void reset_rbufs(struct slgt_info *info);
 456 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 457 static void rdma_reset(struct slgt_info *info);
 458 static bool rx_get_frame(struct slgt_info *info);
 459 static bool rx_get_buf(struct slgt_info *info);
 460
 461 static void tx_start(struct slgt_info *info);
 462 static void tx_stop(struct slgt_info *info);
 463 static void tx_set_idle(struct slgt_info *info);
 464 static unsigned int free_tbuf_count(struct slgt_info *info);
 465 static unsigned int tbuf_bytes(struct slgt_info *info);
 466 static void reset_tbufs(struct slgt_info *info);
 467 static void tdma_reset(struct slgt_info *info);
 468 static void tdma_start(struct slgt_info *info);
 469 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 470
 471 static void get_signals(struct slgt_info *info);
 472 static void set_signals(struct slgt_info *info);
 473 static void enable_loopback(struct slgt_info *info);
 474 static void set_rate(struct slgt_info *info, u32 data_rate);
 475
 476 static int  bh_action(struct slgt_info *info);
 477 static void bh_handler(struct work_struct *work);
 478 static void bh_transmit(struct slgt_info *info);
 479 static void isr_serial(struct slgt_info *info);
 480 static void isr_rdma(struct slgt_info *info);
 481 static void isr_txeom(struct slgt_info *info, unsigned short status);
 482 static void isr_tdma(struct slgt_info *info);
 483
 484 static int  alloc_dma_bufs(struct slgt_info *info);
 485 static void free_dma_bufs(struct slgt_info *info);
 486 static int  alloc_desc(struct slgt_info *info);
 487 static void free_desc(struct slgt_info *info);
 488 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 489 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 490
 491 static int  alloc_tmp_rbuf(struct slgt_info *info);
 492 static void free_tmp_rbuf(struct slgt_info *info);
 493
 494 static void tx_timeout(unsigned long context);
 495 static void rx_timeout(unsigned long context);
 496
 497 /*
 498  * ioctl handlers
 499  */
 500 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 501 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 502 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 503 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 504 static int  set_txidle(struct slgt_info *info, int idle_mode);
 505 static int  tx_enable(struct slgt_info *info, int enable);
 506 static int  tx_abort(struct slgt_info *info);
 507 static int  rx_enable(struct slgt_info *info, int enable);
 508 static int  modem_input_wait(struct slgt_info *info,int arg);
 509 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 510 static int  tiocmget(struct tty_struct *tty, struct file *file);
 511 static int  tiocmset(struct tty_struct *tty, struct file *file,
 512                      unsigned int set, unsigned int clear);
 513 static int set_break(struct tty_struct *tty, int break_state);
 514 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 515 static int  set_interface(struct slgt_info *info, int if_mode);
 516 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 517 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 518 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 519
 520 /*
 521  * driver functions
 522  */
 523 static void add_device(struct slgt_info *info);
 524 static void device_init(int adapter_num, struct pci_dev *pdev);
 525 static int  claim_resources(struct slgt_info *info);
 526 static void release_resources(struct slgt_info *info);
 527
 528 /*
 529  * DEBUG OUTPUT CODE
 530  */
 531 #ifndef DBGINFO
 532 #define DBGINFO(fmt)
 533 #endif
 534 #ifndef DBGERR
 535 #define DBGERR(fmt)
 536 #endif
 537 #ifndef DBGBH
 538 #define DBGBH(fmt)
 539 #endif
 540 #ifndef DBGISR
 541 #define DBGISR(fmt)
 542 #endif
 543
 544 #ifdef DBGDATA
 545 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 546 {
 547         int i;
 548         int linecount;
 549         printk("%s %s data:\n",info->device_name, label);
 550         while(count) {
 551                 linecount = (count > 16) ? 16 : count;
 552                 for(i=0; i < linecount; i++)
 553                         printk("%02X ",(unsigned char)data[i]);
 554                 for(;i<17;i++)
 555                         printk("   ");
 556                 for(i=0;i<linecount;i++) {
 557                         if (data[i]>=040 && data[i]<=0176)
 558                                 printk("%c",data[i]);
 559                         else
 560                                 printk(".");
 561                 }
 562                 printk("\n");
 563                 data  += linecount;
 564                 count -= linecount;
 565         }
 566 }
 567 #else
 568 #define DBGDATA(info, buf, size, label)
 569 #endif
 570
 571 #ifdef DBGTBUF
 572 static void dump_tbufs(struct slgt_info *info)
 573 {
 574         int i;
 575         printk("tbuf_current=%d\n", info->tbuf_current);
 576         for (i=0 ; i < info->tbuf_count ; i++) {
 577                 printk("%d: count=%04X status=%04X\n",
 578                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 579         }
 580 }
 581 #else
 582 #define DBGTBUF(info)
 583 #endif
 584
 585 #ifdef DBGRBUF
 586 static void dump_rbufs(struct slgt_info *info)
 587 {
 588         int i;
 589         printk("rbuf_current=%d\n", info->rbuf_current);
 590         for (i=0 ; i < info->rbuf_count ; i++) {
 591                 printk("%d: count=%04X status=%04X\n",
 592                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 593         }
 594 }
 595 #else
 596 #define DBGRBUF(info)
 597 #endif
 598
 599 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 600 {
 601 #ifdef SANITY_CHECK
 602         if (!info) {
 603                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 604                 return 1;
 605         }
 606         if (info->magic != MGSL_MAGIC) {
 607                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 608                 return 1;
 609         }
 610 #else
 611         if (!info)
 612                 return 1;
 613 #endif
 614         return 0;
 615 }
 616
 617 /**
 618  * line discipline callback wrappers
 619  *
 620  * The wrappers maintain line discipline references
 621  * while calling into the line discipline.
 622  *
 623  * ldisc_receive_buf  - pass receive data to line discipline
 624  */
 625 static void ldisc_receive_buf(struct tty_struct *tty,
 626                               const __u8 *data, char *flags, int count)
 627 {
 628         struct tty_ldisc *ld;
 629         if (!tty)
 630                 return;
 631         ld = tty_ldisc_ref(tty);
 632         if (ld) {
 633                 if (ld->ops->receive_buf)
 634                         ld->ops->receive_buf(tty, data, flags, count);
 635                 tty_ldisc_deref(ld);
 636         }
 637 }
 638
 639 /* tty callbacks */
 640
 641 static int open(struct tty_struct *tty, struct file *filp)
 642 {
 643         struct slgt_info *info;
 644         int retval, line;
 645         unsigned long flags;
 646
 647         line = tty->index;
 648         if ((line < 0) || (line >= slgt_device_count)) {
 649                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 650                 return -ENODEV;
 651         }
 652
 653         info = slgt_device_list;
 654         while(info && info->line != line)
 655                 info = info->next_device;
 656         if (sanity_check(info, tty->name, "open"))
 657                 return -ENODEV;
 658         if (info->init_error) {
 659                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 660                 return -ENODEV;
 661         }
 662
 663         tty->driver_data = info;
 664         info->port.tty = tty;
 665
 666         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 667
 668         /* If port is closing, signal caller to try again */
 669         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 670                 if (info->port.flags & ASYNC_CLOSING)
 671                         interruptible_sleep_on(&info->port.close_wait);
 672                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 673                         -EAGAIN : -ERESTARTSYS);
 674                 goto cleanup;
 675         }
 676
 677         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 678
 679         spin_lock_irqsave(&info->netlock, flags);
 680         if (info->netcount) {
 681                 retval = -EBUSY;
 682                 spin_unlock_irqrestore(&info->netlock, flags);
 683                 goto cleanup;
 684         }
 685         info->port.count++;
 686         spin_unlock_irqrestore(&info->netlock, flags);
 687
 688         if (info->port.count == 1) {
 689                 /* 1st open on this device, init hardware */
 690                 retval = startup(info);
 691                 if (retval < 0)
 692                         goto cleanup;
 693         }
 694
 695         retval = block_til_ready(tty, filp, info);
 696         if (retval) {
 697                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 698                 goto cleanup;
 699         }
 700
 701         retval = 0;
 702
 703 cleanup:
 704         if (retval) {
 705                 if (tty->count == 1)
 706                         info->port.tty = NULL; /* tty layer will release tty struct */
 707                 if(info->port.count)
 708                         info->port.count--;
 709         }
 710
 711         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 712         return retval;
 713 }
 714
 715 static void close(struct tty_struct *tty, struct file *filp)
 716 {
 717         struct slgt_info *info = tty->driver_data;
 718
 719         if (sanity_check(info, tty->name, "close"))
 720                 return;
 721         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 722
 723         if (!info->port.count)
 724                 return;
 725
 726         if (tty_hung_up_p(filp))
 727                 goto cleanup;
 728
 729         if ((tty->count == 1) && (info->port.count != 1)) {
 730                 /*
 731                  * tty->count is 1 and the tty structure will be freed.
 732                  * info->port.count should be one in this case.
 733                  * if it's not, correct it so that the port is shutdown.
 734                  */
 735                 DBGERR(("%s close: bad refcount; tty->count=1, "
 736                        "info->port.count=%d\n", info->device_name, info->port.count));
 737                 info->port.count = 1;
 738         }
 739
 740         info->port.count--;
 741
 742         /* if at least one open remaining, leave hardware active */
 743         if (info->port.count)
 744                 goto cleanup;
 745
 746         info->port.flags |= ASYNC_CLOSING;
 747
 748         /* set tty->closing to notify line discipline to
 749          * only process XON/XOFF characters. Only the N_TTY
 750          * discipline appears to use this (ppp does not).
 751          */
 752         tty->closing = 1;
 753
 754         /* wait for transmit data to clear all layers */
 755
 756         if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 757                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 758                 tty_wait_until_sent(tty, info->port.closing_wait);
 759         }
 760
 761         if (info->port.flags & ASYNC_INITIALIZED)
 762                 wait_until_sent(tty, info->timeout);
 763         flush_buffer(tty);
 764         tty_ldisc_flush(tty);
 765
 766         shutdown(info);
 767
 768         tty->closing = 0;
 769         info->port.tty = NULL;
 770
 771         if (info->port.blocked_open) {
 772                 if (info->port.close_delay) {
 773                         msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
 774                 }
 775                 wake_up_interruptible(&info->port.open_wait);
 776         }
 777
 778         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 779
 780         wake_up_interruptible(&info->port.close_wait);
 781
 782 cleanup:
 783         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 784 }
 785
 786 static void hangup(struct tty_struct *tty)
 787 {
 788         struct slgt_info *info = tty->driver_data;
 789
 790         if (sanity_check(info, tty->name, "hangup"))
 791                 return;
 792         DBGINFO(("%s hangup\n", info->device_name));
 793
 794         flush_buffer(tty);
 795         shutdown(info);
 796
 797         info->port.count = 0;
 798         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 799         info->port.tty = NULL;
 800
 801         wake_up_interruptible(&info->port.open_wait);
 802 }
 803
 804 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 805 {
 806         struct slgt_info *info = tty->driver_data;
 807         unsigned long flags;
 808
 809         DBGINFO(("%s set_termios\n", tty->driver->name));
 810
 811         change_params(info);
 812
 813         /* Handle transition to B0 status */
 814         if (old_termios->c_cflag & CBAUD &&
 815             !(tty->termios->c_cflag & CBAUD)) {
 816                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 817                 spin_lock_irqsave(&info->lock,flags);
 818                 set_signals(info);
 819                 spin_unlock_irqrestore(&info->lock,flags);
 820         }
 821
 822         /* Handle transition away from B0 status */
 823         if (!(old_termios->c_cflag & CBAUD) &&
 824             tty->termios->c_cflag & CBAUD) {
 825                 info->signals |= SerialSignal_DTR;
 826                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 827                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 828                         info->signals |= SerialSignal_RTS;
 829                 }
 830                 spin_lock_irqsave(&info->lock,flags);
 831                 set_signals(info);
 832                 spin_unlock_irqrestore(&info->lock,flags);
 833         }
 834
 835         /* Handle turning off CRTSCTS */
 836         if (old_termios->c_cflag & CRTSCTS &&
 837             !(tty->termios->c_cflag & CRTSCTS)) {
 838                 tty->hw_stopped = 0;
 839                 tx_release(tty);
 840         }
 841 }
 842
 843 static int write(struct tty_struct *tty,
 844                  const unsigned char *buf, int count)
 845 {
 846         int ret = 0;
 847         struct slgt_info *info = tty->driver_data;
 848         unsigned long flags;
 849         unsigned int bufs_needed;
 850
 851         if (sanity_check(info, tty->name, "write"))
 852                 goto cleanup;
 853         DBGINFO(("%s write count=%d\n", info->device_name, count));
 854
 855         if (!info->tx_buf)
 856                 goto cleanup;
 857
 858         if (count > info->max_frame_size) {
 859                 ret = -EIO;
 860                 goto cleanup;
 861         }
 862
 863         if (!count)
 864                 goto cleanup;
 865
 866         if (!info->tx_active && info->tx_count) {
 867                 /* send accumulated data from send_char() */
 868                 tx_load(info, info->tx_buf, info->tx_count);
 869                 goto start;
 870         }
 871         bufs_needed = (count/DMABUFSIZE);
 872         if (count % DMABUFSIZE)
 873                 ++bufs_needed;
 874         if (bufs_needed > free_tbuf_count(info))
 875                 goto cleanup;
 876
 877         ret = info->tx_count = count;
 878         tx_load(info, buf, count);
 879         goto start;
 880
 881 start:
 882         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 883                 spin_lock_irqsave(&info->lock,flags);
 884                 if (!info->tx_active)
 885                         tx_start(info);
 886                 else
 887                         tdma_start(info);
 888                 spin_unlock_irqrestore(&info->lock,flags);
 889         }
 890
 891 cleanup:
 892         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 893         return ret;
 894 }
 895
 896 static int put_char(struct tty_struct *tty, unsigned char ch)
 897 {
 898         struct slgt_info *info = tty->driver_data;
 899         unsigned long flags;
 900         int ret = 0;
 901
 902         if (sanity_check(info, tty->name, "put_char"))
 903                 return 0;
 904         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 905         if (!info->tx_buf)
 906                 return 0;
 907         spin_lock_irqsave(&info->lock,flags);
 908         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 909                 info->tx_buf[info->tx_count++] = ch;
 910                 ret = 1;
 911         }
 912         spin_unlock_irqrestore(&info->lock,flags);
 913         return ret;
 914 }
 915
 916 static void send_xchar(struct tty_struct *tty, char ch)
 917 {
 918         struct slgt_info *info = tty->driver_data;
 919         unsigned long flags;
 920
 921         if (sanity_check(info, tty->name, "send_xchar"))
 922                 return;
 923         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 924         info->x_char = ch;
 925         if (ch) {
 926                 spin_lock_irqsave(&info->lock,flags);
 927                 if (!info->tx_enabled)
 928                         tx_start(info);
 929                 spin_unlock_irqrestore(&info->lock,flags);
 930         }
 931 }
 932
 933 static void wait_until_sent(struct tty_struct *tty, int timeout)
 934 {
 935         struct slgt_info *info = tty->driver_data;
 936         unsigned long orig_jiffies, char_time;
 937
 938         if (!info )
 939                 return;
 940         if (sanity_check(info, tty->name, "wait_until_sent"))
 941                 return;
 942         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 943         if (!(info->port.flags & ASYNC_INITIALIZED))
 944                 goto exit;
 945
 946         orig_jiffies = jiffies;
 947
 948         /* Set check interval to 1/5 of estimated time to
 949          * send a character, and make it at least 1. The check
 950          * interval should also be less than the timeout.
 951          * Note: use tight timings here to satisfy the NIST-PCTS.
 952          */
 953
 954         lock_kernel();
 955
 956         if (info->params.data_rate) {
 957                 char_time = info->timeout/(32 * 5);
 958                 if (!char_time)
 959                         char_time++;
 960         } else
 961                 char_time = 1;
 962
 963         if (timeout)
 964                 char_time = min_t(unsigned long, char_time, timeout);
 965
 966         while (info->tx_active) {
 967                 msleep_interruptible(jiffies_to_msecs(char_time));
 968                 if (signal_pending(current))
 969                         break;
 970                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 971                         break;
 972         }
 973         unlock_kernel();
 974
 975 exit:
 976         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 977 }
 978
 979 static int write_room(struct tty_struct *tty)
 980 {
 981         struct slgt_info *info = tty->driver_data;
 982         int ret;
 983
 984         if (sanity_check(info, tty->name, "write_room"))
 985                 return 0;
 986         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 987         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 988         return ret;
 989 }
 990
 991 static void flush_chars(struct tty_struct *tty)
 992 {
 993         struct slgt_info *info = tty->driver_data;
 994         unsigned long flags;
 995
 996         if (sanity_check(info, tty->name, "flush_chars"))
 997                 return;
 998         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 999
1000         if (info->tx_count <= 0 || tty->stopped ||
1001             tty->hw_stopped || !info->tx_buf)
1002                 return;
1003
1004         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1005
1006         spin_lock_irqsave(&info->lock,flags);
1007         if (!info->tx_active && info->tx_count) {
1008                 tx_load(info, info->tx_buf,info->tx_count);
1009                 tx_start(info);
1010         }
1011         spin_unlock_irqrestore(&info->lock,flags);
1012 }
1013
1014 static void flush_buffer(struct tty_struct *tty)
1015 {
1016         struct slgt_info *info = tty->driver_data;
1017         unsigned long flags;
1018
1019         if (sanity_check(info, tty->name, "flush_buffer"))
1020                 return;
1021         DBGINFO(("%s flush_buffer\n", info->device_name));
1022
1023         spin_lock_irqsave(&info->lock,flags);
1024         if (!info->tx_active)
1025                 info->tx_count = 0;
1026         spin_unlock_irqrestore(&info->lock,flags);
1027
1028         tty_wakeup(tty);
1029 }
1030
1031 /*
1032  * throttle (stop) transmitter
1033  */
1034 static void tx_hold(struct tty_struct *tty)
1035 {
1036         struct slgt_info *info = tty->driver_data;
1037         unsigned long flags;
1038
1039         if (sanity_check(info, tty->name, "tx_hold"))
1040                 return;
1041         DBGINFO(("%s tx_hold\n", info->device_name));
1042         spin_lock_irqsave(&info->lock,flags);
1043         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1044                 tx_stop(info);
1045         spin_unlock_irqrestore(&info->lock,flags);
1046 }
1047
1048 /*
1049  * release (start) transmitter
1050  */
1051 static void tx_release(struct tty_struct *tty)
1052 {
1053         struct slgt_info *info = tty->driver_data;
1054         unsigned long flags;
1055
1056         if (sanity_check(info, tty->name, "tx_release"))
1057                 return;
1058         DBGINFO(("%s tx_release\n", info->device_name));
1059         spin_lock_irqsave(&info->lock,flags);
1060         if (!info->tx_active && info->tx_count) {
1061                 tx_load(info, info->tx_buf, info->tx_count);
1062                 tx_start(info);
1063         }
1064         spin_unlock_irqrestore(&info->lock,flags);
1065 }
1066
1067 /*
1068  * Service an IOCTL request
1069  *
1070  * Arguments
1071  *
1072  *      tty     pointer to tty instance data
1073  *      file    pointer to associated file object for device
1074  *      cmd     IOCTL command code
1075  *      arg     command argument/context
1076  *
1077  * Return 0 if success, otherwise error code
1078  */
1079 static int ioctl(struct tty_struct *tty, struct file *file,
1080                  unsigned int cmd, unsigned long arg)
1081 {
1082         struct slgt_info *info = tty->driver_data;
1083         struct mgsl_icount cnow;        /* kernel counter temps */
1084         struct serial_icounter_struct __user *p_cuser;  /* user space */
1085         unsigned long flags;
1086         void __user *argp = (void __user *)arg;
1087         int ret;
1088
1089         if (sanity_check(info, tty->name, "ioctl"))
1090                 return -ENODEV;
1091         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1092
1093         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1094             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1095                 if (tty->flags & (1 << TTY_IO_ERROR))
1096                     return -EIO;
1097         }
1098
1099         lock_kernel();
1100
1101         switch (cmd) {
1102         case MGSL_IOCGPARAMS:
1103                 ret = get_params(info, argp);
1104                 break;
1105         case MGSL_IOCSPARAMS:
1106                 ret = set_params(info, argp);
1107                 break;
1108         case MGSL_IOCGTXIDLE:
1109                 ret = get_txidle(info, argp);
1110                 break;
1111         case MGSL_IOCSTXIDLE:
1112                 ret = set_txidle(info, (int)arg);
1113                 break;
1114         case MGSL_IOCTXENABLE:
1115                 ret = tx_enable(info, (int)arg);
1116                 break;
1117         case MGSL_IOCRXENABLE:
1118                 ret = rx_enable(info, (int)arg);
1119                 break;
1120         case MGSL_IOCTXABORT:
1121                 ret = tx_abort(info);
1122                 break;
1123         case MGSL_IOCGSTATS:
1124                 ret = get_stats(info, argp);
1125                 break;
1126         case MGSL_IOCWAITEVENT:
1127                 ret = wait_mgsl_event(info, argp);
1128                 break;
1129         case TIOCMIWAIT:
1130                 ret = modem_input_wait(info,(int)arg);
1131                 break;
1132         case MGSL_IOCGIF:
1133                 ret = get_interface(info, argp);
1134                 break;
1135         case MGSL_IOCSIF:
1136                 ret = set_interface(info,(int)arg);
1137                 break;
1138         case MGSL_IOCSGPIO:
1139                 ret = set_gpio(info, argp);
1140                 break;
1141         case MGSL_IOCGGPIO:
1142                 ret = get_gpio(info, argp);
1143                 break;
1144         case MGSL_IOCWAITGPIO:
1145                 ret = wait_gpio(info, argp);
1146                 break;
1147         case TIOCGICOUNT:
1148                 spin_lock_irqsave(&info->lock,flags);
1149                 cnow = info->icount;
1150                 spin_unlock_irqrestore(&info->lock,flags);
1151                 p_cuser = argp;
1152                 if (put_user(cnow.cts, &p_cuser->cts) ||
1153                     put_user(cnow.dsr, &p_cuser->dsr) ||
1154                     put_user(cnow.rng, &p_cuser->rng) ||
1155                     put_user(cnow.dcd, &p_cuser->dcd) ||
1156                     put_user(cnow.rx, &p_cuser->rx) ||
1157                     put_user(cnow.tx, &p_cuser->tx) ||
1158                     put_user(cnow.frame, &p_cuser->frame) ||
1159                     put_user(cnow.overrun, &p_cuser->overrun) ||
1160                     put_user(cnow.parity, &p_cuser->parity) ||
1161                     put_user(cnow.brk, &p_cuser->brk) ||
1162                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1163                         ret = -EFAULT;
1164                 ret = 0;
1165                 break;
1166         default:
1167                 ret = -ENOIOCTLCMD;
1168         }
1169         unlock_kernel();
1170         return ret;
1171 }
1172
1173 /*
1174  * support for 32 bit ioctl calls on 64 bit systems
1175  */
1176 #ifdef CONFIG_COMPAT
1177 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1178 {
1179         struct MGSL_PARAMS32 tmp_params;
1180
1181         DBGINFO(("%s get_params32\n", info->device_name));
1182         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1183         tmp_params.loopback        = info->params.loopback;
1184         tmp_params.flags           = info->params.flags;
1185         tmp_params.encoding        = info->params.encoding;
1186         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1187         tmp_params.addr_filter     = info->params.addr_filter;
1188         tmp_params.crc_type        = info->params.crc_type;
1189         tmp_params.preamble_length = info->params.preamble_length;
1190         tmp_params.preamble        = info->params.preamble;
1191         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1192         tmp_params.data_bits       = info->params.data_bits;
1193         tmp_params.stop_bits       = info->params.stop_bits;
1194         tmp_params.parity          = info->params.parity;
1195         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1196                 return -EFAULT;
1197         return 0;
1198 }
1199
1200 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1201 {
1202         struct MGSL_PARAMS32 tmp_params;
1203
1204         DBGINFO(("%s set_params32\n", info->device_name));
1205         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1206                 return -EFAULT;
1207
1208         spin_lock(&info->lock);
1209         info->params.mode            = tmp_params.mode;
1210         info->params.loopback        = tmp_params.loopback;
1211         info->params.flags           = tmp_params.flags;
1212         info->params.encoding        = tmp_params.encoding;
1213         info->params.clock_speed     = tmp_params.clock_speed;
1214         info->params.addr_filter     = tmp_params.addr_filter;
1215         info->params.crc_type        = tmp_params.crc_type;
1216         info->params.preamble_length = tmp_params.preamble_length;
1217         info->params.preamble        = tmp_params.preamble;
1218         info->params.data_rate       = tmp_params.data_rate;
1219         info->params.data_bits       = tmp_params.data_bits;
1220         info->params.stop_bits       = tmp_params.stop_bits;
1221         info->params.parity          = tmp_params.parity;
1222         spin_unlock(&info->lock);
1223
1224         change_params(info);
1225
1226         return 0;
1227 }
1228
1229 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1230                          unsigned int cmd, unsigned long arg)
1231 {
1232         struct slgt_info *info = tty->driver_data;
1233         int rc = -ENOIOCTLCMD;
1234
1235         if (sanity_check(info, tty->name, "compat_ioctl"))
1236                 return -ENODEV;
1237         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1238
1239         switch (cmd) {
1240
1241         case MGSL_IOCSPARAMS32:
1242                 rc = set_params32(info, compat_ptr(arg));
1243                 break;
1244
1245         case MGSL_IOCGPARAMS32:
1246                 rc = get_params32(info, compat_ptr(arg));
1247                 break;
1248
1249         case MGSL_IOCGPARAMS:
1250         case MGSL_IOCSPARAMS:
1251         case MGSL_IOCGTXIDLE:
1252         case MGSL_IOCGSTATS:
1253         case MGSL_IOCWAITEVENT:
1254         case MGSL_IOCGIF:
1255         case MGSL_IOCSGPIO:
1256         case MGSL_IOCGGPIO:
1257         case MGSL_IOCWAITGPIO:
1258         case TIOCGICOUNT:
1259                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1260                 break;
1261
1262         case MGSL_IOCSTXIDLE:
1263         case MGSL_IOCTXENABLE:
1264         case MGSL_IOCRXENABLE:
1265         case MGSL_IOCTXABORT:
1266         case TIOCMIWAIT:
1267         case MGSL_IOCSIF:
1268                 rc = ioctl(tty, file, cmd, arg);
1269                 break;
1270         }
1271
1272         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1273         return rc;
1274 }
1275 #else
1276 #define slgt_compat_ioctl NULL
1277 #endif /* ifdef CONFIG_COMPAT */
1278
1279 /*
1280  * proc fs support
1281  */
1282 static inline int line_info(char *buf, struct slgt_info *info)
1283 {
1284         char stat_buf[30];
1285         int ret;
1286         unsigned long flags;
1287
1288         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1289                       info->device_name, info->phys_reg_addr,
1290                       info->irq_level, info->max_frame_size);
1291
1292         /* output current serial signal states */
1293         spin_lock_irqsave(&info->lock,flags);
1294         get_signals(info);
1295         spin_unlock_irqrestore(&info->lock,flags);
1296
1297         stat_buf[0] = 0;
1298         stat_buf[1] = 0;
1299         if (info->signals & SerialSignal_RTS)
1300                 strcat(stat_buf, "|RTS");
1301         if (info->signals & SerialSignal_CTS)
1302                 strcat(stat_buf, "|CTS");
1303         if (info->signals & SerialSignal_DTR)
1304                 strcat(stat_buf, "|DTR");
1305         if (info->signals & SerialSignal_DSR)
1306                 strcat(stat_buf, "|DSR");
1307         if (info->signals & SerialSignal_DCD)
1308                 strcat(stat_buf, "|CD");
1309         if (info->signals & SerialSignal_RI)
1310                 strcat(stat_buf, "|RI");
1311
1312         if (info->params.mode != MGSL_MODE_ASYNC) {
1313                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1314                                info->icount.txok, info->icount.rxok);
1315                 if (info->icount.txunder)
1316                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1317                 if (info->icount.txabort)
1318                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1319                 if (info->icount.rxshort)
1320                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1321                 if (info->icount.rxlong)
1322                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1323                 if (info->icount.rxover)
1324                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1325                 if (info->icount.rxcrc)
1326                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1327         } else {
1328                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1329                                info->icount.tx, info->icount.rx);
1330                 if (info->icount.frame)
1331                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1332                 if (info->icount.parity)
1333                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1334                 if (info->icount.brk)
1335                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1336                 if (info->icount.overrun)
1337                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1338         }
1339
1340         /* Append serial signal status to end */
1341         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1342
1343         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1344                        info->tx_active,info->bh_requested,info->bh_running,
1345                        info->pending_bh);
1346
1347         return ret;
1348 }
1349
1350 /* Called to print information about devices
1351  */
1352 static int read_proc(char *page, char **start, off_t off, int count,
1353                      int *eof, void *data)
1354 {
1355         int len = 0, l;
1356         off_t   begin = 0;
1357         struct slgt_info *info;
1358
1359         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1360
1361         info = slgt_device_list;
1362         while( info ) {
1363                 l = line_info(page + len, info);
1364                 len += l;
1365                 if (len+begin > off+count)
1366                         goto done;
1367                 if (len+begin < off) {
1368                         begin += len;
1369                         len = 0;
1370                 }
1371                 info = info->next_device;
1372         }
1373
1374         *eof = 1;
1375 done:
1376         if (off >= len+begin)
1377                 return 0;
1378         *start = page + (off-begin);
1379         return ((count < begin+len-off) ? count : begin+len-off);
1380 }
1381
1382 /*
1383  * return count of bytes in transmit buffer
1384  */
1385 static int chars_in_buffer(struct tty_struct *tty)
1386 {
1387         struct slgt_info *info = tty->driver_data;
1388         int count;
1389         if (sanity_check(info, tty->name, "chars_in_buffer"))
1390                 return 0;
1391         count = tbuf_bytes(info);
1392         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1393         return count;
1394 }
1395
1396 /*
1397  * signal remote device to throttle send data (our receive data)
1398  */
1399 static void throttle(struct tty_struct * tty)
1400 {
1401         struct slgt_info *info = tty->driver_data;
1402         unsigned long flags;
1403
1404         if (sanity_check(info, tty->name, "throttle"))
1405                 return;
1406         DBGINFO(("%s throttle\n", info->device_name));
1407         if (I_IXOFF(tty))
1408                 send_xchar(tty, STOP_CHAR(tty));
1409         if (tty->termios->c_cflag & CRTSCTS) {
1410                 spin_lock_irqsave(&info->lock,flags);
1411                 info->signals &= ~SerialSignal_RTS;
1412                 set_signals(info);
1413                 spin_unlock_irqrestore(&info->lock,flags);
1414         }
1415 }
1416
1417 /*
1418  * signal remote device to stop throttling send data (our receive data)
1419  */
1420 static void unthrottle(struct tty_struct * tty)
1421 {
1422         struct slgt_info *info = tty->driver_data;
1423         unsigned long flags;
1424
1425         if (sanity_check(info, tty->name, "unthrottle"))
1426                 return;
1427         DBGINFO(("%s unthrottle\n", info->device_name));
1428         if (I_IXOFF(tty)) {
1429                 if (info->x_char)
1430                         info->x_char = 0;
1431                 else
1432                         send_xchar(tty, START_CHAR(tty));
1433         }
1434         if (tty->termios->c_cflag & CRTSCTS) {
1435                 spin_lock_irqsave(&info->lock,flags);
1436                 info->signals |= SerialSignal_RTS;
1437                 set_signals(info);
1438                 spin_unlock_irqrestore(&info->lock,flags);
1439         }
1440 }
1441
1442 /*
1443  * set or clear transmit break condition
1444  * break_state  -1=set break condition, 0=clear
1445  */
1446 static int set_break(struct tty_struct *tty, int break_state)
1447 {
1448         struct slgt_info *info = tty->driver_data;
1449         unsigned short value;
1450         unsigned long flags;
1451
1452         if (sanity_check(info, tty->name, "set_break"))
1453                 return -EINVAL;
1454         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1455
1456         spin_lock_irqsave(&info->lock,flags);
1457         value = rd_reg16(info, TCR);
1458         if (break_state == -1)
1459                 value |= BIT6;
1460         else
1461                 value &= ~BIT6;
1462         wr_reg16(info, TCR, value);
1463         spin_unlock_irqrestore(&info->lock,flags);
1464         return 0;
1465 }
1466
1467 #if SYNCLINK_GENERIC_HDLC
1468
1469 /**
1470  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1471  * set encoding and frame check sequence (FCS) options
1472  *
1473  * dev       pointer to network device structure
1474  * encoding  serial encoding setting
1475  * parity    FCS setting
1476  *
1477  * returns 0 if success, otherwise error code
1478  */
1479 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1480                           unsigned short parity)
1481 {
1482         struct slgt_info *info = dev_to_port(dev);
1483         unsigned char  new_encoding;
1484         unsigned short new_crctype;
1485
1486         /* return error if TTY interface open */
1487         if (info->port.count)
1488                 return -EBUSY;
1489
1490         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1491
1492         switch (encoding)
1493         {
1494         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1495         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1496         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1497         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1498         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1499         default: return -EINVAL;
1500         }
1501
1502         switch (parity)
1503         {
1504         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1505         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1506         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1507         default: return -EINVAL;
1508         }
1509
1510         info->params.encoding = new_encoding;
1511         info->params.crc_type = new_crctype;
1512
1513         /* if network interface up, reprogram hardware */
1514         if (info->netcount)
1515                 program_hw(info);
1516
1517         return 0;
1518 }
1519
1520 /**
1521  * called by generic HDLC layer to send frame
1522  *
1523  * skb  socket buffer containing HDLC frame
1524  * dev  pointer to network device structure
1525  *
1526  * returns 0 if success, otherwise error code
1527  */
1528 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1529 {
1530         struct slgt_info *info = dev_to_port(dev);
1531         unsigned long flags;
1532
1533         DBGINFO(("%s hdlc_xmit\n", dev->name));
1534
1535         /* stop sending until this frame completes */
1536         netif_stop_queue(dev);
1537
1538         /* copy data to device buffers */
1539         info->tx_count = skb->len;
1540         tx_load(info, skb->data, skb->len);
1541
1542         /* update network statistics */
1543         dev->stats.tx_packets++;
1544         dev->stats.tx_bytes += skb->len;
1545
1546         /* done with socket buffer, so free it */
1547         dev_kfree_skb(skb);
1548
1549         /* save start time for transmit timeout detection */
1550         dev->trans_start = jiffies;
1551
1552         /* start hardware transmitter if necessary */
1553         spin_lock_irqsave(&info->lock,flags);
1554         if (!info->tx_active)
1555                 tx_start(info);
1556         spin_unlock_irqrestore(&info->lock,flags);
1557
1558         return 0;
1559 }
1560
1561 /**
1562  * called by network layer when interface enabled
1563  * claim resources and initialize hardware
1564  *
1565  * dev  pointer to network device structure
1566  *
1567  * returns 0 if success, otherwise error code
1568  */
1569 static int hdlcdev_open(struct net_device *dev)
1570 {
1571         struct slgt_info *info = dev_to_port(dev);
1572         int rc;
1573         unsigned long flags;
1574
1575         if (!try_module_get(THIS_MODULE))
1576                 return -EBUSY;
1577
1578         DBGINFO(("%s hdlcdev_open\n", dev->name));
1579
1580         /* generic HDLC layer open processing */
1581         if ((rc = hdlc_open(dev)))
1582                 return rc;
1583
1584         /* arbitrate between network and tty opens */
1585         spin_lock_irqsave(&info->netlock, flags);
1586         if (info->port.count != 0 || info->netcount != 0) {
1587                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1588                 spin_unlock_irqrestore(&info->netlock, flags);
1589                 return -EBUSY;
1590         }
1591         info->netcount=1;
1592         spin_unlock_irqrestore(&info->netlock, flags);
1593
1594         /* claim resources and init adapter */
1595         if ((rc = startup(info)) != 0) {
1596                 spin_lock_irqsave(&info->netlock, flags);
1597                 info->netcount=0;
1598                 spin_unlock_irqrestore(&info->netlock, flags);
1599                 return rc;
1600         }
1601
1602         /* assert DTR and RTS, apply hardware settings */
1603         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1604         program_hw(info);
1605
1606         /* enable network layer transmit */
1607         dev->trans_start = jiffies;
1608         netif_start_queue(dev);
1609
1610         /* inform generic HDLC layer of current DCD status */
1611         spin_lock_irqsave(&info->lock, flags);
1612         get_signals(info);
1613         spin_unlock_irqrestore(&info->lock, flags);
1614         if (info->signals & SerialSignal_DCD)
1615                 netif_carrier_on(dev);
1616         else
1617                 netif_carrier_off(dev);
1618         return 0;
1619 }
1620
1621 /**
1622  * called by network layer when interface is disabled
1623  * shutdown hardware and release resources
1624  *
1625  * dev  pointer to network device structure
1626  *
1627  * returns 0 if success, otherwise error code
1628  */
1629 static int hdlcdev_close(struct net_device *dev)
1630 {
1631         struct slgt_info *info = dev_to_port(dev);
1632         unsigned long flags;
1633
1634         DBGINFO(("%s hdlcdev_close\n", dev->name));
1635
1636         netif_stop_queue(dev);
1637
1638         /* shutdown adapter and release resources */
1639         shutdown(info);
1640
1641         hdlc_close(dev);
1642
1643         spin_lock_irqsave(&info->netlock, flags);
1644         info->netcount=0;
1645         spin_unlock_irqrestore(&info->netlock, flags);
1646
1647         module_put(THIS_MODULE);
1648         return 0;
1649 }
1650
1651 /**
1652  * called by network layer to process IOCTL call to network device
1653  *
1654  * dev  pointer to network device structure
1655  * ifr  pointer to network interface request structure
1656  * cmd  IOCTL command code
1657  *
1658  * returns 0 if success, otherwise error code
1659  */
1660 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1661 {
1662         const size_t size = sizeof(sync_serial_settings);
1663         sync_serial_settings new_line;
1664         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1665         struct slgt_info *info = dev_to_port(dev);
1666         unsigned int flags;
1667
1668         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1669
1670         /* return error if TTY interface open */
1671         if (info->port.count)
1672                 return -EBUSY;
1673
1674         if (cmd != SIOCWANDEV)
1675                 return hdlc_ioctl(dev, ifr, cmd);
1676
1677         switch(ifr->ifr_settings.type) {
1678         case IF_GET_IFACE: /* return current sync_serial_settings */
1679
1680                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1681                 if (ifr->ifr_settings.size < size) {
1682                         ifr->ifr_settings.size = size; /* data size wanted */
1683                         return -ENOBUFS;
1684                 }
1685
1686                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1687                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1688                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1689                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1690
1691                 switch (flags){
1692                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1693                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1694                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1695                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1696                 default: new_line.clock_type = CLOCK_DEFAULT;
1697                 }
1698
1699                 new_line.clock_rate = info->params.clock_speed;
1700                 new_line.loopback   = info->params.loopback ? 1:0;
1701
1702                 if (copy_to_user(line, &new_line, size))
1703                         return -EFAULT;
1704                 return 0;
1705
1706         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1707
1708                 if(!capable(CAP_NET_ADMIN))
1709                         return -EPERM;
1710                 if (copy_from_user(&new_line, line, size))
1711                         return -EFAULT;
1712
1713                 switch (new_line.clock_type)
1714                 {
1715                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1716                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1717                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1718                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1719                 case CLOCK_DEFAULT:  flags = info->params.flags &
1720                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1721                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1722                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1723                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1724                 default: return -EINVAL;
1725                 }
1726
1727                 if (new_line.loopback != 0 && new_line.loopback != 1)
1728                         return -EINVAL;
1729
1730                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1731                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1732                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1733                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1734                 info->params.flags |= flags;
1735
1736                 info->params.loopback = new_line.loopback;
1737
1738                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1739                         info->params.clock_speed = new_line.clock_rate;
1740                 else
1741                         info->params.clock_speed = 0;
1742
1743                 /* if network interface up, reprogram hardware */
1744                 if (info->netcount)
1745                         program_hw(info);
1746                 return 0;
1747
1748         default:
1749                 return hdlc_ioctl(dev, ifr, cmd);
1750         }
1751 }
1752
1753 /**
1754  * called by network layer when transmit timeout is detected
1755  *
1756  * dev  pointer to network device structure
1757  */
1758 static void hdlcdev_tx_timeout(struct net_device *dev)
1759 {
1760         struct slgt_info *info = dev_to_port(dev);
1761         unsigned long flags;
1762
1763         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1764
1765         dev->stats.tx_errors++;
1766         dev->stats.tx_aborted_errors++;
1767
1768         spin_lock_irqsave(&info->lock,flags);
1769         tx_stop(info);
1770         spin_unlock_irqrestore(&info->lock,flags);
1771
1772         netif_wake_queue(dev);
1773 }
1774
1775 /**
1776  * called by device driver when transmit completes
1777  * reenable network layer transmit if stopped
1778  *
1779  * info  pointer to device instance information
1780  */
1781 static void hdlcdev_tx_done(struct slgt_info *info)
1782 {
1783         if (netif_queue_stopped(info->netdev))
1784                 netif_wake_queue(info->netdev);
1785 }
1786
1787 /**
1788  * called by device driver when frame received
1789  * pass frame to network layer
1790  *
1791  * info  pointer to device instance information
1792  * buf   pointer to buffer contianing frame data
1793  * size  count of data bytes in buf
1794  */
1795 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1796 {
1797         struct sk_buff *skb = dev_alloc_skb(size);
1798         struct net_device *dev = info->netdev;
1799
1800         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1801
1802         if (skb == NULL) {
1803                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1804                 dev->stats.rx_dropped++;
1805                 return;
1806         }
1807
1808         memcpy(skb_put(skb, size), buf, size);
1809
1810         skb->protocol = hdlc_type_trans(skb, dev);
1811
1812         dev->stats.rx_packets++;
1813         dev->stats.rx_bytes += size;
1814
1815         netif_rx(skb);
1816
1817         dev->last_rx = jiffies;
1818 }
1819
1820 /**
1821  * called by device driver when adding device instance
1822  * do generic HDLC initialization
1823  *
1824  * info  pointer to device instance information
1825  *
1826  * returns 0 if success, otherwise error code
1827  */
1828 static int hdlcdev_init(struct slgt_info *info)
1829 {
1830         int rc;
1831         struct net_device *dev;
1832         hdlc_device *hdlc;
1833
1834         /* allocate and initialize network and HDLC layer objects */
1835
1836         if (!(dev = alloc_hdlcdev(info))) {
1837                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1838                 return -ENOMEM;
1839         }
1840
1841         /* for network layer reporting purposes only */
1842         dev->mem_start = info->phys_reg_addr;
1843         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1844         dev->irq       = info->irq_level;
1845
1846         /* network layer callbacks and settings */
1847         dev->do_ioctl       = hdlcdev_ioctl;
1848         dev->open           = hdlcdev_open;
1849         dev->stop           = hdlcdev_close;
1850         dev->tx_timeout     = hdlcdev_tx_timeout;
1851         dev->watchdog_timeo = 10*HZ;
1852         dev->tx_queue_len   = 50;
1853
1854         /* generic HDLC layer callbacks and settings */
1855         hdlc         = dev_to_hdlc(dev);
1856         hdlc->attach = hdlcdev_attach;
1857         hdlc->xmit   = hdlcdev_xmit;
1858
1859         /* register objects with HDLC layer */
1860         if ((rc = register_hdlc_device(dev))) {
1861                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1862                 free_netdev(dev);
1863                 return rc;
1864         }
1865
1866         info->netdev = dev;
1867         return 0;
1868 }
1869
1870 /**
1871  * called by device driver when removing device instance
1872  * do generic HDLC cleanup
1873  *
1874  * info  pointer to device instance information
1875  */
1876 static void hdlcdev_exit(struct slgt_info *info)
1877 {
1878         unregister_hdlc_device(info->netdev);
1879         free_netdev(info->netdev);
1880         info->netdev = NULL;
1881 }
1882
1883 #endif /* ifdef CONFIG_HDLC */
1884
1885 /*
1886  * get async data from rx DMA buffers
1887  */
1888 static void rx_async(struct slgt_info *info)
1889 {
1890         struct tty_struct *tty = info->port.tty;
1891         struct mgsl_icount *icount = &info->icount;
1892         unsigned int start, end;
1893         unsigned char *p;
1894         unsigned char status;
1895         struct slgt_desc *bufs = info->rbufs;
1896         int i, count;
1897         int chars = 0;
1898         int stat;
1899         unsigned char ch;
1900
1901         start = end = info->rbuf_current;
1902
1903         while(desc_complete(bufs[end])) {
1904                 count = desc_count(bufs[end]) - info->rbuf_index;
1905                 p     = bufs[end].buf + info->rbuf_index;
1906
1907                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1908                 DBGDATA(info, p, count, "rx");
1909
1910                 for(i=0 ; i < count; i+=2, p+=2) {
1911                         ch = *p;
1912                         icount->rx++;
1913
1914                         stat = 0;
1915
1916                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1917                                 if (status & BIT1)
1918                                         icount->parity++;
1919                                 else if (status & BIT0)
1920                                         icount->frame++;
1921                                 /* discard char if tty control flags say so */
1922                                 if (status & info->ignore_status_mask)
1923                                         continue;
1924                                 if (status & BIT1)
1925                                         stat = TTY_PARITY;
1926                                 else if (status & BIT0)
1927                                         stat = TTY_FRAME;
1928                         }
1929                         if (tty) {
1930                                 tty_insert_flip_char(tty, ch, stat);
1931                                 chars++;
1932                         }
1933                 }
1934
1935                 if (i < count) {
1936                         /* receive buffer not completed */
1937                         info->rbuf_index += i;
1938                         mod_timer(&info->rx_timer, jiffies + 1);
1939                         break;
1940                 }
1941
1942                 info->rbuf_index = 0;
1943                 free_rbufs(info, end, end);
1944
1945                 if (++end == info->rbuf_count)
1946                         end = 0;
1947
1948                 /* if entire list searched then no frame available */
1949                 if (end == start)
1950                         break;
1951         }
1952
1953         if (tty && chars)
1954                 tty_flip_buffer_push(tty);
1955 }
1956
1957 /*
1958  * return next bottom half action to perform
1959  */
1960 static int bh_action(struct slgt_info *info)
1961 {
1962         unsigned long flags;
1963         int rc;
1964
1965         spin_lock_irqsave(&info->lock,flags);
1966
1967         if (info->pending_bh & BH_RECEIVE) {
1968                 info->pending_bh &= ~BH_RECEIVE;
1969                 rc = BH_RECEIVE;
1970         } else if (info->pending_bh & BH_TRANSMIT) {
1971                 info->pending_bh &= ~BH_TRANSMIT;
1972                 rc = BH_TRANSMIT;
1973         } else if (info->pending_bh & BH_STATUS) {
1974                 info->pending_bh &= ~BH_STATUS;
1975                 rc = BH_STATUS;
1976         } else {
1977                 /* Mark BH routine as complete */
1978                 info->bh_running = false;
1979                 info->bh_requested = false;
1980                 rc = 0;
1981         }
1982
1983         spin_unlock_irqrestore(&info->lock,flags);
1984
1985         return rc;
1986 }
1987
1988 /*
1989  * perform bottom half processing
1990  */
1991 static void bh_handler(struct work_struct *work)
1992 {
1993         struct slgt_info *info = container_of(work, struct slgt_info, task);
1994         int action;
1995
1996         if (!info)
1997                 return;
1998         info->bh_running = true;
1999
2000         while((action = bh_action(info))) {
2001                 switch (action) {
2002                 case BH_RECEIVE:
2003                         DBGBH(("%s bh receive\n", info->device_name));
2004                         switch(info->params.mode) {
2005                         case MGSL_MODE_ASYNC:
2006                                 rx_async(info);
2007                                 break;
2008                         case MGSL_MODE_HDLC:
2009                                 while(rx_get_frame(info));
2010                                 break;
2011                         case MGSL_MODE_RAW:
2012                         case MGSL_MODE_MONOSYNC:
2013                         case MGSL_MODE_BISYNC:
2014                                 while(rx_get_buf(info));
2015                                 break;
2016                         }
2017                         /* restart receiver if rx DMA buffers exhausted */
2018                         if (info->rx_restart)
2019                                 rx_start(info);
2020                         break;
2021                 case BH_TRANSMIT:
2022                         bh_transmit(info);
2023                         break;
2024                 case BH_STATUS:
2025                         DBGBH(("%s bh status\n", info->device_name));
2026                         info->ri_chkcount = 0;
2027                         info->dsr_chkcount = 0;
2028                         info->dcd_chkcount = 0;
2029                         info->cts_chkcount = 0;
2030                         break;
2031                 default:
2032                         DBGBH(("%s unknown action\n", info->device_name));
2033                         break;
2034                 }
2035         }
2036         DBGBH(("%s bh_handler exit\n", info->device_name));
2037 }
2038
2039 static void bh_transmit(struct slgt_info *info)
2040 {
2041         struct tty_struct *tty = info->port.tty;
2042
2043         DBGBH(("%s bh_transmit\n", info->device_name));
2044         if (tty)
2045                 tty_wakeup(tty);
2046 }
2047
2048 static void dsr_change(struct slgt_info *info, unsigned short status)
2049 {
2050         if (status & BIT3) {
2051                 info->signals |= SerialSignal_DSR;
2052                 info->input_signal_events.dsr_up++;
2053         } else {
2054                 info->signals &= ~SerialSignal_DSR;
2055                 info->input_signal_events.dsr_down++;
2056         }
2057         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2058         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2059                 slgt_irq_off(info, IRQ_DSR);
2060                 return;
2061         }
2062         info->icount.dsr++;
2063         wake_up_interruptible(&info->status_event_wait_q);
2064         wake_up_interruptible(&info->event_wait_q);
2065         info->pending_bh |= BH_STATUS;
2066 }
2067
2068 static void cts_change(struct slgt_info *info, unsigned short status)
2069 {
2070         if (status & BIT2) {
2071                 info->signals |= SerialSignal_CTS;
2072                 info->input_signal_events.cts_up++;
2073         } else {
2074                 info->signals &= ~SerialSignal_CTS;
2075                 info->input_signal_events.cts_down++;
2076         }
2077         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2078         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2079                 slgt_irq_off(info, IRQ_CTS);
2080                 return;
2081         }
2082         info->icount.cts++;
2083         wake_up_interruptible(&info->status_event_wait_q);
2084         wake_up_interruptible(&info->event_wait_q);
2085         info->pending_bh |= BH_STATUS;
2086
2087         if (info->port.flags & ASYNC_CTS_FLOW) {
2088                 if (info->port.tty) {
2089                         if (info->port.tty->hw_stopped) {
2090                                 if (info->signals & SerialSignal_CTS) {
2091                                         info->port.tty->hw_stopped = 0;
2092                                         info->pending_bh |= BH_TRANSMIT;
2093                                         return;
2094                                 }
2095                         } else {
2096                                 if (!(info->signals & SerialSignal_CTS))
2097                                         info->port.tty->hw_stopped = 1;
2098                         }
2099                 }
2100         }
2101 }
2102
2103 static void dcd_change(struct slgt_info *info, unsigned short status)
2104 {
2105         if (status & BIT1) {
2106                 info->signals |= SerialSignal_DCD;
2107                 info->input_signal_events.dcd_up++;
2108         } else {
2109                 info->signals &= ~SerialSignal_DCD;
2110                 info->input_signal_events.dcd_down++;
2111         }
2112         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2113         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2114                 slgt_irq_off(info, IRQ_DCD);
2115                 return;
2116         }
2117         info->icount.dcd++;
2118 #if SYNCLINK_GENERIC_HDLC
2119         if (info->netcount) {
2120                 if (info->signals & SerialSignal_DCD)
2121                         netif_carrier_on(info->netdev);
2122                 else
2123                         netif_carrier_off(info->netdev);
2124         }
2125 #endif
2126         wake_up_interruptible(&info->status_event_wait_q);
2127         wake_up_interruptible(&info->event_wait_q);
2128         info->pending_bh |= BH_STATUS;
2129
2130         if (info->port.flags & ASYNC_CHECK_CD) {
2131                 if (info->signals & SerialSignal_DCD)
2132                         wake_up_interruptible(&info->port.open_wait);
2133                 else {
2134                         if (info->port.tty)
2135                                 tty_hangup(info->port.tty);
2136                 }
2137         }
2138 }
2139
2140 static void ri_change(struct slgt_info *info, unsigned short status)
2141 {
2142         if (status & BIT0) {
2143                 info->signals |= SerialSignal_RI;
2144                 info->input_signal_events.ri_up++;
2145         } else {
2146                 info->signals &= ~SerialSignal_RI;
2147                 info->input_signal_events.ri_down++;
2148         }
2149         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2150         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2151                 slgt_irq_off(info, IRQ_RI);
2152                 return;
2153         }
2154         info->icount.rng++;
2155         wake_up_interruptible(&info->status_event_wait_q);
2156         wake_up_interruptible(&info->event_wait_q);
2157         info->pending_bh |= BH_STATUS;
2158 }
2159
2160 static void isr_serial(struct slgt_info *info)
2161 {
2162         unsigned short status = rd_reg16(info, SSR);
2163
2164         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2165
2166         wr_reg16(info, SSR, status); /* clear pending */
2167
2168         info->irq_occurred = true;
2169
2170         if (info->params.mode == MGSL_MODE_ASYNC) {
2171                 if (status & IRQ_TXIDLE) {
2172                         if (info->tx_count)
2173                                 isr_txeom(info, status);
2174                 }
2175                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2176                         info->icount.brk++;
2177                         /* process break detection if tty control allows */
2178                         if (info->port.tty) {
2179                                 if (!(status & info->ignore_status_mask)) {
2180                                         if (info->read_status_mask & MASK_BREAK) {
2181                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2182                                                 if (info->port.flags & ASYNC_SAK)
2183                                                         do_SAK(info->port.tty);
2184                                         }
2185                                 }
2186                         }
2187                 }
2188         } else {
2189                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2190                         isr_txeom(info, status);
2191
2192                 if (status & IRQ_RXIDLE) {
2193                         if (status & RXIDLE)
2194                                 info->icount.rxidle++;
2195                         else
2196                                 info->icount.exithunt++;
2197                         wake_up_interruptible(&info->event_wait_q);
2198                 }
2199
2200                 if (status & IRQ_RXOVER)
2201                         rx_start(info);
2202         }
2203
2204         if (status & IRQ_DSR)
2205                 dsr_change(info, status);
2206         if (status & IRQ_CTS)
2207                 cts_change(info, status);
2208         if (status & IRQ_DCD)
2209                 dcd_change(info, status);
2210         if (status & IRQ_RI)
2211                 ri_change(info, status);
2212 }
2213
2214 static void isr_rdma(struct slgt_info *info)
2215 {
2216         unsigned int status = rd_reg32(info, RDCSR);
2217
2218         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2219
2220         /* RDCSR (rx DMA control/status)
2221          *
2222          * 31..07  reserved
2223          * 06      save status byte to DMA buffer
2224          * 05      error
2225          * 04      eol (end of list)
2226          * 03      eob (end of buffer)
2227          * 02      IRQ enable
2228          * 01      reset
2229          * 00      enable
2230          */
2231         wr_reg32(info, RDCSR, status);  /* clear pending */
2232
2233         if (status & (BIT5 + BIT4)) {
2234                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2235                 info->rx_restart = true;
2236         }
2237         info->pending_bh |= BH_RECEIVE;
2238 }
2239
2240 static void isr_tdma(struct slgt_info *info)
2241 {
2242         unsigned int status = rd_reg32(info, TDCSR);
2243
2244         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2245
2246         /* TDCSR (tx DMA control/status)
2247          *
2248          * 31..06  reserved
2249          * 05      error
2250          * 04      eol (end of list)
2251          * 03      eob (end of buffer)
2252          * 02      IRQ enable
2253          * 01      reset
2254          * 00      enable
2255          */
2256         wr_reg32(info, TDCSR, status);  /* clear pending */
2257
2258         if (status & (BIT5 + BIT4 + BIT3)) {
2259                 // another transmit buffer has completed
2260                 // run bottom half to get more send data from user
2261                 info->pending_bh |= BH_TRANSMIT;
2262         }
2263 }
2264
2265 static void isr_txeom(struct slgt_info *info, unsigned short status)
2266 {
2267         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2268
2269         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2270         tdma_reset(info);
2271         reset_tbufs(info);
2272         if (status & IRQ_TXUNDER) {
2273                 unsigned short val = rd_reg16(info, TCR);
2274                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2275                 wr_reg16(info, TCR, val); /* clear reset bit */
2276         }
2277
2278         if (info->tx_active) {
2279                 if (info->params.mode != MGSL_MODE_ASYNC) {
2280                         if (status & IRQ_TXUNDER)
2281                                 info->icount.txunder++;
2282                         else if (status & IRQ_TXIDLE)
2283                                 info->icount.txok++;
2284                 }
2285
2286                 info->tx_active = false;
2287                 info->tx_count = 0;
2288
2289                 del_timer(&info->tx_timer);
2290
2291                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2292                         info->signals &= ~SerialSignal_RTS;
2293                         info->drop_rts_on_tx_done = false;
2294                         set_signals(info);
2295                 }
2296
2297 #if SYNCLINK_GENERIC_HDLC
2298                 if (info->netcount)
2299                         hdlcdev_tx_done(info);
2300                 else
2301 #endif
2302                 {
2303                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2304                                 tx_stop(info);
2305                                 return;
2306                         }
2307                         info->pending_bh |= BH_TRANSMIT;
2308                 }
2309         }
2310 }
2311
2312 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2313 {
2314         struct cond_wait *w, *prev;
2315
2316         /* wake processes waiting for specific transitions */
2317         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2318                 if (w->data & changed) {
2319                         w->data = state;
2320                         wake_up_interruptible(&w->q);
2321                         if (prev != NULL)
2322                                 prev->next = w->next;
2323                         else
2324                                 info->gpio_wait_q = w->next;
2325                 } else
2326                         prev = w;
2327         }
2328 }
2329
2330 /* interrupt service routine
2331  *
2332  *      irq     interrupt number
2333  *      dev_id  device ID supplied during interrupt registration
2334  */
2335 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2336 {
2337         struct slgt_info *info = dev_id;
2338         unsigned int gsr;
2339         unsigned int i;
2340
2341         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2342
2343         spin_lock(&info->lock);
2344
2345         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2346                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2347                 info->irq_occurred = true;
2348                 for(i=0; i < info->port_count ; i++) {
2349                         if (info->port_array[i] == NULL)
2350                                 continue;
2351                         if (gsr & (BIT8 << i))
2352                                 isr_serial(info->port_array[i]);
2353                         if (gsr & (BIT16 << (i*2)))
2354                                 isr_rdma(info->port_array[i]);
2355                         if (gsr & (BIT17 << (i*2)))
2356                                 isr_tdma(info->port_array[i]);
2357                 }
2358         }
2359
2360         if (info->gpio_present) {
2361                 unsigned int state;
2362                 unsigned int changed;
2363                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2364                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2365                         /* read latched state of GPIO signals */
2366                         state = rd_reg32(info, IOVR);
2367                         /* clear pending GPIO interrupt bits */
2368                         wr_reg32(info, IOSR, changed);
2369                         for (i=0 ; i < info->port_count ; i++) {
2370                                 if (info->port_array[i] != NULL)
2371                                         isr_gpio(info->port_array[i], changed, state);
2372                         }
2373                 }
2374         }
2375
2376         for(i=0; i < info->port_count ; i++) {
2377                 struct slgt_info *port = info->port_array[i];
2378
2379                 if (port && (port->port.count || port->netcount) &&
2380                     port->pending_bh && !port->bh_running &&
2381                     !port->bh_requested) {
2382                         DBGISR(("%s bh queued\n", port->device_name));
2383                         schedule_work(&port->task);
2384                         port->bh_requested = true;
2385                 }
2386         }
2387
2388         spin_unlock(&info->lock);
2389
2390         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2391         return IRQ_HANDLED;
2392 }
2393
2394 static int startup(struct slgt_info *info)
2395 {
2396         DBGINFO(("%s startup\n", info->device_name));
2397
2398         if (info->port.flags & ASYNC_INITIALIZED)
2399                 return 0;
2400
2401         if (!info->tx_buf) {
2402                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2403                 if (!info->tx_buf) {
2404                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2405                         return -ENOMEM;
2406                 }
2407         }
2408
2409         info->pending_bh = 0;
2410
2411         memset(&info->icount, 0, sizeof(info->icount));
2412
2413         /* program hardware for current parameters */
2414         change_params(info);
2415
2416         if (info->port.tty)
2417                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2418
2419         info->port.flags |= ASYNC_INITIALIZED;
2420
2421         return 0;
2422 }
2423
2424 /*
2425  *  called by close() and hangup() to shutdown hardware
2426  */
2427 static void shutdown(struct slgt_info *info)
2428 {
2429         unsigned long flags;
2430
2431         if (!(info->port.flags & ASYNC_INITIALIZED))
2432                 return;
2433
2434         DBGINFO(("%s shutdown\n", info->device_name));
2435
2436         /* clear status wait queue because status changes */
2437         /* can't happen after shutting down the hardware */
2438         wake_up_interruptible(&info->status_event_wait_q);
2439         wake_up_interruptible(&info->event_wait_q);
2440
2441         del_timer_sync(&info->tx_timer);
2442         del_timer_sync(&info->rx_timer);
2443
2444         kfree(info->tx_buf);
2445         info->tx_buf = NULL;
2446
2447         spin_lock_irqsave(&info->lock,flags);
2448
2449         tx_stop(info);
2450         rx_stop(info);
2451
2452         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2453
2454         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2455                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2456                 set_signals(info);
2457         }
2458
2459         flush_cond_wait(&info->gpio_wait_q);
2460
2461         spin_unlock_irqrestore(&info->lock,flags);
2462
2463         if (info->port.tty)
2464                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2465
2466         info->port.flags &= ~ASYNC_INITIALIZED;
2467 }
2468
2469 static void program_hw(struct slgt_info *info)
2470 {
2471         unsigned long flags;
2472
2473         spin_lock_irqsave(&info->lock,flags);
2474
2475         rx_stop(info);
2476         tx_stop(info);
2477
2478         if (info->params.mode != MGSL_MODE_ASYNC ||
2479             info->netcount)
2480                 sync_mode(info);
2481         else
2482                 async_mode(info);
2483
2484         set_signals(info);
2485
2486         info->dcd_chkcount = 0;
2487         info->cts_chkcount = 0;
2488         info->ri_chkcount = 0;
2489         info->dsr_chkcount = 0;
2490
2491         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2492         get_signals(info);
2493
2494         if (info->netcount ||
2495             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2496                 rx_start(info);
2497
2498         spin_unlock_irqrestore(&info->lock,flags);
2499 }
2500
2501 /*
2502  * reconfigure adapter based on new parameters
2503  */
2504 static void change_params(struct slgt_info *info)
2505 {
2506         unsigned cflag;
2507         int bits_per_char;
2508
2509         if (!info->port.tty || !info->port.tty->termios)
2510                 return;
2511         DBGINFO(("%s change_params\n", info->device_name));
2512
2513         cflag = info->port.tty->termios->c_cflag;
2514
2515         /* if B0 rate (hangup) specified then negate DTR and RTS */
2516         /* otherwise assert DTR and RTS */
2517         if (cflag & CBAUD)
2518                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2519         else
2520                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2521
2522         /* byte size and parity */
2523
2524         switch (cflag & CSIZE) {
2525         case CS5: info->params.data_bits = 5; break;
2526         case CS6: info->params.data_bits = 6; break;
2527         case CS7: info->params.data_bits = 7; break;
2528         case CS8: info->params.data_bits = 8; break;
2529         default:  info->params.data_bits = 7; break;
2530         }
2531
2532         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2533
2534         if (cflag & PARENB)
2535                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2536         else
2537                 info->params.parity = ASYNC_PARITY_NONE;
2538
2539         /* calculate number of jiffies to transmit a full
2540          * FIFO (32 bytes) at specified data rate
2541          */
2542         bits_per_char = info->params.data_bits +
2543                         info->params.stop_bits + 1;
2544
2545         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2546
2547         if (info->params.data_rate) {
2548                 info->timeout = (32*HZ*bits_per_char) /
2549                                 info->params.data_rate;
2550         }
2551         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2552
2553         if (cflag & CRTSCTS)
2554                 info->port.flags |= ASYNC_CTS_FLOW;
2555         else
2556                 info->port.flags &= ~ASYNC_CTS_FLOW;
2557
2558         if (cflag & CLOCAL)
2559                 info->port.flags &= ~ASYNC_CHECK_CD;
2560         else
2561                 info->port.flags |= ASYNC_CHECK_CD;
2562
2563         /* process tty input control flags */
2564
2565         info->read_status_mask = IRQ_RXOVER;
2566         if (I_INPCK(info->port.tty))
2567                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2568         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2569                 info->read_status_mask |= MASK_BREAK;
2570         if (I_IGNPAR(info->port.tty))
2571                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2572         if (I_IGNBRK(info->port.tty)) {
2573                 info->ignore_status_mask |= MASK_BREAK;
2574                 /* If ignoring parity and break indicators, ignore
2575                  * overruns too.  (For real raw support).
2576                  */
2577                 if (I_IGNPAR(info->port.tty))
2578                         info->ignore_status_mask |= MASK_OVERRUN;
2579         }
2580
2581         program_hw(info);
2582 }
2583
2584 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2585 {
2586         DBGINFO(("%s get_stats\n",  info->device_name));
2587         if (!user_icount) {
2588                 memset(&info->icount, 0, sizeof(info->icount));
2589         } else {
2590                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2591                         return -EFAULT;
2592         }
2593         return 0;
2594 }
2595
2596 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2597 {
2598         DBGINFO(("%s get_params\n", info->device_name));
2599         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2600                 return -EFAULT;
2601         return 0;
2602 }
2603
2604 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2605 {
2606         unsigned long flags;
2607         MGSL_PARAMS tmp_params;
2608
2609         DBGINFO(("%s set_params\n", info->device_name));
2610         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2611                 return -EFAULT;
2612
2613         spin_lock_irqsave(&info->lock, flags);
2614         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2615         spin_unlock_irqrestore(&info->lock, flags);
2616
2617         change_params(info);
2618
2619         return 0;
2620 }
2621
2622 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2623 {
2624         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2625         if (put_user(info->idle_mode, idle_mode))
2626                 return -EFAULT;
2627         return 0;
2628 }
2629
2630 static int set_txidle(struct slgt_info *info, int idle_mode)
2631 {
2632         unsigned long flags;
2633         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2634         spin_lock_irqsave(&info->lock,flags);
2635         info->idle_mode = idle_mode;
2636         if (info->params.mode != MGSL_MODE_ASYNC)
2637                 tx_set_idle(info);
2638         spin_unlock_irqrestore(&info->lock,flags);
2639         return 0;
2640 }
2641
2642 static int tx_enable(struct slgt_info *info, int enable)
2643 {
2644         unsigned long flags;
2645         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2646         spin_lock_irqsave(&info->lock,flags);
2647         if (enable) {
2648                 if (!info->tx_enabled)
2649                         tx_start(info);
2650         } else {
2651                 if (info->tx_enabled)
2652                         tx_stop(info);
2653         }
2654         spin_unlock_irqrestore(&info->lock,flags);
2655         return 0;
2656 }
2657
2658 /*
2659  * abort transmit HDLC frame
2660  */
2661 static int tx_abort(struct slgt_info *info)
2662 {
2663         unsigned long flags;
2664         DBGINFO(("%s tx_abort\n", info->device_name));
2665         spin_lock_irqsave(&info->lock,flags);
2666         tdma_reset(info);
2667         spin_unlock_irqrestore(&info->lock,flags);
2668         return 0;
2669 }
2670
2671 static int rx_enable(struct slgt_info *info, int enable)
2672 {
2673         unsigned long flags;
2674         unsigned int rbuf_fill_level;
2675         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2676         spin_lock_irqsave(&info->lock,flags);
2677         /*
2678          * enable[31..16] = receive DMA buffer fill level
2679          * 0 = noop (leave fill level unchanged)
2680          * fill level must be multiple of 4 and <= buffer size
2681          */
2682         rbuf_fill_level = ((unsigned int)enable) >> 16;
2683         if (rbuf_fill_level) {
2684                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2685                         spin_unlock_irqrestore(&info->lock, flags);
2686                         return -EINVAL;
2687                 }
2688                 info->rbuf_fill_level = rbuf_fill_level;
2689                 rx_stop(info); /* restart receiver to use new fill level */
2690         }
2691
2692         /*
2693          * enable[1..0] = receiver enable command
2694          * 0 = disable
2695          * 1 = enable
2696          * 2 = enable or force hunt mode if already enabled
2697          */
2698         enable &= 3;
2699         if (enable) {
2700                 if (!info->rx_enabled)
2701                         rx_start(info);
2702                 else if (enable == 2) {
2703                         /* force hunt mode (write 1 to RCR[3]) */
2704                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2705                 }
2706         } else {
2707                 if (info->rx_enabled)
2708                         rx_stop(info);
2709         }
2710         spin_unlock_irqrestore(&info->lock,flags);
2711         return 0;
2712 }
2713
2714 /*
2715  *  wait for specified event to occur
2716  */
2717 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2718 {
2719         unsigned long flags;
2720         int s;
2721         int rc=0;
2722         struct mgsl_icount cprev, cnow;
2723         int events;
2724         int mask;
2725         struct  _input_signal_events oldsigs, newsigs;
2726         DECLARE_WAITQUEUE(wait, current);
2727
2728         if (get_user(mask, mask_ptr))
2729                 return -EFAULT;
2730
2731         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2732
2733         spin_lock_irqsave(&info->lock,flags);
2734
2735         /* return immediately if state matches requested events */
2736         get_signals(info);
2737         s = info->signals;
2738
2739         events = mask &
2740                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2741                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2742                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2743                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2744         if (events) {
2745                 spin_unlock_irqrestore(&info->lock,flags);
2746                 goto exit;
2747         }
2748
2749         /* save current irq counts */
2750         cprev = info->icount;
2751         oldsigs = info->input_signal_events;
2752
2753         /* enable hunt and idle irqs if needed */
2754         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2755                 unsigned short val = rd_reg16(info, SCR);
2756                 if (!(val & IRQ_RXIDLE))
2757                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2758         }
2759
2760         set_current_state(TASK_INTERRUPTIBLE);
2761         add_wait_queue(&info->event_wait_q, &wait);
2762
2763         spin_unlock_irqrestore(&info->lock,flags);
2764
2765         for(;;) {
2766                 schedule();
2767                 if (signal_pending(current)) {
2768                         rc = -ERESTARTSYS;
2769                         break;
2770                 }
2771
2772                 /* get current irq counts */
2773                 spin_lock_irqsave(&info->lock,flags);
2774                 cnow = info->icount;
2775                 newsigs = info->input_signal_events;
2776                 set_current_state(TASK_INTERRUPTIBLE);
2777                 spin_unlock_irqrestore(&info->lock,flags);
2778
2779                 /* if no change, wait aborted for some reason */
2780                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2781                     newsigs.dsr_down == oldsigs.dsr_down &&
2782                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2783                     newsigs.dcd_down == oldsigs.dcd_down &&
2784                     newsigs.cts_up   == oldsigs.cts_up   &&
2785                     newsigs.cts_down == oldsigs.cts_down &&
2786                     newsigs.ri_up    == oldsigs.ri_up    &&
2787                     newsigs.ri_down  == oldsigs.ri_down  &&
2788                     cnow.exithunt    == cprev.exithunt   &&
2789                     cnow.rxidle      == cprev.rxidle) {
2790                         rc = -EIO;
2791                         break;
2792                 }
2793
2794                 events = mask &
2795                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2796                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2797                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2798                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2799                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2800                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2801                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2802                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2803                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2804                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2805                 if (events)
2806                         break;
2807
2808                 cprev = cnow;
2809                 oldsigs = newsigs;
2810         }
2811
2812         remove_wait_queue(&info->event_wait_q, &wait);
2813         set_current_state(TASK_RUNNING);
2814
2815
2816         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2817                 spin_lock_irqsave(&info->lock,flags);
2818                 if (!waitqueue_active(&info->event_wait_q)) {
2819                         /* disable enable exit hunt mode/idle rcvd IRQs */
2820                         wr_reg16(info, SCR,
2821                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2822                 }
2823                 spin_unlock_irqrestore(&info->lock,flags);
2824         }
2825 exit:
2826         if (rc == 0)
2827                 rc = put_user(events, mask_ptr);
2828         return rc;
2829 }
2830
2831 static int get_interface(struct slgt_info *info, int __user *if_mode)
2832 {
2833         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2834         if (put_user(info->if_mode, if_mode))
2835                 return -EFAULT;
2836         return 0;
2837 }
2838
2839 static int set_interface(struct slgt_info *info, int if_mode)
2840 {
2841         unsigned long flags;
2842         unsigned short val;
2843
2844         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2845         spin_lock_irqsave(&info->lock,flags);
2846         info->if_mode = if_mode;
2847
2848         msc_set_vcr(info);
2849
2850         /* TCR (tx control) 07  1=RTS driver control */
2851         val = rd_reg16(info, TCR);
2852         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2853                 val |= BIT7;
2854         else
2855                 val &= ~BIT7;
2856         wr_reg16(info, TCR, val);
2857
2858         spin_unlock_irqrestore(&info->lock,flags);
2859         return 0;
2860 }
2861
2862 /*
2863  * set general purpose IO pin state and direction
2864  *
2865  * user_gpio fields:
2866  * state   each bit indicates a pin state
2867  * smask   set bit indicates pin state to set
2868  * dir     each bit indicates a pin direction (0=input, 1=output)
2869  * dmask   set bit indicates pin direction to set
2870  */
2871 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2872 {
2873         unsigned long flags;
2874         struct gpio_desc gpio;
2875         __u32 data;
2876
2877         if (!info->gpio_present)
2878                 return -EINVAL;
2879         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2880                 return -EFAULT;
2881         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2882                  info->device_name, gpio.state, gpio.smask,
2883                  gpio.dir, gpio.dmask));
2884
2885         spin_lock_irqsave(&info->lock,flags);
2886         if (gpio.dmask) {
2887                 data = rd_reg32(info, IODR);
2888                 data |= gpio.dmask & gpio.dir;
2889                 data &= ~(gpio.dmask & ~gpio.dir);
2890                 wr_reg32(info, IODR, data);
2891         }
2892         if (gpio.smask) {
2893                 data = rd_reg32(info, IOVR);
2894                 data |= gpio.smask & gpio.state;
2895                 data &= ~(gpio.smask & ~gpio.state);
2896                 wr_reg32(info, IOVR, data);
2897         }
2898         spin_unlock_irqrestore(&info->lock,flags);
2899
2900         return 0;
2901 }
2902
2903 /*
2904  * get general purpose IO pin state and direction
2905  */
2906 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2907 {
2908         struct gpio_desc gpio;
2909         if (!info->gpio_present)
2910                 return -EINVAL;
2911         gpio.state = rd_reg32(info, IOVR);
2912         gpio.smask = 0xffffffff;
2913         gpio.dir   = rd_reg32(info, IODR);
2914         gpio.dmask = 0xffffffff;
2915         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2916                 return -EFAULT;
2917         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2918                  info->device_name, gpio.state, gpio.dir));
2919         return 0;
2920 }
2921
2922 /*
2923  * conditional wait facility
2924  */
2925 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2926 {
2927         init_waitqueue_head(&w->q);
2928         init_waitqueue_entry(&w->wait, current);
2929         w->data = data;
2930 }
2931
2932 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2933 {
2934         set_current_state(TASK_INTERRUPTIBLE);
2935         add_wait_queue(&w->q, &w->wait);
2936         w->next = *head;
2937         *head = w;
2938 }
2939
2940 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2941 {
2942         struct cond_wait *w, *prev;
2943         remove_wait_queue(&cw->q, &cw->wait);
2944         set_current_state(TASK_RUNNING);
2945         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2946                 if (w == cw) {
2947                         if (prev != NULL)
2948                                 prev->next = w->next;
2949                         else
2950                                 *head = w->next;
2951                         break;
2952                 }
2953         }
2954 }
2955
2956 static void flush_cond_wait(struct cond_wait **head)
2957 {
2958         while (*head != NULL) {
2959                 wake_up_interruptible(&(*head)->q);
2960                 *head = (*head)->next;
2961         }
2962 }
2963
2964 /*
2965  * wait for general purpose I/O pin(s) to enter specified state
2966  *
2967  * user_gpio fields:
2968  * state - bit indicates target pin state
2969  * smask - set bit indicates watched pin
2970  *
2971  * The wait ends when at least one watched pin enters the specified
2972  * state. When 0 (no error) is returned, user_gpio->state is set to the
2973  * state of all GPIO pins when the wait ends.
2974  *
2975  * Note: Each pin may be a dedicated input, dedicated output, or
2976  * configurable input/output. The number and configuration of pins
2977  * varies with the specific adapter model. Only input pins (dedicated
2978  * or configured) can be monitored with this function.
2979  */
2980 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2981 {
2982         unsigned long flags;
2983         int rc = 0;
2984         struct gpio_desc gpio;
2985         struct cond_wait wait;
2986         u32 state;
2987
2988         if (!info->gpio_present)
2989                 return -EINVAL;
2990         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2991                 return -EFAULT;
2992         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2993                  info->device_name, gpio.state, gpio.smask));
2994         /* ignore output pins identified by set IODR bit */
2995         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2996                 return -EINVAL;
2997         init_cond_wait(&wait, gpio.smask);
2998
2999         spin_lock_irqsave(&info->lock, flags);
3000         /* enable interrupts for watched pins */
3001         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3002         /* get current pin states */
3003         state = rd_reg32(info, IOVR);
3004
3005         if (gpio.smask & ~(state ^ gpio.state)) {
3006                 /* already in target state */
3007                 gpio.state = state;
3008         } else {
3009                 /* wait for target state */
3010                 add_cond_wait(&info->gpio_wait_q, &wait);
3011                 spin_unlock_irqrestore(&info->lock, flags);
3012                 schedule();
3013                 if (signal_pending(current))
3014                         rc = -ERESTARTSYS;
3015                 else
3016                         gpio.state = wait.data;
3017                 spin_lock_irqsave(&info->lock, flags);
3018                 remove_cond_wait(&info->gpio_wait_q, &wait);
3019         }
3020
3021         /* disable all GPIO interrupts if no waiting processes */
3022         if (info->gpio_wait_q == NULL)
3023                 wr_reg32(info, IOER, 0);
3024         spin_unlock_irqrestore(&info->lock,flags);
3025
3026         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3027                 rc = -EFAULT;
3028         return rc;
3029 }
3030
3031 static int modem_input_wait(struct slgt_info *info,int arg)
3032 {
3033         unsigned long flags;
3034         int rc;
3035         struct mgsl_icount cprev, cnow;
3036         DECLARE_WAITQUEUE(wait, current);
3037
3038         /* save current irq counts */
3039         spin_lock_irqsave(&info->lock,flags);
3040         cprev = info->icount;
3041         add_wait_queue(&info->status_event_wait_q, &wait);
3042         set_current_state(TASK_INTERRUPTIBLE);
3043         spin_unlock_irqrestore(&info->lock,flags);
3044
3045         for(;;) {
3046                 schedule();
3047                 if (signal_pending(current)) {
3048                         rc = -ERESTARTSYS;
3049                         break;
3050                 }
3051
3052                 /* get new irq counts */
3053                 spin_lock_irqsave(&info->lock,flags);
3054                 cnow = info->icount;
3055                 set_current_state(TASK_INTERRUPTIBLE);
3056                 spin_unlock_irqrestore(&info->lock,flags);
3057
3058                 /* if no change, wait aborted for some reason */
3059                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3060                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3061                         rc = -EIO;
3062                         break;
3063                 }
3064
3065                 /* check for change in caller specified modem input */
3066                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3067                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3068                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3069                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3070                         rc = 0;
3071                         break;
3072                 }
3073
3074                 cprev = cnow;
3075         }
3076         remove_wait_queue(&info->status_event_wait_q, &wait);
3077         set_current_state(TASK_RUNNING);
3078         return rc;
3079 }
3080
3081 /*
3082  *  return state of serial control and status signals
3083  */
3084 static int tiocmget(struct tty_struct *tty, struct file *file)
3085 {
3086         struct slgt_info *info = tty->driver_data;
3087         unsigned int result;
3088         unsigned long flags;
3089
3090         spin_lock_irqsave(&info->lock,flags);
3091         get_signals(info);
3092         spin_unlock_irqrestore(&info->lock,flags);
3093
3094         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3095                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3096                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3097                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3098                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3099                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3100
3101         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3102         return result;
3103 }
3104
3105 /*
3106  * set modem control signals (DTR/RTS)
3107  *
3108  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3109  *              TIOCMSET = set/clear signal values
3110  *      value   bit mask for command
3111  */
3112 static int tiocmset(struct tty_struct *tty, struct file *file,
3113                     unsigned int set, unsigned int clear)
3114 {
3115         struct slgt_info *info = tty->driver_data;
3116         unsigned long flags;
3117
3118         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3119
3120         if (set & TIOCM_RTS)
3121                 info->signals |= SerialSignal_RTS;
3122         if (set & TIOCM_DTR)
3123                 info->signals |= SerialSignal_DTR;
3124         if (clear & TIOCM_RTS)
3125                 info->signals &= ~SerialSignal_RTS;
3126         if (clear & TIOCM_DTR)
3127                 info->signals &= ~SerialSignal_DTR;
3128
3129         spin_lock_irqsave(&info->lock,flags);
3130         set_signals(info);
3131         spin_unlock_irqrestore(&info->lock,flags);
3132         return 0;
3133 }
3134
3135 static int carrier_raised(struct tty_port *port)
3136 {
3137         unsigned long flags;
3138         struct slgt_info *info = container_of(port, struct slgt_info, port);
3139
3140         spin_lock_irqsave(&info->lock,flags);
3141         get_signals(info);
3142         spin_unlock_irqrestore(&info->lock,flags);
3143         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3144 }
3145
3146 static void raise_dtr_rts(struct tty_port *port)
3147 {
3148         unsigned long flags;
3149         struct slgt_info *info = container_of(port, struct slgt_info, port);
3150
3151         spin_lock_irqsave(&info->lock,flags);
3152         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3153         set_signals(info);
3154         spin_unlock_irqrestore(&info->lock,flags);
3155 }
3156
3157
3158 /*
3159  *  block current process until the device is ready to open
3160  */
3161 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3162                            struct slgt_info *info)
3163 {
3164         DECLARE_WAITQUEUE(wait, current);
3165         int             retval;
3166         bool            do_clocal = false;
3167         bool            extra_count = false;
3168         unsigned long   flags;
3169         int             cd;
3170         struct tty_port *port = &info->port;
3171
3172         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3173
3174         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3175                 /* nonblock mode is set or port is not enabled */
3176                 port->flags |= ASYNC_NORMAL_ACTIVE;
3177                 return 0;
3178         }
3179
3180         if (tty->termios->c_cflag & CLOCAL)
3181                 do_clocal = true;
3182
3183         /* Wait for carrier detect and the line to become
3184          * free (i.e., not in use by the callout).  While we are in
3185          * this loop, port->count is dropped by one, so that
3186          * close() knows when to free things.  We restore it upon
3187          * exit, either normal or abnormal.
3188          */
3189
3190         retval = 0;
3191         add_wait_queue(&port->open_wait, &wait);
3192
3193         spin_lock_irqsave(&info->lock, flags);
3194         if (!tty_hung_up_p(filp)) {
3195                 extra_count = true;
3196                 port->count--;
3197         }
3198         spin_unlock_irqrestore(&info->lock, flags);
3199         port->blocked_open++;
3200
3201         while (1) {
3202                 if ((tty->termios->c_cflag & CBAUD))
3203                         tty_port_raise_dtr_rts(port);
3204
3205                 set_current_state(TASK_INTERRUPTIBLE);
3206
3207                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3208                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3209                                         -EAGAIN : -ERESTARTSYS;
3210                         break;
3211                 }
3212
3213                 cd = tty_port_carrier_raised(port);
3214
3215                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3216                         break;
3217
3218                 if (signal_pending(current)) {
3219                         retval = -ERESTARTSYS;
3220                         break;
3221                 }
3222
3223                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3224                 schedule();
3225         }
3226
3227         set_current_state(TASK_RUNNING);
3228         remove_wait_queue(&port->open_wait, &wait);
3229
3230         if (extra_count)
3231                 port->count++;
3232         port->blocked_open--;
3233
3234         if (!retval)
3235                 port->flags |= ASYNC_NORMAL_ACTIVE;
3236
3237         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3238         return retval;
3239 }
3240
3241 static int alloc_tmp_rbuf(struct slgt_info *info)
3242 {
3243         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3244         if (info->tmp_rbuf == NULL)
3245                 return -ENOMEM;
3246         return 0;
3247 }
3248
3249 static void free_tmp_rbuf(struct slgt_info *info)
3250 {
3251         kfree(info->tmp_rbuf);
3252         info->tmp_rbuf = NULL;
3253 }
3254
3255 /*
3256  * allocate DMA descriptor lists.
3257  */
3258 static int alloc_desc(struct slgt_info *info)
3259 {
3260         unsigned int i;
3261         unsigned int pbufs;
3262
3263         /* allocate memory to hold descriptor lists */
3264         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3265         if (info->bufs == NULL)
3266                 return -ENOMEM;
3267
3268         memset(info->bufs, 0, DESC_LIST_SIZE);
3269
3270         info->rbufs = (struct slgt_desc*)info->bufs;
3271         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3272
3273         pbufs = (unsigned int)info->bufs_dma_addr;
3274
3275         /*
3276          * Build circular lists of descriptors
3277          */
3278
3279         for (i=0; i < info->rbuf_count; i++) {
3280                 /* physical address of this descriptor */
3281                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3282
3283                 /* physical address of next descriptor */
3284                 if (i == info->rbuf_count - 1)
3285                         info->rbufs[i].next = cpu_to_le32(pbufs);
3286                 else
3287                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3288                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3289         }
3290
3291         for (i=0; i < info->tbuf_count; i++) {
3292                 /* physical address of this descriptor */
3293                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3294
3295                 /* physical address of next descriptor */
3296                 if (i == info->tbuf_count - 1)
3297                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3298                 else
3299                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3300         }
3301
3302         return 0;
3303 }
3304
3305 static void free_desc(struct slgt_info *info)
3306 {
3307         if (info->bufs != NULL) {
3308                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3309                 info->bufs  = NULL;
3310                 info->rbufs = NULL;
3311                 info->tbufs = NULL;
3312         }
3313 }
3314
3315 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3316 {
3317         int i;
3318         for (i=0; i < count; i++) {
3319                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3320                         return -ENOMEM;
3321                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3322         }
3323         return 0;
3324 }
3325
3326 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3327 {
3328         int i;
3329         for (i=0; i < count; i++) {
3330                 if (bufs[i].buf == NULL)
3331                         continue;
3332                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3333                 bufs[i].buf = NULL;
3334         }
3335 }
3336
3337 static int alloc_dma_bufs(struct slgt_info *info)
3338 {
3339         info->rbuf_count = 32;
3340         info->tbuf_count = 32;
3341
3342         if (alloc_desc(info) < 0 ||
3343             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3344             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3345             alloc_tmp_rbuf(info) < 0) {
3346                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3347                 return -ENOMEM;
3348         }
3349         reset_rbufs(info);
3350         return 0;
3351 }
3352
3353 static void free_dma_bufs(struct slgt_info *info)
3354 {
3355         if (info->bufs) {
3356                 free_bufs(info, info->rbufs, info->rbuf_count);
3357                 free_bufs(info, info->tbufs, info->tbuf_count);
3358                 free_desc(info);
3359         }
3360         free_tmp_rbuf(info);
3361 }
3362
3363 static int claim_resources(struct slgt_info *info)
3364 {
3365         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3366                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3367                         info->device_name, info->phys_reg_addr));
3368                 info->init_error = DiagStatus_AddressConflict;
3369                 goto errout;
3370         }
3371         else
3372                 info->reg_addr_requested = true;
3373
3374         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3375         if (!info->reg_addr) {
3376                 DBGERR(("%s cant map device registers, addr=%08X\n",
3377                         info->device_name, info->phys_reg_addr));
3378                 info->init_error = DiagStatus_CantAssignPciResources;
3379                 goto errout;
3380         }
3381         return 0;
3382
3383 errout:
3384         release_resources(info);
3385         return -ENODEV;
3386 }
3387
3388 static void release_resources(struct slgt_info *info)
3389 {
3390         if (info->irq_requested) {
3391                 free_irq(info->irq_level, info);
3392                 info->irq_requested = false;
3393         }
3394
3395         if (info->reg_addr_requested) {
3396                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3397                 info->reg_addr_requested = false;
3398         }
3399
3400         if (info->reg_addr) {
3401                 iounmap(info->reg_addr);
3402                 info->reg_addr = NULL;
3403         }
3404 }
3405
3406 /* Add the specified device instance data structure to the
3407  * global linked list of devices and increment the device count.
3408  */
3409 static void add_device(struct slgt_info *info)
3410 {
3411         char *devstr;
3412
3413         info->next_device = NULL;
3414         info->line = slgt_device_count;
3415         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3416
3417         if (info->line < MAX_DEVICES) {
3418                 if (maxframe[info->line])
3419                         info->max_frame_size = maxframe[info->line];
3420         }
3421
3422         slgt_device_count++;
3423
3424         if (!slgt_device_list)
3425                 slgt_device_list = info;
3426         else {
3427                 struct slgt_info *current_dev = slgt_device_list;
3428                 while(current_dev->next_device)
3429                         current_dev = current_dev->next_device;
3430                 current_dev->next_device = info;
3431         }
3432
3433         if (info->max_frame_size < 4096)
3434                 info->max_frame_size = 4096;
3435         else if (info->max_frame_size > 65535)
3436                 info->max_frame_size = 65535;
3437
3438         switch(info->pdev->device) {
3439         case SYNCLINK_GT_DEVICE_ID:
3440                 devstr = "GT";
3441                 break;
3442         case SYNCLINK_GT2_DEVICE_ID:
3443                 devstr = "GT2";
3444                 break;
3445         case SYNCLINK_GT4_DEVICE_ID:
3446                 devstr = "GT4";
3447                 break;
3448         case SYNCLINK_AC_DEVICE_ID:
3449                 devstr = "AC";
3450                 info->params.mode = MGSL_MODE_ASYNC;
3451                 break;
3452         default:
3453                 devstr = "(unknown model)";
3454         }
3455         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3456                 devstr, info->device_name, info->phys_reg_addr,
3457                 info->irq_level, info->max_frame_size);
3458
3459 #if SYNCLINK_GENERIC_HDLC
3460         hdlcdev_init(info);
3461 #endif
3462 }
3463
3464 static const struct tty_port_operations slgt_port_ops = {
3465         .carrier_raised = carrier_raised,
3466         .raise_dtr_rts = raise_dtr_rts,
3467 };
3468
3469 /*
3470  *  allocate device instance structure, return NULL on failure
3471  */
3472 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3473 {
3474         struct slgt_info *info;
3475
3476         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3477
3478         if (!info) {
3479                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3480                         driver_name, adapter_num, port_num));
3481         } else {
3482                 tty_port_init(&info->port);
3483                 info->port.ops = &slgt_port_ops;
3484                 info->magic = MGSL_MAGIC;
3485                 INIT_WORK(&info->task, bh_handler);
3486                 info->max_frame_size = 4096;
3487                 info->rbuf_fill_level = DMABUFSIZE;
3488                 info->port.close_delay = 5*HZ/10;
3489                 info->port.closing_wait = 30*HZ;
3490                 init_waitqueue_head(&info->status_event_wait_q);
3491                 init_waitqueue_head(&info->event_wait_q);
3492                 spin_lock_init(&info->netlock);
3493                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3494                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3495                 info->adapter_num = adapter_num;
3496                 info->port_num = port_num;
3497
3498                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3499                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3500
3501                 /* Copy configuration info to device instance data */
3502                 info->pdev = pdev;
3503                 info->irq_level = pdev->irq;
3504                 info->phys_reg_addr = pci_resource_start(pdev,0);
3505
3506                 info->bus_type = MGSL_BUS_TYPE_PCI;
3507                 info->irq_flags = IRQF_SHARED;
3508
3509                 info->init_error = -1; /* assume error, set to 0 on successful init */
3510         }
3511
3512         return info;
3513 }
3514
3515 static void device_init(int adapter_num, struct pci_dev *pdev)
3516 {
3517         struct slgt_info *port_array[SLGT_MAX_PORTS];
3518         int i;
3519         int port_count = 1;
3520
3521         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3522                 port_count = 2;
3523         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3524                 port_count = 4;
3525
3526         /* allocate device instances for all ports */
3527         for (i=0; i < port_count; ++i) {
3528                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3529                 if (port_array[i] == NULL) {
3530                         for (--i; i >= 0; --i)
3531                                 kfree(port_array[i]);
3532                         return;
3533                 }
3534         }
3535
3536         /* give copy of port_array to all ports and add to device list  */
3537         for (i=0; i < port_count; ++i) {
3538                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3539                 add_device(port_array[i]);
3540                 port_array[i]->port_count = port_count;
3541                 spin_lock_init(&port_array[i]->lock);
3542         }
3543
3544         /* Allocate and claim adapter resources */
3545         if (!claim_resources(port_array[0])) {
3546
3547                 alloc_dma_bufs(port_array[0]);
3548
3549                 /* copy resource information from first port to others */
3550                 for (i = 1; i < port_count; ++i) {
3551                         port_array[i]->lock      = port_array[0]->lock;
3552                         port_array[i]->irq_level = port_array[0]->irq_level;
3553                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3554                         alloc_dma_bufs(port_array[i]);
3555                 }
3556
3557                 if (request_irq(port_array[0]->irq_level,
3558                                         slgt_interrupt,
3559                                         port_array[0]->irq_flags,
3560                                         port_array[0]->device_name,
3561                                         port_array[0]) < 0) {
3562                         DBGERR(("%s request_irq failed IRQ=%d\n",
3563                                 port_array[0]->device_name,
3564                                 port_array[0]->irq_level));
3565                 } else {
3566                         port_array[0]->irq_requested = true;
3567                         adapter_test(port_array[0]);
3568                         for (i=1 ; i < port_count ; i++) {
3569                                 port_array[i]->init_error = port_array[0]->init_error;
3570                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3571                         }
3572                 }
3573         }
3574
3575         for (i=0; i < port_count; ++i)
3576                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3577 }
3578
3579 static int __devinit init_one(struct pci_dev *dev,
3580                               const struct pci_device_id *ent)
3581 {
3582         if (pci_enable_device(dev)) {
3583                 printk("error enabling pci device %p\n", dev);
3584                 return -EIO;
3585         }
3586         pci_set_master(dev);
3587         device_init(slgt_device_count, dev);
3588         return 0;
3589 }
3590
3591 static void __devexit remove_one(struct pci_dev *dev)
3592 {
3593 }
3594
3595 static const struct tty_operations ops = {
3596         .open = open,
3597         .close = close,
3598         .write = write,
3599         .put_char = put_char,
3600         .flush_chars = flush_chars,
3601         .write_room = write_room,
3602         .chars_in_buffer = chars_in_buffer,
3603         .flush_buffer = flush_buffer,
3604         .ioctl = ioctl,
3605         .compat_ioctl = slgt_compat_ioctl,
3606         .throttle = throttle,
3607         .unthrottle = unthrottle,
3608         .send_xchar = send_xchar,
3609         .break_ctl = set_break,
3610         .wait_until_sent = wait_until_sent,
3611         .read_proc = read_proc,
3612         .set_termios = set_termios,
3613         .stop = tx_hold,
3614         .start = tx_release,
3615         .hangup = hangup,
3616         .tiocmget = tiocmget,
3617         .tiocmset = tiocmset,
3618 };
3619
3620 static void slgt_cleanup(void)
3621 {
3622         int rc;
3623         struct slgt_info *info;
3624         struct slgt_info *tmp;
3625
3626         printk("unload %s %s\n", driver_name, driver_version);
3627
3628         if (serial_driver) {
3629                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3630                         tty_unregister_device(serial_driver, info->line);
3631                 if ((rc = tty_unregister_driver(serial_driver)))
3632                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3633                 put_tty_driver(serial_driver);
3634         }
3635
3636         /* reset devices */
3637         info = slgt_device_list;
3638         while(info) {
3639                 reset_port(info);
3640                 info = info->next_device;
3641         }
3642
3643         /* release devices */
3644         info = slgt_device_list;
3645         while(info) {
3646 #if SYNCLINK_GENERIC_HDLC
3647                 hdlcdev_exit(info);
3648 #endif
3649                 free_dma_bufs(info);
3650                 free_tmp_rbuf(info);
3651                 if (info->port_num == 0)
3652                         release_resources(info);
3653                 tmp = info;
3654                 info = info->next_device;
3655                 kfree(tmp);
3656         }
3657
3658         if (pci_registered)
3659                 pci_unregister_driver(&pci_driver);
3660 }
3661
3662 /*
3663  *  Driver initialization entry point.
3664  */
3665 static int __init slgt_init(void)
3666 {
3667         int rc;
3668
3669         printk("%s %s\n", driver_name, driver_version);
3670
3671         serial_driver = alloc_tty_driver(MAX_DEVICES);
3672         if (!serial_driver) {
3673                 printk("%s can't allocate tty driver\n", driver_name);
3674                 return -ENOMEM;
3675         }
3676
3677         /* Initialize the tty_driver structure */
3678
3679         serial_driver->owner = THIS_MODULE;
3680         serial_driver->driver_name = tty_driver_name;
3681         serial_driver->name = tty_dev_prefix;
3682         serial_driver->major = ttymajor;
3683         serial_driver->minor_start = 64;
3684         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3685         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3686         serial_driver->init_termios = tty_std_termios;
3687         serial_driver->init_termios.c_cflag =
3688                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3689         serial_driver->init_termios.c_ispeed = 9600;
3690         serial_driver->init_termios.c_ospeed = 9600;
3691         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3692         tty_set_operations(serial_driver, &ops);
3693         if ((rc = tty_register_driver(serial_driver)) < 0) {
3694                 DBGERR(("%s can't register serial driver\n", driver_name));
3695                 put_tty_driver(serial_driver);
3696                 serial_driver = NULL;
3697                 goto error;
3698         }
3699
3700         printk("%s %s, tty major#%d\n",
3701                 driver_name, driver_version,
3702                 serial_driver->major);
3703
3704         slgt_device_count = 0;
3705         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3706                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3707                 goto error;
3708         }
3709         pci_registered = true;
3710
3711         if (!slgt_device_list)
3712                 printk("%s no devices found\n",driver_name);
3713
3714         return 0;
3715
3716 error:
3717         slgt_cleanup();
3718         return rc;
3719 }
3720
3721 static void __exit slgt_exit(void)
3722 {
3723         slgt_cleanup();
3724 }
3725
3726 module_init(slgt_init);
3727 module_exit(slgt_exit);
3728
3729 /*
3730  * register access routines
3731  */
3732
3733 #define CALC_REGADDR() \
3734         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3735         if (addr >= 0x80) \
3736                 reg_addr += (info->port_num) * 32;
3737
3738 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3739 {
3740         CALC_REGADDR();
3741         return readb((void __iomem *)reg_addr);
3742 }
3743
3744 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3745 {
3746         CALC_REGADDR();
3747         writeb(value, (void __iomem *)reg_addr);
3748 }
3749
3750 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3751 {
3752         CALC_REGADDR();
3753         return readw((void __iomem *)reg_addr);
3754 }
3755
3756 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3757 {
3758         CALC_REGADDR();
3759         writew(value, (void __iomem *)reg_addr);
3760 }
3761
3762 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3763 {
3764         CALC_REGADDR();
3765         return readl((void __iomem *)reg_addr);
3766 }
3767
3768 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3769 {
3770         CALC_REGADDR();
3771         writel(value, (void __iomem *)reg_addr);
3772 }
3773
3774 static void rdma_reset(struct slgt_info *info)
3775 {
3776         unsigned int i;
3777
3778         /* set reset bit */
3779         wr_reg32(info, RDCSR, BIT1);
3780
3781         /* wait for enable bit cleared */
3782         for(i=0 ; i < 1000 ; i++)
3783                 if (!(rd_reg32(info, RDCSR) & BIT0))
3784                         break;
3785 }
3786
3787 static void tdma_reset(struct slgt_info *info)
3788 {
3789         unsigned int i;
3790
3791         /* set reset bit */
3792         wr_reg32(info, TDCSR, BIT1);
3793
3794         /* wait for enable bit cleared */
3795         for(i=0 ; i < 1000 ; i++)
3796                 if (!(rd_reg32(info, TDCSR) & BIT0))
3797                         break;
3798 }
3799
3800 /*
3801  * enable internal loopback
3802  * TxCLK and RxCLK are generated from BRG
3803  * and TxD is looped back to RxD internally.
3804  */
3805 static void enable_loopback(struct slgt_info *info)
3806 {
3807         /* SCR (serial control) BIT2=looopback enable */
3808         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3809
3810         if (info->params.mode != MGSL_MODE_ASYNC) {
3811                 /* CCR (clock control)
3812                  * 07..05  tx clock source (010 = BRG)
3813                  * 04..02  rx clock source (010 = BRG)
3814                  * 01      auxclk enable   (0 = disable)
3815                  * 00      BRG enable      (1 = enable)
3816                  *
3817                  * 0100 1001
3818                  */
3819                 wr_reg8(info, CCR, 0x49);
3820
3821                 /* set speed if available, otherwise use default */
3822                 if (info->params.clock_speed)
3823                         set_rate(info, info->params.clock_speed);
3824                 else
3825                         set_rate(info, 3686400);
3826         }
3827 }
3828
3829 /*
3830  *  set baud rate generator to specified rate
3831  */
3832 static void set_rate(struct slgt_info *info, u32 rate)
3833 {
3834         unsigned int div;
3835         static unsigned int osc = 14745600;
3836
3837         /* div = osc/rate - 1
3838          *
3839          * Round div up if osc/rate is not integer to
3840          * force to next slowest rate.
3841          */
3842
3843         if (rate) {
3844                 div = osc/rate;
3845                 if (!(osc % rate) && div)
3846                         div--;
3847                 wr_reg16(info, BDR, (unsigned short)div);
3848         }
3849 }
3850
3851 static void rx_stop(struct slgt_info *info)
3852 {
3853         unsigned short val;
3854
3855         /* disable and reset receiver */
3856         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3857         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3858         wr_reg16(info, RCR, val);                  /* clear reset bit */
3859
3860         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3861
3862         /* clear pending rx interrupts */
3863         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3864
3865         rdma_reset(info);
3866
3867         info->rx_enabled = false;
3868         info->rx_restart = false;
3869 }
3870
3871 static void rx_start(struct slgt_info *info)
3872 {
3873         unsigned short val;
3874
3875         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3876
3877         /* clear pending rx overrun IRQ */
3878         wr_reg16(info, SSR, IRQ_RXOVER);
3879
3880         /* reset and disable receiver */
3881         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3882         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3883         wr_reg16(info, RCR, val);                  /* clear reset bit */
3884
3885         rdma_reset(info);
3886         reset_rbufs(info);
3887
3888         /* set 1st descriptor address */
3889         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3890
3891         if (info->params.mode != MGSL_MODE_ASYNC) {
3892                 /* enable rx DMA and DMA interrupt */
3893                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3894         } else {
3895                 /* enable saving of rx status, rx DMA and DMA interrupt */
3896                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3897         }
3898
3899         slgt_irq_on(info, IRQ_RXOVER);
3900
3901         /* enable receiver */
3902         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3903
3904         info->rx_restart = false;
3905         info->rx_enabled = true;
3906 }
3907
3908 static void tx_start(struct slgt_info *info)
3909 {
3910         if (!info->tx_enabled) {
3911                 wr_reg16(info, TCR,
3912                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3913                 info->tx_enabled = true;
3914         }
3915
3916         if (info->tx_count) {
3917                 info->drop_rts_on_tx_done = false;
3918
3919                 if (info->params.mode != MGSL_MODE_ASYNC) {
3920                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3921                                 get_signals(info);
3922                                 if (!(info->signals & SerialSignal_RTS)) {
3923                                         info->signals |= SerialSignal_RTS;
3924                                         set_signals(info);
3925                                         info->drop_rts_on_tx_done = true;
3926                                 }
3927                         }
3928
3929                         slgt_irq_off(info, IRQ_TXDATA);
3930                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3931                         /* clear tx idle and underrun status bits */
3932                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3933                         if (info->params.mode == MGSL_MODE_HDLC)
3934                                 mod_timer(&info->tx_timer, jiffies +
3935                                                 msecs_to_jiffies(5000));
3936                 } else {
3937                         slgt_irq_off(info, IRQ_TXDATA);
3938                         slgt_irq_on(info, IRQ_TXIDLE);
3939                         /* clear tx idle status bit */
3940                         wr_reg16(info, SSR, IRQ_TXIDLE);
3941                 }
3942                 tdma_start(info);
3943                 info->tx_active = true;
3944         }
3945 }
3946
3947 /*
3948  * start transmit DMA if inactive and there are unsent buffers
3949  */
3950 static void tdma_start(struct slgt_info *info)
3951 {
3952         unsigned int i;
3953
3954         if (rd_reg32(info, TDCSR) & BIT0)
3955                 return;
3956
3957         /* transmit DMA inactive, check for unsent buffers */
3958         i = info->tbuf_start;
3959         while (!desc_count(info->tbufs[i])) {
3960                 if (++i == info->tbuf_count)
3961                         i = 0;
3962                 if (i == info->tbuf_current)
3963                         return;
3964         }
3965         info->tbuf_start = i;
3966
3967         /* there are unsent buffers, start transmit DMA */
3968
3969         /* reset needed if previous error condition */
3970         tdma_reset(info);
3971
3972         /* set 1st descriptor address */
3973         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3974         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3975 }
3976
3977 static void tx_stop(struct slgt_info *info)
3978 {
3979         unsigned short val;
3980
3981         del_timer(&info->tx_timer);
3982
3983         tdma_reset(info);
3984
3985         /* reset and disable transmitter */
3986         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3987         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3988
3989         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3990
3991         /* clear tx idle and underrun status bit */
3992         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3993
3994         reset_tbufs(info);
3995
3996         info->tx_enabled = false;
3997         info->tx_active = false;
3998 }
3999
4000 static void reset_port(struct slgt_info *info)
4001 {
4002         if (!info->reg_addr)
4003                 return;
4004
4005         tx_stop(info);
4006         rx_stop(info);
4007
4008         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4009         set_signals(info);
4010
4011         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4012 }
4013
4014 static void reset_adapter(struct slgt_info *info)
4015 {
4016         int i;
4017         for (i=0; i < info->port_count; ++i) {
4018                 if (info->port_array[i])
4019                         reset_port(info->port_array[i]);
4020         }
4021 }
4022
4023 static void async_mode(struct slgt_info *info)
4024 {
4025         unsigned short val;
4026
4027         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4028         tx_stop(info);
4029         rx_stop(info);
4030
4031         /* TCR (tx control)
4032          *
4033          * 15..13  mode, 010=async
4034          * 12..10  encoding, 000=NRZ
4035          * 09      parity enable
4036          * 08      1=odd parity, 0=even parity
4037          * 07      1=RTS driver control
4038          * 06      1=break enable
4039          * 05..04  character length
4040          *         00=5 bits
4041          *         01=6 bits
4042          *         10=7 bits
4043          *         11=8 bits
4044          * 03      0=1 stop bit, 1=2 stop bits
4045          * 02      reset
4046          * 01      enable
4047          * 00      auto-CTS enable
4048          */
4049         val = 0x4000;
4050
4051         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4052                 val |= BIT7;
4053
4054         if (info->params.parity != ASYNC_PARITY_NONE) {
4055                 val |= BIT9;
4056                 if (info->params.parity == ASYNC_PARITY_ODD)
4057                         val |= BIT8;
4058         }
4059
4060         switch (info->params.data_bits)
4061         {
4062         case 6: val |= BIT4; break;
4063         case 7: val |= BIT5; break;
4064         case 8: val |= BIT5 + BIT4; break;
4065         }
4066
4067         if (info->params.stop_bits != 1)
4068                 val |= BIT3;
4069
4070         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4071                 val |= BIT0;
4072
4073         wr_reg16(info, TCR, val);
4074
4075         /* RCR (rx control)
4076          *
4077          * 15..13  mode, 010=async
4078          * 12..10  encoding, 000=NRZ
4079          * 09      parity enable
4080          * 08      1=odd parity, 0=even parity
4081          * 07..06  reserved, must be 0
4082          * 05..04  character length
4083          *         00=5 bits
4084          *         01=6 bits
4085          *         10=7 bits
4086          *         11=8 bits
4087          * 03      reserved, must be zero
4088          * 02      reset
4089          * 01      enable
4090          * 00      auto-DCD enable
4091          */
4092         val = 0x4000;
4093
4094         if (info->params.parity != ASYNC_PARITY_NONE) {
4095                 val |= BIT9;
4096                 if (info->params.parity == ASYNC_PARITY_ODD)
4097                         val |= BIT8;
4098         }
4099
4100         switch (info->params.data_bits)
4101         {
4102         case 6: val |= BIT4; break;
4103         case 7: val |= BIT5; break;
4104         case 8: val |= BIT5 + BIT4; break;
4105         }
4106
4107         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4108                 val |= BIT0;
4109
4110         wr_reg16(info, RCR, val);
4111
4112         /* CCR (clock control)
4113          *
4114          * 07..05  011 = tx clock source is BRG/16
4115          * 04..02  010 = rx clock source is BRG
4116          * 01      0 = auxclk disabled
4117          * 00      1 = BRG enabled
4118          *
4119          * 0110 1001
4120          */
4121         wr_reg8(info, CCR, 0x69);
4122
4123         msc_set_vcr(info);
4124
4125         /* SCR (serial control)
4126          *
4127          * 15  1=tx req on FIFO half empty
4128          * 14  1=rx req on FIFO half full
4129          * 13  tx data  IRQ enable
4130          * 12  tx idle  IRQ enable
4131          * 11  rx break on IRQ enable
4132          * 10  rx data  IRQ enable
4133          * 09  rx break off IRQ enable
4134          * 08  overrun  IRQ enable
4135          * 07  DSR      IRQ enable
4136          * 06  CTS      IRQ enable
4137          * 05  DCD      IRQ enable
4138          * 04  RI       IRQ enable
4139          * 03  reserved, must be zero
4140          * 02  1=txd->rxd internal loopback enable
4141          * 01  reserved, must be zero
4142          * 00  1=master IRQ enable
4143          */
4144         val = BIT15 + BIT14 + BIT0;
4145         wr_reg16(info, SCR, val);
4146
4147         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4148
4149         set_rate(info, info->params.data_rate * 16);
4150
4151         if (info->params.loopback)
4152                 enable_loopback(info);
4153 }
4154
4155 static void sync_mode(struct slgt_info *info)
4156 {
4157         unsigned short val;
4158
4159         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4160         tx_stop(info);
4161         rx_stop(info);
4162
4163         /* TCR (tx control)
4164          *
4165          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4166          * 12..10  encoding
4167          * 09      CRC enable
4168          * 08      CRC32
4169          * 07      1=RTS driver control
4170          * 06      preamble enable
4171          * 05..04  preamble length
4172          * 03      share open/close flag
4173          * 02      reset
4174          * 01      enable
4175          * 00      auto-CTS enable
4176          */
4177         val = BIT2;
4178
4179         switch(info->params.mode) {
4180         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4181         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4182         case MGSL_MODE_RAW:      val |= BIT13; break;
4183         }
4184         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4185                 val |= BIT7;
4186
4187         switch(info->params.encoding)
4188         {
4189         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4190         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4191         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4192         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4193         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4194         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4195         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4196         }
4197
4198         switch (info->params.crc_type & HDLC_CRC_MASK)
4199         {
4200         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4201         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4202         }
4203
4204         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4205                 val |= BIT6;
4206
4207         switch (info->params.preamble_length)
4208         {
4209         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4210         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4211         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4212         }
4213
4214         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4215                 val |= BIT0;
4216
4217         wr_reg16(info, TCR, val);
4218
4219         /* TPR (transmit preamble) */
4220
4221         switch (info->params.preamble)
4222         {
4223         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4224         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4225         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4226         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4227         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4228         default:                          val = 0x7e; break;
4229         }
4230         wr_reg8(info, TPR, (unsigned char)val);
4231
4232         /* RCR (rx control)
4233          *
4234          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4235          * 12..10  encoding
4236          * 09      CRC enable
4237          * 08      CRC32
4238          * 07..03  reserved, must be 0
4239          * 02      reset
4240          * 01      enable
4241          * 00      auto-DCD enable
4242          */
4243         val = 0;
4244
4245         switch(info->params.mode) {
4246         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4247         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4248         case MGSL_MODE_RAW:      val |= BIT13; break;
4249         }
4250
4251         switch(info->params.encoding)
4252         {
4253         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4254         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4255         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4256         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4257         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4258         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4259         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4260         }
4261
4262         switch (info->params.crc_type & HDLC_CRC_MASK)
4263         {
4264         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4265         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4266         }
4267
4268         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4269                 val |= BIT0;
4270
4271         wr_reg16(info, RCR, val);
4272
4273         /* CCR (clock control)
4274          *
4275          * 07..05  tx clock source
4276          * 04..02  rx clock source
4277          * 01      auxclk enable
4278          * 00      BRG enable
4279          */
4280         val = 0;
4281
4282         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4283         {
4284                 // when RxC source is DPLL, BRG generates 16X DPLL
4285                 // reference clock, so take TxC from BRG/16 to get
4286                 // transmit clock at actual data rate
4287                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4288                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4289                 else
4290                         val |= BIT6;    /* 010, txclk = BRG */
4291         }
4292         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4293                 val |= BIT7;    /* 100, txclk = DPLL Input */
4294         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4295                 val |= BIT5;    /* 001, txclk = RXC Input */
4296
4297         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4298                 val |= BIT3;    /* 010, rxclk = BRG */
4299         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4300                 val |= BIT4;    /* 100, rxclk = DPLL */
4301         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4302                 val |= BIT2;    /* 001, rxclk = TXC Input */
4303
4304         if (info->params.clock_speed)
4305                 val |= BIT1 + BIT0;
4306
4307         wr_reg8(info, CCR, (unsigned char)val);
4308
4309         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4310         {
4311                 // program DPLL mode
4312                 switch(info->params.encoding)
4313                 {
4314                 case HDLC_ENCODING_BIPHASE_MARK:
4315                 case HDLC_ENCODING_BIPHASE_SPACE:
4316                         val = BIT7; break;
4317                 case HDLC_ENCODING_BIPHASE_LEVEL:
4318                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4319                         val = BIT7 + BIT6; break;
4320                 default: val = BIT6;    // NRZ encodings
4321                 }
4322                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4323
4324                 // DPLL requires a 16X reference clock from BRG
4325                 set_rate(info, info->params.clock_speed * 16);
4326         }
4327         else
4328                 set_rate(info, info->params.clock_speed);
4329
4330         tx_set_idle(info);
4331
4332         msc_set_vcr(info);
4333
4334         /* SCR (serial control)
4335          *
4336          * 15  1=tx req on FIFO half empty
4337          * 14  1=rx req on FIFO half full
4338          * 13  tx data  IRQ enable
4339          * 12  tx idle  IRQ enable
4340          * 11  underrun IRQ enable
4341          * 10  rx data  IRQ enable
4342          * 09  rx idle  IRQ enable
4343          * 08  overrun  IRQ enable
4344          * 07  DSR      IRQ enable
4345          * 06  CTS      IRQ enable
4346          * 05  DCD      IRQ enable
4347          * 04  RI       IRQ enable
4348          * 03  reserved, must be zero
4349          * 02  1=txd->rxd internal loopback enable
4350          * 01  reserved, must be zero
4351          * 00  1=master IRQ enable
4352          */
4353         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4354
4355         if (info->params.loopback)
4356                 enable_loopback(info);
4357 }
4358
4359 /*
4360  *  set transmit idle mode
4361  */
4362 static void tx_set_idle(struct slgt_info *info)
4363 {
4364         unsigned char val;
4365         unsigned short tcr;
4366
4367         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4368          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4369          */
4370         tcr = rd_reg16(info, TCR);
4371         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4372                 /* disable preamble, set idle size to 16 bits */
4373                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4374                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4375                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4376         } else if (!(tcr & BIT6)) {
4377                 /* preamble is disabled, set idle size to 8 bits */
4378                 tcr &= ~(BIT5 + BIT4);
4379         }
4380         wr_reg16(info, TCR, tcr);
4381
4382         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4383                 /* LSB of custom tx idle specified in tx idle register */
4384                 val = (unsigned char)(info->idle_mode & 0xff);
4385         } else {
4386                 /* standard 8 bit idle patterns */
4387                 switch(info->idle_mode)
4388                 {
4389                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4390                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4391                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4392                 case HDLC_TXIDLE_ZEROS:
4393                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4394                 default:                         val = 0xff;
4395                 }
4396         }
4397
4398         wr_reg8(info, TIR, val);
4399 }
4400
4401 /*
4402  * get state of V24 status (input) signals
4403  */
4404 static void get_signals(struct slgt_info *info)
4405 {
4406         unsigned short status = rd_reg16(info, SSR);
4407
4408         /* clear all serial signals except DTR and RTS */
4409         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4410
4411         if (status & BIT3)
4412                 info->signals |= SerialSignal_DSR;
4413         if (status & BIT2)
4414                 info->signals |= SerialSignal_CTS;
4415         if (status & BIT1)
4416                 info->signals |= SerialSignal_DCD;
4417         if (status & BIT0)
4418                 info->signals |= SerialSignal_RI;
4419 }
4420
4421 /*
4422  * set V.24 Control Register based on current configuration
4423  */
4424 static void msc_set_vcr(struct slgt_info *info)
4425 {
4426         unsigned char val = 0;
4427
4428         /* VCR (V.24 control)
4429          *
4430          * 07..04  serial IF select
4431          * 03      DTR
4432          * 02      RTS
4433          * 01      LL
4434          * 00      RL
4435          */
4436
4437         switch(info->if_mode & MGSL_INTERFACE_MASK)
4438         {
4439         case MGSL_INTERFACE_RS232:
4440                 val |= BIT5; /* 0010 */
4441                 break;
4442         case MGSL_INTERFACE_V35:
4443                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4444                 break;
4445         case MGSL_INTERFACE_RS422:
4446                 val |= BIT6; /* 0100 */
4447                 break;
4448         }
4449
4450         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4451                 val |= BIT4;
4452         if (info->signals & SerialSignal_DTR)
4453                 val |= BIT3;
4454         if (info->signals & SerialSignal_RTS)
4455                 val |= BIT2;
4456         if (info->if_mode & MGSL_INTERFACE_LL)
4457                 val |= BIT1;
4458         if (info->if_mode & MGSL_INTERFACE_RL)
4459                 val |= BIT0;
4460         wr_reg8(info, VCR, val);
4461 }
4462
4463 /*
4464  * set state of V24 control (output) signals
4465  */
4466 static void set_signals(struct slgt_info *info)
4467 {
4468         unsigned char val = rd_reg8(info, VCR);
4469         if (info->signals & SerialSignal_DTR)
4470                 val |= BIT3;
4471         else
4472                 val &= ~BIT3;
4473         if (info->signals & SerialSignal_RTS)
4474                 val |= BIT2;
4475         else
4476                 val &= ~BIT2;
4477         wr_reg8(info, VCR, val);
4478 }
4479
4480 /*
4481  * free range of receive DMA buffers (i to last)
4482  */
4483 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4484 {
4485         int done = 0;
4486
4487         while(!done) {
4488                 /* reset current buffer for reuse */
4489                 info->rbufs[i].status = 0;
4490                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4491                 if (i == last)
4492                         done = 1;
4493                 if (++i == info->rbuf_count)
4494                         i = 0;
4495         }
4496         info->rbuf_current = i;
4497 }
4498
4499 /*
4500  * mark all receive DMA buffers as free
4501  */
4502 static void reset_rbufs(struct slgt_info *info)
4503 {
4504         free_rbufs(info, 0, info->rbuf_count - 1);
4505 }
4506
4507 /*
4508  * pass receive HDLC frame to upper layer
4509  *
4510  * return true if frame available, otherwise false
4511  */
4512 static bool rx_get_frame(struct slgt_info *info)
4513 {
4514         unsigned int start, end;
4515         unsigned short status;
4516         unsigned int framesize = 0;
4517         unsigned long flags;
4518         struct tty_struct *tty = info->port.tty;
4519         unsigned char addr_field = 0xff;
4520         unsigned int crc_size = 0;
4521
4522         switch (info->params.crc_type & HDLC_CRC_MASK) {
4523         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4524         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4525         }
4526
4527 check_again:
4528
4529         framesize = 0;
4530         addr_field = 0xff;
4531         start = end = info->rbuf_current;
4532
4533         for (;;) {
4534                 if (!desc_complete(info->rbufs[end]))
4535                         goto cleanup;
4536
4537                 if (framesize == 0 && info->params.addr_filter != 0xff)
4538                         addr_field = info->rbufs[end].buf[0];
4539
4540                 framesize += desc_count(info->rbufs[end]);
4541
4542                 if (desc_eof(info->rbufs[end]))
4543                         break;
4544
4545                 if (++end == info->rbuf_count)
4546                         end = 0;
4547
4548                 if (end == info->rbuf_current) {
4549                         if (info->rx_enabled){
4550                                 spin_lock_irqsave(&info->lock,flags);
4551                                 rx_start(info);
4552                                 spin_unlock_irqrestore(&info->lock,flags);
4553                         }
4554                         goto cleanup;
4555                 }
4556         }
4557
4558         /* status
4559          *
4560          * 15      buffer complete
4561          * 14..06  reserved
4562          * 05..04  residue
4563          * 02      eof (end of frame)
4564          * 01      CRC error
4565          * 00      abort
4566          */
4567         status = desc_status(info->rbufs[end]);
4568
4569         /* ignore CRC bit if not using CRC (bit is undefined) */
4570         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4571                 status &= ~BIT1;
4572
4573         if (framesize == 0 ||
4574                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4575                 free_rbufs(info, start, end);
4576                 goto check_again;
4577         }
4578
4579         if (framesize < (2 + crc_size) || status & BIT0) {
4580                 info->icount.rxshort++;
4581                 framesize = 0;
4582         } else if (status & BIT1) {
4583                 info->icount.rxcrc++;
4584                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4585                         framesize = 0;
4586         }
4587
4588 #if SYNCLINK_GENERIC_HDLC
4589         if (framesize == 0) {
4590                 info->netdev->stats.rx_errors++;
4591                 info->netdev->stats.rx_frame_errors++;
4592         }
4593 #endif
4594
4595         DBGBH(("%s rx frame status=%04X size=%d\n",
4596                 info->device_name, status, framesize));
4597         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4598
4599         if (framesize) {
4600                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4601                         framesize -= crc_size;
4602                         crc_size = 0;
4603                 }
4604
4605                 if (framesize > info->max_frame_size + crc_size)
4606                         info->icount.rxlong++;
4607                 else {
4608                         /* copy dma buffer(s) to contiguous temp buffer */
4609                         int copy_count = framesize;
4610                         int i = start;
4611                         unsigned char *p = info->tmp_rbuf;
4612                         info->tmp_rbuf_count = framesize;
4613
4614                         info->icount.rxok++;
4615
4616                         while(copy_count) {
4617                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4618                                 memcpy(p, info->rbufs[i].buf, partial_count);
4619                                 p += partial_count;
4620                                 copy_count -= partial_count;
4621                                 if (++i == info->rbuf_count)
4622                                         i = 0;
4623                         }
4624
4625                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4626                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4627                                 framesize++;
4628                         }
4629
4630 #if SYNCLINK_GENERIC_HDLC
4631                         if (info->netcount)
4632                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4633                         else
4634 #endif
4635                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4636                 }
4637         }
4638         free_rbufs(info, start, end);
4639         return true;
4640
4641 cleanup:
4642         return false;
4643 }
4644
4645 /*
4646  * pass receive buffer (RAW synchronous mode) to tty layer
4647  * return true if buffer available, otherwise false
4648  */
4649 static bool rx_get_buf(struct slgt_info *info)
4650 {
4651         unsigned int i = info->rbuf_current;
4652         unsigned int count;
4653
4654         if (!desc_complete(info->rbufs[i]))
4655                 return false;
4656         count = desc_count(info->rbufs[i]);
4657         switch(info->params.mode) {
4658         case MGSL_MODE_MONOSYNC:
4659         case MGSL_MODE_BISYNC:
4660                 /* ignore residue in byte synchronous modes */
4661                 if (desc_residue(info->rbufs[i]))
4662                         count--;
4663                 break;
4664         }
4665         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4666         DBGINFO(("rx_get_buf size=%d\n", count));
4667         if (count)
4668                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4669                                   info->flag_buf, count);
4670         free_rbufs(info, i, i);
4671         return true;
4672 }
4673
4674 static void reset_tbufs(struct slgt_info *info)
4675 {
4676         unsigned int i;
4677         info->tbuf_current = 0;
4678         for (i=0 ; i < info->tbuf_count ; i++) {
4679                 info->tbufs[i].status = 0;
4680                 info->tbufs[i].count  = 0;
4681         }
4682 }
4683
4684 /*
4685  * return number of free transmit DMA buffers
4686  */
4687 static unsigned int free_tbuf_count(struct slgt_info *info)
4688 {
4689         unsigned int count = 0;
4690         unsigned int i = info->tbuf_current;
4691
4692         do
4693         {
4694                 if (desc_count(info->tbufs[i]))
4695                         break; /* buffer in use */
4696                 ++count;
4697                 if (++i == info->tbuf_count)
4698                         i=0;
4699         } while (i != info->tbuf_current);
4700
4701         /* if tx DMA active, last zero count buffer is in use */
4702         if (count && (rd_reg32(info, TDCSR) & BIT0))
4703                 --count;
4704
4705         return count;
4706 }
4707
4708 /*
4709  * return number of bytes in unsent transmit DMA buffers
4710  * and the serial controller tx FIFO
4711  */
4712 static unsigned int tbuf_bytes(struct slgt_info *info)
4713 {
4714         unsigned int total_count = 0;
4715         unsigned int i = info->tbuf_current;
4716         unsigned int reg_value;
4717         unsigned int count;
4718         unsigned int active_buf_count = 0;
4719
4720         /*
4721          * Add descriptor counts for all tx DMA buffers.
4722          * If count is zero (cleared by DMA controller after read),
4723          * the buffer is complete or is actively being read from.
4724          *
4725          * Record buf_count of last buffer with zero count starting
4726          * from current ring position. buf_count is mirror
4727          * copy of count and is not cleared by serial controller.
4728          * If DMA controller is active, that buffer is actively
4729          * being read so add to total.
4730          */
4731         do {
4732                 count = desc_count(info->tbufs[i]);
4733                 if (count)
4734                         total_count += count;
4735                 else if (!total_count)
4736                         active_buf_count = info->tbufs[i].buf_count;
4737                 if (++i == info->tbuf_count)
4738                         i = 0;
4739         } while (i != info->tbuf_current);
4740
4741         /* read tx DMA status register */
4742         reg_value = rd_reg32(info, TDCSR);
4743
4744         /* if tx DMA active, last zero count buffer is in use */
4745         if (reg_value & BIT0)
4746                 total_count += active_buf_count;
4747
4748         /* add tx FIFO count = reg_value[15..8] */
4749         total_count += (reg_value >> 8) & 0xff;
4750
4751         /* if transmitter active add one byte for shift register */
4752         if (info->tx_active)
4753                 total_count++;
4754
4755         return total_count;
4756 }
4757
4758 /*
4759  * load transmit DMA buffer(s) with data
4760  */
4761 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4762 {
4763         unsigned short count;
4764         unsigned int i;
4765         struct slgt_desc *d;
4766
4767         if (size == 0)
4768                 return;
4769
4770         DBGDATA(info, buf, size, "tx");
4771
4772         info->tbuf_start = i = info->tbuf_current;
4773
4774         while (size) {
4775                 d = &info->tbufs[i];
4776                 if (++i == info->tbuf_count)
4777                         i = 0;
4778
4779                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4780                 memcpy(d->buf, buf, count);
4781
4782                 size -= count;
4783                 buf  += count;
4784
4785                 /*
4786                  * set EOF bit for last buffer of HDLC frame or
4787                  * for every buffer in raw mode
4788                  */
4789                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4790                     info->params.mode == MGSL_MODE_RAW)
4791                         set_desc_eof(*d, 1);
4792                 else
4793                         set_desc_eof(*d, 0);
4794
4795                 set_desc_count(*d, count);
4796                 d->buf_count = count;
4797         }
4798
4799         info->tbuf_current = i;
4800 }
4801
4802 static int register_test(struct slgt_info *info)
4803 {
4804         static unsigned short patterns[] =
4805                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4806         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4807         unsigned int i;
4808         int rc = 0;
4809
4810         for (i=0 ; i < count ; i++) {
4811                 wr_reg16(info, TIR, patterns[i]);
4812                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4813                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4814                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4815                         rc = -ENODEV;
4816                         break;
4817                 }
4818         }
4819         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4820         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4821         return rc;
4822 }
4823
4824 static int irq_test(struct slgt_info *info)
4825 {
4826         unsigned long timeout;
4827         unsigned long flags;
4828         struct tty_struct *oldtty = info->port.tty;
4829         u32 speed = info->params.data_rate;
4830
4831         info->params.data_rate = 921600;
4832         info->port.tty = NULL;
4833
4834         spin_lock_irqsave(&info->lock, flags);
4835         async_mode(info);
4836         slgt_irq_on(info, IRQ_TXIDLE);
4837
4838         /* enable transmitter */
4839         wr_reg16(info, TCR,
4840                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4841
4842         /* write one byte and wait for tx idle */
4843         wr_reg16(info, TDR, 0);
4844
4845         /* assume failure */
4846         info->init_error = DiagStatus_IrqFailure;
4847         info->irq_occurred = false;
4848
4849         spin_unlock_irqrestore(&info->lock, flags);
4850
4851         timeout=100;
4852         while(timeout-- && !info->irq_occurred)
4853                 msleep_interruptible(10);
4854
4855         spin_lock_irqsave(&info->lock,flags);
4856         reset_port(info);
4857         spin_unlock_irqrestore(&info->lock,flags);
4858
4859         info->params.data_rate = speed;
4860         info->port.tty = oldtty;
4861
4862         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4863         return info->irq_occurred ? 0 : -ENODEV;
4864 }
4865
4866 static int loopback_test_rx(struct slgt_info *info)
4867 {
4868         unsigned char *src, *dest;
4869         int count;
4870
4871         if (desc_complete(info->rbufs[0])) {
4872                 count = desc_count(info->rbufs[0]);
4873                 src   = info->rbufs[0].buf;
4874                 dest  = info->tmp_rbuf;
4875
4876                 for( ; count ; count-=2, src+=2) {
4877                         /* src=data byte (src+1)=status byte */
4878                         if (!(*(src+1) & (BIT9 + BIT8))) {
4879                                 *dest = *src;
4880                                 dest++;
4881                                 info->tmp_rbuf_count++;
4882                         }
4883                 }
4884                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4885                 return 1;
4886         }
4887         return 0;
4888 }
4889
4890 static int loopback_test(struct slgt_info *info)
4891 {
4892 #define TESTFRAMESIZE 20
4893
4894         unsigned long timeout;
4895         u16 count = TESTFRAMESIZE;
4896         unsigned char buf[TESTFRAMESIZE];
4897         int rc = -ENODEV;
4898         unsigned long flags;
4899
4900         struct tty_struct *oldtty = info->port.tty;
4901         MGSL_PARAMS params;
4902
4903         memcpy(&params, &info->params, sizeof(params));
4904
4905         info->params.mode = MGSL_MODE_ASYNC;
4906         info->params.data_rate = 921600;
4907         info->params.loopback = 1;
4908         info->port.tty = NULL;
4909
4910         /* build and send transmit frame */
4911         for (count = 0; count < TESTFRAMESIZE; ++count)
4912                 buf[count] = (unsigned char)count;
4913
4914         info->tmp_rbuf_count = 0;
4915         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4916
4917         /* program hardware for HDLC and enabled receiver */
4918         spin_lock_irqsave(&info->lock,flags);
4919         async_mode(info);
4920         rx_start(info);
4921         info->tx_count = count;
4922         tx_load(info, buf, count);
4923         tx_start(info);
4924         spin_unlock_irqrestore(&info->lock, flags);
4925
4926         /* wait for receive complete */
4927         for (timeout = 100; timeout; --timeout) {
4928                 msleep_interruptible(10);
4929                 if (loopback_test_rx(info)) {
4930                         rc = 0;
4931                         break;
4932                 }
4933         }
4934
4935         /* verify received frame length and contents */
4936         if (!rc && (info->tmp_rbuf_count != count ||
4937                   memcmp(buf, info->tmp_rbuf, count))) {
4938                 rc = -ENODEV;
4939         }
4940
4941         spin_lock_irqsave(&info->lock,flags);
4942         reset_adapter(info);
4943         spin_unlock_irqrestore(&info->lock,flags);
4944
4945         memcpy(&info->params, &params, sizeof(info->params));
4946         info->port.tty = oldtty;
4947
4948         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4949         return rc;
4950 }
4951
4952 static int adapter_test(struct slgt_info *info)
4953 {
4954         DBGINFO(("testing %s\n", info->device_name));
4955         if (register_test(info) < 0) {
4956                 printk("register test failure %s addr=%08X\n",
4957                         info->device_name, info->phys_reg_addr);
4958         } else if (irq_test(info) < 0) {
4959                 printk("IRQ test failure %s IRQ=%d\n",
4960                         info->device_name, info->irq_level);
4961         } else if (loopback_test(info) < 0) {
4962                 printk("loopback test failure %s\n", info->device_name);
4963         }
4964         return info->init_error;
4965 }
4966
4967 /*
4968  * transmit timeout handler
4969  */
4970 static void tx_timeout(unsigned long context)
4971 {
4972         struct slgt_info *info = (struct slgt_info*)context;
4973         unsigned long flags;
4974
4975         DBGINFO(("%s tx_timeout\n", info->device_name));
4976         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4977                 info->icount.txtimeout++;
4978         }
4979         spin_lock_irqsave(&info->lock,flags);
4980         info->tx_active = false;
4981         info->tx_count = 0;
4982         spin_unlock_irqrestore(&info->lock,flags);
4983
4984 #if SYNCLINK_GENERIC_HDLC
4985         if (info->netcount)
4986                 hdlcdev_tx_done(info);
4987         else
4988 #endif
4989                 bh_transmit(info);
4990 }
4991
4992 /*
4993  * receive buffer polling timer
4994  */
4995 static void rx_timeout(unsigned long context)
4996 {
4997         struct slgt_info *info = (struct slgt_info*)context;
4998         unsigned long flags;
4999
5000         DBGINFO(("%s rx_timeout\n", info->device_name));
5001         spin_lock_irqsave(&info->lock, flags);
5002         info->pending_bh |= BH_RECEIVE;
5003         spin_unlock_irqrestore(&info->lock, flags);
5004         bh_handler(&info->task);
5005 }
5006