2 * Copyright (C) 2004 IBM Corporation
5 * Leendert van Doorn <leendert@watson.ibm.com>
6 * Dave Safford <safford@watson.ibm.com>
7 * Reiner Sailer <sailer@watson.ibm.com>
8 * Kylene Hall <kjhall@us.ibm.com>
10 * Maintained by: <tpmdd_devel@lists.sourceforge.net>
12 * Device driver for TCG/TCPA TPM (trusted platform module).
13 * Specifications at www.trustedcomputinggroup.org
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation, version 2 of the
24 /* National definitions */
40 enum tpm_nsc_status_loc {
48 NSC_STATUS_OBF = 0x01, /* output buffer full */
49 NSC_STATUS_IBF = 0x02, /* input buffer full */
50 NSC_STATUS_F0 = 0x04, /* F0 */
51 NSC_STATUS_A2 = 0x08, /* A2 */
52 NSC_STATUS_RDY = 0x10, /* ready to receive command */
53 NSC_STATUS_IBR = 0x20 /* ready to receive data */
56 enum tpm_nsc_cmd_mode {
57 NSC_COMMAND_NORMAL = 0x01, /* normal mode */
58 NSC_COMMAND_EOC = 0x03,
59 NSC_COMMAND_CANCEL = 0x22
62 * Wait for a certain status to appear
64 static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
68 /* status immediately available check */
69 *data = inb(chip->vendor->base + NSC_STATUS);
70 if ((*data & mask) == val)
74 stop = jiffies + 10 * HZ;
77 *data = inb(chip->vendor->base + 1);
78 if ((*data & mask) == val)
81 while (time_before(jiffies, stop));
86 static int nsc_wait_for_ready(struct tpm_chip *chip)
91 /* status immediately available check */
92 status = inb(chip->vendor->base + NSC_STATUS);
93 if (status & NSC_STATUS_OBF)
94 status = inb(chip->vendor->base + NSC_DATA);
95 if (status & NSC_STATUS_RDY)
102 status = inb(chip->vendor->base + NSC_STATUS);
103 if (status & NSC_STATUS_OBF)
104 status = inb(chip->vendor->base + NSC_DATA);
105 if (status & NSC_STATUS_RDY)
108 while (time_before(jiffies, stop));
110 dev_info(&chip->pci_dev->dev, "wait for ready failed\n");
115 static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
125 if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
126 dev_err(&chip->pci_dev->dev, "F0 timeout\n");
130 inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
131 dev_err(&chip->pci_dev->dev, "not in normal mode (0x%x)\n",
136 /* read the whole packet */
137 for (p = buffer; p < &buffer[count]; p++) {
139 (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
140 dev_err(&chip->pci_dev->dev,
141 "OBF timeout (while reading data)\n");
144 if (data & NSC_STATUS_F0)
146 *p = inb(chip->vendor->base + NSC_DATA);
149 if ((data & NSC_STATUS_F0) == 0) {
150 dev_err(&chip->pci_dev->dev, "F0 not set\n");
153 if ((data = inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_EOC) {
154 dev_err(&chip->pci_dev->dev,
155 "expected end of command(0x%x)\n", data);
159 native_size = (__force __be32 *) (buf + 2);
160 size = be32_to_cpu(*native_size);
168 static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
174 * If we hit the chip with back to back commands it locks up
175 * and never set IBF. Hitting it with this "hammer" seems to
176 * fix it. Not sure why this is needed, we followed the flow
177 * chart in the manual to the letter.
179 outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
181 if (nsc_wait_for_ready(chip) != 0)
184 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
185 dev_err(&chip->pci_dev->dev, "IBF timeout\n");
189 outb(NSC_COMMAND_NORMAL, chip->vendor->base + NSC_COMMAND);
190 if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
191 dev_err(&chip->pci_dev->dev, "IBR timeout\n");
195 for (i = 0; i < count; i++) {
196 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
197 dev_err(&chip->pci_dev->dev,
198 "IBF timeout (while writing data)\n");
201 outb(buf[i], chip->vendor->base + NSC_DATA);
204 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
205 dev_err(&chip->pci_dev->dev, "IBF timeout\n");
208 outb(NSC_COMMAND_EOC, chip->vendor->base + NSC_COMMAND);
213 static void tpm_nsc_cancel(struct tpm_chip *chip)
215 outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
218 static struct file_operations nsc_ops = {
219 .owner = THIS_MODULE,
224 .release = tpm_release,
227 static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
228 static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
229 static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL);
230 static DEVICE_ATTR(cancel, S_IWUSR|S_IWGRP, NULL, tpm_store_cancel);
232 static struct attribute * nsc_attrs[] = {
233 &dev_attr_pubek.attr,
236 &dev_attr_cancel.attr,
240 static struct attribute_group nsc_attr_grp = { .attrs = nsc_attrs };
242 static struct tpm_vendor_specific tpm_nsc = {
243 .recv = tpm_nsc_recv,
244 .send = tpm_nsc_send,
245 .cancel = tpm_nsc_cancel,
246 .req_complete_mask = NSC_STATUS_OBF,
247 .req_complete_val = NSC_STATUS_OBF,
248 .req_canceled = NSC_STATUS_RDY,
249 .base = TPM_NSC_BASE,
250 .attr_group = &nsc_attr_grp,
251 .miscdev = { .fops = &nsc_ops, },
254 static int __devinit tpm_nsc_init(struct pci_dev *pci_dev,
255 const struct pci_device_id *pci_id)
259 if (pci_enable_device(pci_dev))
262 if (tpm_lpc_bus_init(pci_dev, TPM_NSC_BASE)) {
267 /* verify that it is a National part (SID) */
268 if (tpm_read_index(NSC_SID_INDEX) != 0xEF) {
273 dev_dbg(&pci_dev->dev, "NSC TPM detected\n");
274 dev_dbg(&pci_dev->dev,
275 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
276 tpm_read_index(0x07), tpm_read_index(0x20),
277 tpm_read_index(0x27));
278 dev_dbg(&pci_dev->dev,
279 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
280 tpm_read_index(0x21), tpm_read_index(0x25),
281 tpm_read_index(0x26), tpm_read_index(0x28));
282 dev_dbg(&pci_dev->dev, "NSC IO Base0 0x%x\n",
283 (tpm_read_index(0x60) << 8) | tpm_read_index(0x61));
284 dev_dbg(&pci_dev->dev, "NSC IO Base1 0x%x\n",
285 (tpm_read_index(0x62) << 8) | tpm_read_index(0x63));
286 dev_dbg(&pci_dev->dev, "NSC Interrupt number and wakeup 0x%x\n",
287 tpm_read_index(0x70));
288 dev_dbg(&pci_dev->dev, "NSC IRQ type select 0x%x\n",
289 tpm_read_index(0x71));
290 dev_dbg(&pci_dev->dev,
291 "NSC DMA channel select0 0x%x, select1 0x%x\n",
292 tpm_read_index(0x74), tpm_read_index(0x75));
293 dev_dbg(&pci_dev->dev,
295 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
296 tpm_read_index(0xF0), tpm_read_index(0xF1),
297 tpm_read_index(0xF2), tpm_read_index(0xF3),
298 tpm_read_index(0xF4), tpm_read_index(0xF5),
299 tpm_read_index(0xF6), tpm_read_index(0xF7),
300 tpm_read_index(0xF8), tpm_read_index(0xF9));
302 dev_info(&pci_dev->dev,
303 "NSC PC21100 TPM revision %d\n",
304 tpm_read_index(0x27) & 0x1F);
306 if (tpm_read_index(NSC_LDC_INDEX) == 0)
307 dev_info(&pci_dev->dev, ": NSC TPM not active\n");
309 /* select PM channel 1 */
310 tpm_write_index(NSC_LDN_INDEX, 0x12);
311 tpm_read_index(NSC_LDN_INDEX);
313 /* disable the DPM module */
314 tpm_write_index(NSC_LDC_INDEX, 0);
315 tpm_read_index(NSC_LDC_INDEX);
317 /* set the data register base addresses */
318 tpm_write_index(NSC_DIO_INDEX, TPM_NSC_BASE >> 8);
319 tpm_write_index(NSC_DIO_INDEX + 1, TPM_NSC_BASE);
320 tpm_read_index(NSC_DIO_INDEX);
321 tpm_read_index(NSC_DIO_INDEX + 1);
323 /* set the command register base addresses */
324 tpm_write_index(NSC_CIO_INDEX, (TPM_NSC_BASE + 1) >> 8);
325 tpm_write_index(NSC_CIO_INDEX + 1, (TPM_NSC_BASE + 1));
326 tpm_read_index(NSC_DIO_INDEX);
327 tpm_read_index(NSC_DIO_INDEX + 1);
329 /* set the interrupt number to be used for the host interface */
330 tpm_write_index(NSC_IRQ_INDEX, TPM_NSC_IRQ);
331 tpm_write_index(NSC_ITS_INDEX, 0x00);
332 tpm_read_index(NSC_IRQ_INDEX);
334 /* enable the DPM module */
335 tpm_write_index(NSC_LDC_INDEX, 0x01);
336 tpm_read_index(NSC_LDC_INDEX);
338 if ((rc = tpm_register_hardware(pci_dev, &tpm_nsc)) < 0)
344 pci_disable_device(pci_dev);
348 static struct pci_device_id tpm_pci_tbl[] __devinitdata = {
349 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0)},
350 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12)},
351 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0)},
352 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12)},
353 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0)},
354 {PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_LPC)},
358 MODULE_DEVICE_TABLE(pci, tpm_pci_tbl);
360 static struct pci_driver nsc_pci_driver = {
362 .id_table = tpm_pci_tbl,
363 .probe = tpm_nsc_init,
364 .remove = __devexit_p(tpm_remove),
365 .suspend = tpm_pm_suspend,
366 .resume = tpm_pm_resume,
369 static int __init init_nsc(void)
371 return pci_register_driver(&nsc_pci_driver);
374 static void __exit cleanup_nsc(void)
376 pci_unregister_driver(&nsc_pci_driver);
379 module_init(init_nsc);
380 module_exit(cleanup_nsc);
382 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
383 MODULE_DESCRIPTION("TPM Driver");
384 MODULE_VERSION("2.0");
385 MODULE_LICENSE("GPL");