2 * Copyright (C) 2004 IBM Corporation
5 * Leendert van Doorn <leendert@watson.ibm.com>
6 * Dave Safford <safford@watson.ibm.com>
7 * Reiner Sailer <sailer@watson.ibm.com>
8 * Kylene Hall <kjhall@us.ibm.com>
10 * Maintained by: <tpmdd_devel@lists.sourceforge.net>
12 * Device driver for TCG/TCPA TPM (trusted platform module).
13 * Specifications at www.trustedcomputinggroup.org
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation, version 2 of the
24 /* National definitions */
28 TPM_NSC_BASE0_HI = 0x60,
29 TPM_NSC_BASE0_LO = 0x61,
30 TPM_NSC_BASE1_HI = 0x62,
31 TPM_NSC_BASE1_LO = 0x63
44 enum tpm_nsc_status_loc {
52 NSC_STATUS_OBF = 0x01, /* output buffer full */
53 NSC_STATUS_IBF = 0x02, /* input buffer full */
54 NSC_STATUS_F0 = 0x04, /* F0 */
55 NSC_STATUS_A2 = 0x08, /* A2 */
56 NSC_STATUS_RDY = 0x10, /* ready to receive command */
57 NSC_STATUS_IBR = 0x20 /* ready to receive data */
60 enum tpm_nsc_cmd_mode {
61 NSC_COMMAND_NORMAL = 0x01, /* normal mode */
62 NSC_COMMAND_EOC = 0x03,
63 NSC_COMMAND_CANCEL = 0x22
66 * Wait for a certain status to appear
68 static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
72 /* status immediately available check */
73 *data = inb(chip->vendor->base + NSC_STATUS);
74 if ((*data & mask) == val)
78 stop = jiffies + 10 * HZ;
81 *data = inb(chip->vendor->base + 1);
82 if ((*data & mask) == val)
85 while (time_before(jiffies, stop));
90 static int nsc_wait_for_ready(struct tpm_chip *chip)
95 /* status immediately available check */
96 status = inb(chip->vendor->base + NSC_STATUS);
97 if (status & NSC_STATUS_OBF)
98 status = inb(chip->vendor->base + NSC_DATA);
99 if (status & NSC_STATUS_RDY)
102 /* wait for status */
103 stop = jiffies + 100;
106 status = inb(chip->vendor->base + NSC_STATUS);
107 if (status & NSC_STATUS_OBF)
108 status = inb(chip->vendor->base + NSC_DATA);
109 if (status & NSC_STATUS_RDY)
112 while (time_before(jiffies, stop));
114 dev_info(&chip->pci_dev->dev, "wait for ready failed\n");
119 static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
129 if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
130 dev_err(&chip->pci_dev->dev, "F0 timeout\n");
134 inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
135 dev_err(&chip->pci_dev->dev, "not in normal mode (0x%x)\n",
140 /* read the whole packet */
141 for (p = buffer; p < &buffer[count]; p++) {
143 (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
144 dev_err(&chip->pci_dev->dev,
145 "OBF timeout (while reading data)\n");
148 if (data & NSC_STATUS_F0)
150 *p = inb(chip->vendor->base + NSC_DATA);
153 if ((data & NSC_STATUS_F0) == 0) {
154 dev_err(&chip->pci_dev->dev, "F0 not set\n");
157 if ((data = inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_EOC) {
158 dev_err(&chip->pci_dev->dev,
159 "expected end of command(0x%x)\n", data);
163 native_size = (__force __be32 *) (buf + 2);
164 size = be32_to_cpu(*native_size);
172 static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
178 * If we hit the chip with back to back commands it locks up
179 * and never set IBF. Hitting it with this "hammer" seems to
180 * fix it. Not sure why this is needed, we followed the flow
181 * chart in the manual to the letter.
183 outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
185 if (nsc_wait_for_ready(chip) != 0)
188 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
189 dev_err(&chip->pci_dev->dev, "IBF timeout\n");
193 outb(NSC_COMMAND_NORMAL, chip->vendor->base + NSC_COMMAND);
194 if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
195 dev_err(&chip->pci_dev->dev, "IBR timeout\n");
199 for (i = 0; i < count; i++) {
200 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
201 dev_err(&chip->pci_dev->dev,
202 "IBF timeout (while writing data)\n");
205 outb(buf[i], chip->vendor->base + NSC_DATA);
208 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
209 dev_err(&chip->pci_dev->dev, "IBF timeout\n");
212 outb(NSC_COMMAND_EOC, chip->vendor->base + NSC_COMMAND);
217 static void tpm_nsc_cancel(struct tpm_chip *chip)
219 outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
222 static struct file_operations nsc_ops = {
223 .owner = THIS_MODULE,
228 .release = tpm_release,
231 static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
232 static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
233 static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL);
234 static DEVICE_ATTR(cancel, S_IWUSR|S_IWGRP, NULL, tpm_store_cancel);
236 static struct attribute * nsc_attrs[] = {
237 &dev_attr_pubek.attr,
240 &dev_attr_cancel.attr,
244 static struct attribute_group nsc_attr_grp = { .attrs = nsc_attrs };
246 static struct tpm_vendor_specific tpm_nsc = {
247 .recv = tpm_nsc_recv,
248 .send = tpm_nsc_send,
249 .cancel = tpm_nsc_cancel,
250 .req_complete_mask = NSC_STATUS_OBF,
251 .req_complete_val = NSC_STATUS_OBF,
252 .req_canceled = NSC_STATUS_RDY,
253 .attr_group = &nsc_attr_grp,
254 .miscdev = { .fops = &nsc_ops, },
257 static int __devinit tpm_nsc_init(struct pci_dev *pci_dev,
258 const struct pci_device_id *pci_id)
263 hi = tpm_read_index(TPM_NSC_BASE0_HI);
264 lo = tpm_read_index(TPM_NSC_BASE0_LO);
266 tpm_nsc.base = (hi<<8) | lo;
268 if (pci_enable_device(pci_dev))
271 /* verify that it is a National part (SID) */
272 if (tpm_read_index(NSC_SID_INDEX) != 0xEF) {
277 dev_dbg(&pci_dev->dev, "NSC TPM detected\n");
278 dev_dbg(&pci_dev->dev,
279 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
280 tpm_read_index(0x07), tpm_read_index(0x20),
281 tpm_read_index(0x27));
282 dev_dbg(&pci_dev->dev,
283 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
284 tpm_read_index(0x21), tpm_read_index(0x25),
285 tpm_read_index(0x26), tpm_read_index(0x28));
286 dev_dbg(&pci_dev->dev, "NSC IO Base0 0x%x\n",
287 (tpm_read_index(0x60) << 8) | tpm_read_index(0x61));
288 dev_dbg(&pci_dev->dev, "NSC IO Base1 0x%x\n",
289 (tpm_read_index(0x62) << 8) | tpm_read_index(0x63));
290 dev_dbg(&pci_dev->dev, "NSC Interrupt number and wakeup 0x%x\n",
291 tpm_read_index(0x70));
292 dev_dbg(&pci_dev->dev, "NSC IRQ type select 0x%x\n",
293 tpm_read_index(0x71));
294 dev_dbg(&pci_dev->dev,
295 "NSC DMA channel select0 0x%x, select1 0x%x\n",
296 tpm_read_index(0x74), tpm_read_index(0x75));
297 dev_dbg(&pci_dev->dev,
299 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
300 tpm_read_index(0xF0), tpm_read_index(0xF1),
301 tpm_read_index(0xF2), tpm_read_index(0xF3),
302 tpm_read_index(0xF4), tpm_read_index(0xF5),
303 tpm_read_index(0xF6), tpm_read_index(0xF7),
304 tpm_read_index(0xF8), tpm_read_index(0xF9));
306 dev_info(&pci_dev->dev,
307 "NSC PC21100 TPM revision %d\n",
308 tpm_read_index(0x27) & 0x1F);
310 if (tpm_read_index(NSC_LDC_INDEX) == 0)
311 dev_info(&pci_dev->dev, ": NSC TPM not active\n");
313 /* select PM channel 1 */
314 tpm_write_index(NSC_LDN_INDEX, 0x12);
315 tpm_read_index(NSC_LDN_INDEX);
317 /* disable the DPM module */
318 tpm_write_index(NSC_LDC_INDEX, 0);
319 tpm_read_index(NSC_LDC_INDEX);
321 /* set the data register base addresses */
322 tpm_write_index(NSC_DIO_INDEX, TPM_NSC_BASE >> 8);
323 tpm_write_index(NSC_DIO_INDEX + 1, TPM_NSC_BASE);
324 tpm_read_index(NSC_DIO_INDEX);
325 tpm_read_index(NSC_DIO_INDEX + 1);
327 /* set the command register base addresses */
328 tpm_write_index(NSC_CIO_INDEX, (TPM_NSC_BASE + 1) >> 8);
329 tpm_write_index(NSC_CIO_INDEX + 1, (TPM_NSC_BASE + 1));
330 tpm_read_index(NSC_DIO_INDEX);
331 tpm_read_index(NSC_DIO_INDEX + 1);
333 /* set the interrupt number to be used for the host interface */
334 tpm_write_index(NSC_IRQ_INDEX, TPM_NSC_IRQ);
335 tpm_write_index(NSC_ITS_INDEX, 0x00);
336 tpm_read_index(NSC_IRQ_INDEX);
338 /* enable the DPM module */
339 tpm_write_index(NSC_LDC_INDEX, 0x01);
340 tpm_read_index(NSC_LDC_INDEX);
342 if ((rc = tpm_register_hardware(pci_dev, &tpm_nsc)) < 0)
348 pci_disable_device(pci_dev);
352 static struct pci_device_id tpm_pci_tbl[] __devinitdata = {
353 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0)},
354 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12)},
355 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0)},
356 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12)},
357 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0)},
358 {PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_LPC)},
362 MODULE_DEVICE_TABLE(pci, tpm_pci_tbl);
364 static struct pci_driver nsc_pci_driver = {
366 .id_table = tpm_pci_tbl,
367 .probe = tpm_nsc_init,
368 .remove = __devexit_p(tpm_remove),
369 .suspend = tpm_pm_suspend,
370 .resume = tpm_pm_resume,
373 static int __init init_nsc(void)
375 return pci_register_driver(&nsc_pci_driver);
378 static void __exit cleanup_nsc(void)
380 pci_unregister_driver(&nsc_pci_driver);
383 module_init(init_nsc);
384 module_exit(cleanup_nsc);
386 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
387 MODULE_DESCRIPTION("TPM Driver");
388 MODULE_VERSION("2.0");
389 MODULE_LICENSE("GPL");