2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/dmaengine.h>
25 #include "ioatdma_hw.h"
26 #include <linux/init.h>
27 #include <linux/dmapool.h>
28 #include <linux/cache.h>
29 #include <linux/pci_ids.h>
31 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0
34 * struct ioatdma_device - internal representation of a IOAT device
35 * @pdev: PCI-Express device
36 * @reg_base: MMIO register space base address
37 * @dma_pool: for allocating DMA descriptors
38 * @common: embedded struct dma_device
39 * @version: version of ioatdma device
42 struct ioatdma_device {
44 void __iomem *reg_base;
45 struct pci_pool *dma_pool;
46 struct pci_pool *completion_pool;
47 struct dma_device common;
52 * struct ioat_dma_chan - internal representation of a DMA channel
59 * @completed_cookie: last cookie seen completed on cleanup
60 * @cookie: value of last cookie given to client
70 struct ioat_dma_chan {
72 void __iomem *reg_base;
74 dma_cookie_t completed_cookie;
75 unsigned long last_completion;
77 u32 xfercap; /* XFERCAP register value expanded out */
79 spinlock_t cleanup_lock;
81 struct list_head free_desc;
82 struct list_head used_desc;
86 struct ioatdma_device *device;
87 struct dma_chan common;
89 dma_addr_t completion_addr;
91 u64 full; /* HW completion writeback */
99 /* wrapper around hardware descriptor format + additional software fields */
102 * struct ioat_desc_sw - wrapper around hardware descriptor
103 * @hw: hardware DMA descriptor
104 * @node: this descriptor will either be on the free list,
105 * or attached to a transaction list (async_tx.tx_list)
106 * @tx_cnt: number of descriptors required to complete the transaction
107 * @async_tx: the generic software descriptor for all engines
109 struct ioat_desc_sw {
110 struct ioat_dma_descriptor *hw;
111 struct list_head node;
113 DECLARE_PCI_UNMAP_LEN(len)
114 DECLARE_PCI_UNMAP_ADDR(src)
115 DECLARE_PCI_UNMAP_ADDR(dst)
116 struct dma_async_tx_descriptor async_tx;
119 #if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE)
120 struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
121 void __iomem *iobase);
122 void ioat_dma_remove(struct ioatdma_device *device);
124 #define ioat_dma_probe(pdev, iobase) NULL
125 #define ioat_dma_remove(device) do { } while (0)
128 #endif /* IOATDMA_H */