drivers/edac/r82600_edac.c

   1 /*
   2  * Radisys 82600 Embedded chipset Memory Controller kernel module
   3  * (C) 2005 EADS Astrium
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
   8  * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
   9  *
  10  * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
  11  *
  12  * Written with reference to 82600 High Integration Dual PCI System
  13  * Controller Data Book:
  14  * http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
  15  * references to this document given in []
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/pci_ids.h>
  22 #include <linux/slab.h>
  23 #include "edac_mc.h"
  24
  25 #define r82600_printk(level, fmt, arg...) \
  26         edac_printk(level, "r82600", fmt, ##arg)
  27
  28 #define r82600_mc_printk(mci, level, fmt, arg...) \
  29         edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
  30
  31 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
  32  * supports up to four banks of memory. The four banks can support a mix of
  33  * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
  34  * each of which can be any size from 16MB to 512MB. Both registered (control
  35  * signals buffered) and unbuffered DIMM types are supported. Mixing of
  36  * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
  37  * is not allowed. The 82600 SDRAM interface operates at the same frequency as
  38  * the CPU bus, 66MHz, 100MHz or 133MHz."
  39  */
  40
  41 #define R82600_NR_CSROWS 4
  42 #define R82600_NR_CHANS  1
  43 #define R82600_NR_DIMMS  4
  44
  45 #define R82600_BRIDGE_ID  0x8200
  46
  47 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
  48 #define R82600_DRAMC    0x57    /* Various SDRAM related control bits
  49                                  * all bits are R/W
  50                                  *
  51                                  * 7    SDRAM ISA Hole Enable
  52                                  * 6    Flash Page Mode Enable
  53                                  * 5    ECC Enable: 1=ECC 0=noECC
  54                                  * 4    DRAM DIMM Type: 1=
  55                                  * 3    BIOS Alias Disable
  56                                  * 2    SDRAM BIOS Flash Write Enable
  57                                  * 1:0  SDRAM Refresh Rate: 00=Disabled
  58                                  *          01=7.8usec (256Mbit SDRAMs)
  59                                  *          10=15.6us 11=125usec
  60                                  */
  61
  62 #define R82600_SDRAMC   0x76    /* "SDRAM Control Register"
  63                                  * More SDRAM related control bits
  64                                  * all bits are R/W
  65                                  *
  66                                  * 15:8 Reserved.
  67                                  *
  68                                  * 7:5  Special SDRAM Mode Select
  69                                  *
  70                                  * 4    Force ECC
  71                                  *
  72                                  *        1=Drive ECC bits to 0 during
  73                                  *          write cycles (i.e. ECC test mode)
  74                                  *
  75                                  *        0=Normal ECC functioning
  76                                  *
  77                                  * 3    Enhanced Paging Enable
  78                                  *
  79                                  * 2    CAS# Latency 0=3clks 1=2clks
  80                                  *
  81                                  * 1    RAS# to CAS# Delay 0=3 1=2
  82                                  *
  83                                  * 0    RAS# Precharge     0=3 1=2
  84                                  */
  85
  86 #define R82600_EAP      0x80    /* ECC Error Address Pointer Register
  87                                  *
  88                                  * 31    Disable Hardware Scrubbing (RW)
  89                                  *        0=Scrub on corrected read
  90                                  *        1=Don't scrub on corrected read
  91                                  *
  92                                  * 30:12 Error Address Pointer (RO)
  93                                  *        Upper 19 bits of error address
  94                                  *
  95                                  * 11:4  Syndrome Bits (RO)
  96                                  *
  97                                  * 3     BSERR# on multibit error (RW)
  98                                  *        1=enable 0=disable
  99                                  *
 100                                  * 2     NMI on Single Bit Eror (RW)
 101                                  *        1=NMI triggered by SBE n.b. other
 102                                  *          prerequeists
 103                                  *        0=NMI not triggered
 104                                  *
 105                                  * 1     MBE (R/WC)
 106                                  *        read 1=MBE at EAP (see above)
 107                                  *        read 0=no MBE, or SBE occurred first
 108                                  *        write 1=Clear MBE status (must also
 109                                  *          clear SBE)
 110                                  *        write 0=NOP
 111                                  *
 112                                  * 1     SBE (R/WC)
 113                                  *        read 1=SBE at EAP (see above)
 114                                  *        read 0=no SBE, or MBE occurred first
 115                                  *        write 1=Clear SBE status (must also
 116                                  *          clear MBE)
 117                                  *        write 0=NOP
 118                                  */
 119
 120 #define R82600_DRBA     0x60    /* + 0x60..0x63 SDRAM Row Boundry Address
 121                                  *  Registers
 122                                  *
 123                                  * 7:0  Address lines 30:24 - upper limit of
 124                                  * each row [p57]
 125                                  */
 126
 127 struct r82600_error_info {
 128         u32 eapr;
 129 };
 130
 131 static unsigned int disable_hardware_scrub = 0;
 132
 133 static void r82600_get_error_info (struct mem_ctl_info *mci,
 134                 struct r82600_error_info *info)
 135 {
 136         pci_read_config_dword(mci->pdev, R82600_EAP, &info->eapr);
 137
 138         if (info->eapr & BIT(0))
 139                 /* Clear error to allow next error to be reported [p.62] */
 140                 pci_write_bits32(mci->pdev, R82600_EAP,
 141                                 ((u32) BIT(0) & (u32) BIT(1)),
 142                                 ((u32) BIT(0) & (u32) BIT(1)));
 143
 144         if (info->eapr & BIT(1))
 145                 /* Clear error to allow next error to be reported [p.62] */
 146                 pci_write_bits32(mci->pdev, R82600_EAP,
 147                                 ((u32) BIT(0) & (u32) BIT(1)),
 148                                 ((u32) BIT(0) & (u32) BIT(1)));
 149 }
 150
 151 static int r82600_process_error_info (struct mem_ctl_info *mci,
 152                 struct r82600_error_info *info, int handle_errors)
 153 {
 154         int error_found;
 155         u32 eapaddr, page;
 156         u32 syndrome;
 157
 158         error_found = 0;
 159
 160         /* bits 30:12 store the upper 19 bits of the 32 bit error address */
 161         eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
 162         /* Syndrome in bits 11:4 [p.62]       */
 163         syndrome = (info->eapr >> 4) & 0xFF;
 164
 165         /* the R82600 reports at less than page *
 166          * granularity (upper 19 bits only)     */
 167         page = eapaddr >> PAGE_SHIFT;
 168
 169         if (info->eapr & BIT(0)) {  /* CE? */
 170                 error_found = 1;
 171
 172                 if (handle_errors)
 173                         edac_mc_handle_ce(mci, page, 0,  /* not avail */
 174                                         syndrome,
 175                                         edac_mc_find_csrow_by_page(mci, page),
 176                                         0,  /* channel */
 177                                         mci->ctl_name);
 178         }
 179
 180         if (info->eapr & BIT(1)) {  /* UE? */
 181                 error_found = 1;
 182
 183                 if (handle_errors)
 184                         /* 82600 doesn't give enough info */
 185                         edac_mc_handle_ue(mci, page, 0,
 186                                 edac_mc_find_csrow_by_page(mci, page),
 187                                 mci->ctl_name);
 188         }
 189
 190         return error_found;
 191 }
 192
 193 static void r82600_check(struct mem_ctl_info *mci)
 194 {
 195         struct r82600_error_info info;
 196
 197         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 198         r82600_get_error_info(mci, &info);
 199         r82600_process_error_info(mci, &info, 1);
 200 }
 201
 202 static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
 203 {
 204         int rc = -ENODEV;
 205         int index;
 206         struct mem_ctl_info *mci = NULL;
 207         u8 dramcr;
 208         u32 ecc_on;
 209         u32 reg_sdram;
 210         u32 eapr;
 211         u32 scrub_disabled;
 212         u32 sdram_refresh_rate;
 213         u32 row_high_limit_last = 0;
 214         struct r82600_error_info discard;
 215
 216         debugf0("%s()\n", __func__);
 217         pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
 218         pci_read_config_dword(pdev, R82600_EAP, &eapr);
 219         ecc_on = dramcr & BIT(5);
 220         reg_sdram = dramcr & BIT(4);
 221         scrub_disabled = eapr & BIT(31);
 222         sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
 223         debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
 224                 sdram_refresh_rate);
 225         debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
 226         mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS);
 227
 228         if (mci == NULL) {
 229                 rc = -ENOMEM;
 230                 goto fail;
 231         }
 232
 233         debugf0("%s(): mci = %p\n", __func__, mci);
 234         mci->pdev = pdev;
 235         mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
 236         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 237         /* FIXME try to work out if the chip leads have been used for COM2
 238          * instead on this board? [MA6?] MAYBE:
 239          */
 240
 241         /* On the R82600, the pins for memory bits 72:65 - i.e. the   *
 242          * EC bits are shared with the pins for COM2 (!), so if COM2  *
 243          * is enabled, we assume COM2 is wired up, and thus no EDAC   *
 244          * is possible.                                               */
 245         mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 246
 247         if (ecc_on) {
 248                 if (scrub_disabled)
 249                         debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
 250                                 "%#0x\n", __func__, mci, eapr);
 251         } else
 252                 mci->edac_cap = EDAC_FLAG_NONE;
 253
 254         mci->mod_name = EDAC_MOD_STR;
 255         mci->mod_ver = "$Revision: 1.1.2.6 $";
 256         mci->ctl_name = "R82600";
 257         mci->edac_check = r82600_check;
 258         mci->ctl_page_to_phys = NULL;
 259
 260         for (index = 0; index < mci->nr_csrows; index++) {
 261                 struct csrow_info *csrow = &mci->csrows[index];
 262                 u8 drbar;       /* sDram Row Boundry Address Register */
 263                 u32 row_high_limit;
 264                 u32 row_base;
 265
 266                 /* find the DRAM Chip Select Base address and mask */
 267                 pci_read_config_byte(mci->pdev, R82600_DRBA + index, &drbar);
 268
 269                 debugf1("MC%d: %s() Row=%d DRBA = %#0x\n", mci->mc_idx,
 270                         __func__, index, drbar);
 271
 272                 row_high_limit = ((u32) drbar << 24);
 273 /*              row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
 274
 275                 debugf1("MC%d: %s() Row=%d, Boundry Address=%#0x, Last = "
 276                         "%#0x \n", mci->mc_idx, __func__, index,
 277                         row_high_limit, row_high_limit_last);
 278
 279                 /* Empty row [p.57] */
 280                 if (row_high_limit == row_high_limit_last)
 281                         continue;
 282
 283                 row_base = row_high_limit_last;
 284                 csrow->first_page = row_base >> PAGE_SHIFT;
 285                 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
 286                 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
 287                 /* Error address is top 19 bits - so granularity is      *
 288                  * 14 bits                                               */
 289                 csrow->grain = 1 << 14;
 290                 csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
 291                 /* FIXME - check that this is unknowable with this chipset */
 292                 csrow->dtype = DEV_UNKNOWN;
 293
 294                 /* Mode is global on 82600 */
 295                 csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
 296                 row_high_limit_last = row_high_limit;
 297         }
 298
 299         r82600_get_error_info(mci, &discard);  /* clear counters */
 300
 301         if (edac_mc_add_mc(mci)) {
 302                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 303                 goto fail;
 304         }
 305
 306         /* get this far and it's successful */
 307
 308         if (disable_hardware_scrub) {
 309                 debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
 310                         __func__);
 311                 pci_write_bits32(mci->pdev, R82600_EAP, BIT(31), BIT(31));
 312         }
 313
 314         debugf3("%s(): success\n", __func__);
 315         return 0;
 316
 317 fail:
 318         if (mci)
 319                 edac_mc_free(mci);
 320
 321         return rc;
 322 }
 323
 324 /* returns count (>= 0), or negative on error */
 325 static int __devinit r82600_init_one(struct pci_dev *pdev,
 326                 const struct pci_device_id *ent)
 327 {
 328         debugf0("%s()\n", __func__);
 329
 330         /* don't need to call pci_device_enable() */
 331         return r82600_probe1(pdev, ent->driver_data);
 332 }
 333
 334 static void __devexit r82600_remove_one(struct pci_dev *pdev)
 335 {
 336         struct mem_ctl_info *mci;
 337
 338         debugf0("%s()\n", __func__);
 339
 340         if ((mci = edac_mc_del_mc(pdev)) == NULL)
 341                 return;
 342
 343         edac_mc_free(mci);
 344 }
 345
 346 static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
 347         {
 348                 PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
 349         },
 350         {
 351                 0,
 352         }       /* 0 terminated list. */
 353 };
 354
 355 MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
 356
 357 static struct pci_driver r82600_driver = {
 358         .name = EDAC_MOD_STR,
 359         .probe = r82600_init_one,
 360         .remove = __devexit_p(r82600_remove_one),
 361         .id_table = r82600_pci_tbl,
 362 };
 363
 364 static int __init r82600_init(void)
 365 {
 366         return pci_register_driver(&r82600_driver);
 367 }
 368
 369 static void __exit r82600_exit(void)
 370 {
 371         pci_unregister_driver(&r82600_driver);
 372 }
 373
 374 module_init(r82600_init);
 375 module_exit(r82600_exit);
 376
 377 MODULE_LICENSE("GPL");
 378 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
 379         "on behalf of EADS Astrium");
 380 MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
 381
 382 module_param(disable_hardware_scrub, bool, 0644);
 383 MODULE_PARM_DESC(disable_hardware_scrub,
 384                  "If set, disable the chipset's automatic scrub for CEs");