2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
35 #include <asm/system.h>
37 #ifdef CONFIG_PPC_PMAC
38 #include <asm/pmac_feature.h>
42 #include "fw-transaction.h"
44 #define DESCRIPTOR_OUTPUT_MORE 0
45 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
46 #define DESCRIPTOR_INPUT_MORE (2 << 12)
47 #define DESCRIPTOR_INPUT_LAST (3 << 12)
48 #define DESCRIPTOR_STATUS (1 << 11)
49 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
50 #define DESCRIPTOR_PING (1 << 7)
51 #define DESCRIPTOR_YY (1 << 6)
52 #define DESCRIPTOR_NO_IRQ (0 << 4)
53 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
54 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
55 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
56 #define DESCRIPTOR_WAIT (3 << 0)
62 __le32 branch_address;
64 __le16 transfer_status;
65 } __attribute__((aligned(16)));
67 struct db_descriptor {
70 __le16 second_req_count;
71 __le16 first_req_count;
72 __le32 branch_address;
73 __le16 second_res_count;
74 __le16 first_res_count;
79 } __attribute__((aligned(16)));
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
87 struct descriptor descriptor;
88 struct ar_buffer *next;
94 struct ar_buffer *current_buffer;
95 struct ar_buffer *last_buffer;
98 struct tasklet_struct tasklet;
103 typedef int (*descriptor_callback_t)(struct context *ctx,
104 struct descriptor *d,
105 struct descriptor *last);
108 * A buffer that contains a block of DMA-able coherent memory used for
109 * storing a portion of a DMA descriptor program.
111 struct descriptor_buffer {
112 struct list_head list;
113 dma_addr_t buffer_bus;
116 struct descriptor buffer[0];
120 struct fw_ohci *ohci;
122 int total_allocation;
125 * List of page-sized buffers for storing DMA descriptors.
126 * Head of list contains buffers in use and tail of list contains
129 struct list_head buffer_list;
132 * Pointer to a buffer inside buffer_list that contains the tail
133 * end of the current DMA program.
135 struct descriptor_buffer *buffer_tail;
138 * The descriptor containing the branch address of the first
139 * descriptor that has not yet been filled by the device.
141 struct descriptor *last;
144 * The last descriptor in the DMA program. It contains the branch
145 * address that must be updated upon appending a new descriptor.
147 struct descriptor *prev;
149 descriptor_callback_t callback;
151 struct tasklet_struct tasklet;
154 #define IT_HEADER_SY(v) ((v) << 0)
155 #define IT_HEADER_TCODE(v) ((v) << 4)
156 #define IT_HEADER_CHANNEL(v) ((v) << 8)
157 #define IT_HEADER_TAG(v) ((v) << 14)
158 #define IT_HEADER_SPEED(v) ((v) << 16)
159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
162 struct fw_iso_context base;
163 struct context context;
166 size_t header_length;
169 #define CONFIG_ROM_SIZE 1024
174 __iomem char *registers;
175 dma_addr_t self_id_bus;
177 struct tasklet_struct bus_reset_tasklet;
180 int request_generation; /* for timestamping incoming requests */
185 bool bus_reset_packet_quirk;
188 * Spinlock for accessing fw_ohci data. Never call out of
189 * this driver with this lock held.
192 u32 self_id_buffer[512];
194 /* Config rom buffers */
196 dma_addr_t config_rom_bus;
197 __be32 *next_config_rom;
198 dma_addr_t next_config_rom_bus;
201 struct ar_context ar_request_ctx;
202 struct ar_context ar_response_ctx;
203 struct context at_request_ctx;
204 struct context at_response_ctx;
207 struct iso_context *it_context_list;
208 u64 ir_context_channels;
210 struct iso_context *ir_context_list;
213 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
215 return container_of(card, struct fw_ohci, card);
218 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
219 #define IR_CONTEXT_BUFFER_FILL 0x80000000
220 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
221 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
222 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
223 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
225 #define CONTEXT_RUN 0x8000
226 #define CONTEXT_WAKE 0x1000
227 #define CONTEXT_DEAD 0x0800
228 #define CONTEXT_ACTIVE 0x0400
230 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
231 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
232 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
234 #define FW_OHCI_MAJOR 240
235 #define OHCI1394_REGISTER_SIZE 0x800
236 #define OHCI_LOOP_COUNT 500
237 #define OHCI1394_PCI_HCI_Control 0x40
238 #define SELF_ID_BUF_SIZE 0x800
239 #define OHCI_TCODE_PHY_PACKET 0x0e
240 #define OHCI_VERSION_1_1 0x010010
242 static char ohci_driver_name[] = KBUILD_MODNAME;
244 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
246 #define OHCI_PARAM_DEBUG_AT_AR 1
247 #define OHCI_PARAM_DEBUG_SELFIDS 2
248 #define OHCI_PARAM_DEBUG_IRQS 4
249 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
251 static int param_debug;
252 module_param_named(debug, param_debug, int, 0644);
253 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
254 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
255 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
256 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
257 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
258 ", or a combination, or all = -1)");
260 static void log_irqs(u32 evt)
262 if (likely(!(param_debug &
263 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
266 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
267 !(evt & OHCI1394_busReset))
270 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
271 evt & OHCI1394_selfIDComplete ? " selfID" : "",
272 evt & OHCI1394_RQPkt ? " AR_req" : "",
273 evt & OHCI1394_RSPkt ? " AR_resp" : "",
274 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
275 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
276 evt & OHCI1394_isochRx ? " IR" : "",
277 evt & OHCI1394_isochTx ? " IT" : "",
278 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
279 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
280 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
281 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
282 evt & OHCI1394_busReset ? " busReset" : "",
283 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
284 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
285 OHCI1394_respTxComplete | OHCI1394_isochRx |
286 OHCI1394_isochTx | OHCI1394_postedWriteErr |
287 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
288 OHCI1394_regAccessFail | OHCI1394_busReset)
292 static const char *speed[] = {
293 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
295 static const char *power[] = {
296 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
297 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
299 static const char port[] = { '.', '-', 'p', 'c', };
301 static char _p(u32 *s, int shift)
303 return port[*s >> shift & 3];
306 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
308 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
311 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
312 self_id_count, generation, node_id);
314 for (; self_id_count--; ++s)
315 if ((*s & 1 << 23) == 0)
316 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
317 "%s gc=%d %s %s%s%s\n",
318 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
319 speed[*s >> 14 & 3], *s >> 16 & 63,
320 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
321 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
323 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
325 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
326 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
329 static const char *evts[] = {
330 [0x00] = "evt_no_status", [0x01] = "-reserved-",
331 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
332 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
333 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
334 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
335 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
336 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
337 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
338 [0x10] = "-reserved-", [0x11] = "ack_complete",
339 [0x12] = "ack_pending ", [0x13] = "-reserved-",
340 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
341 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
342 [0x18] = "-reserved-", [0x19] = "-reserved-",
343 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
344 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
345 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
346 [0x20] = "pending/cancelled",
348 static const char *tcodes[] = {
349 [0x0] = "QW req", [0x1] = "BW req",
350 [0x2] = "W resp", [0x3] = "-reserved-",
351 [0x4] = "QR req", [0x5] = "BR req",
352 [0x6] = "QR resp", [0x7] = "BR resp",
353 [0x8] = "cycle start", [0x9] = "Lk req",
354 [0xa] = "async stream packet", [0xb] = "Lk resp",
355 [0xc] = "-reserved-", [0xd] = "-reserved-",
356 [0xe] = "link internal", [0xf] = "-reserved-",
358 static const char *phys[] = {
359 [0x0] = "phy config packet", [0x1] = "link-on packet",
360 [0x2] = "self-id packet", [0x3] = "-reserved-",
363 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
365 int tcode = header[0] >> 4 & 0xf;
368 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
371 if (unlikely(evt >= ARRAY_SIZE(evts)))
374 if (evt == OHCI1394_evt_bus_reset) {
375 fw_notify("A%c evt_bus_reset, generation %d\n",
376 dir, (header[2] >> 16) & 0xff);
380 if (header[0] == ~header[1]) {
381 fw_notify("A%c %s, %s, %08x\n",
382 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
387 case 0x0: case 0x6: case 0x8:
388 snprintf(specific, sizeof(specific), " = %08x",
389 be32_to_cpu((__force __be32)header[3]));
391 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
392 snprintf(specific, sizeof(specific), " %x,%x",
393 header[3] >> 16, header[3] & 0xffff);
401 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
403 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
404 fw_notify("A%c spd %x tl %02x, "
407 dir, speed, header[0] >> 10 & 0x3f,
408 header[1] >> 16, header[0] >> 16, evts[evt],
409 tcodes[tcode], header[1] & 0xffff, header[2], specific);
412 fw_notify("A%c spd %x tl %02x, "
415 dir, speed, header[0] >> 10 & 0x3f,
416 header[1] >> 16, header[0] >> 16, evts[evt],
417 tcodes[tcode], specific);
423 #define log_irqs(evt)
424 #define log_selfids(node_id, generation, self_id_count, sid)
425 #define log_ar_at_event(dir, speed, header, evt)
427 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
429 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
431 writel(data, ohci->registers + offset);
434 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
436 return readl(ohci->registers + offset);
439 static inline void flush_writes(const struct fw_ohci *ohci)
441 /* Do a dummy read to flush writes. */
442 reg_read(ohci, OHCI1394_Version);
445 static int ohci_update_phy_reg(struct fw_card *card, int addr,
446 int clear_bits, int set_bits)
448 struct fw_ohci *ohci = fw_ohci(card);
451 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
454 val = reg_read(ohci, OHCI1394_PhyControl);
455 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
456 fw_error("failed to set phy reg bits.\n");
460 old = OHCI1394_PhyControl_ReadData(val);
461 old = (old & ~clear_bits) | set_bits;
462 reg_write(ohci, OHCI1394_PhyControl,
463 OHCI1394_PhyControl_Write(addr, old));
468 static int ar_context_add_page(struct ar_context *ctx)
470 struct device *dev = ctx->ohci->card.device;
471 struct ar_buffer *ab;
472 dma_addr_t uninitialized_var(ab_bus);
475 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
480 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
481 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
483 DESCRIPTOR_BRANCH_ALWAYS);
484 offset = offsetof(struct ar_buffer, data);
485 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
486 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
487 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
488 ab->descriptor.branch_address = 0;
490 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
491 ctx->last_buffer->next = ab;
492 ctx->last_buffer = ab;
494 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
495 flush_writes(ctx->ohci);
500 static void ar_context_release(struct ar_context *ctx)
502 struct ar_buffer *ab, *ab_next;
506 for (ab = ctx->current_buffer; ab; ab = ab_next) {
508 offset = offsetof(struct ar_buffer, data);
509 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
510 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
515 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
516 #define cond_le32_to_cpu(v) \
517 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
519 #define cond_le32_to_cpu(v) le32_to_cpu(v)
522 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
524 struct fw_ohci *ohci = ctx->ohci;
526 u32 status, length, tcode;
529 p.header[0] = cond_le32_to_cpu(buffer[0]);
530 p.header[1] = cond_le32_to_cpu(buffer[1]);
531 p.header[2] = cond_le32_to_cpu(buffer[2]);
533 tcode = (p.header[0] >> 4) & 0x0f;
535 case TCODE_WRITE_QUADLET_REQUEST:
536 case TCODE_READ_QUADLET_RESPONSE:
537 p.header[3] = (__force __u32) buffer[3];
538 p.header_length = 16;
539 p.payload_length = 0;
542 case TCODE_READ_BLOCK_REQUEST :
543 p.header[3] = cond_le32_to_cpu(buffer[3]);
544 p.header_length = 16;
545 p.payload_length = 0;
548 case TCODE_WRITE_BLOCK_REQUEST:
549 case TCODE_READ_BLOCK_RESPONSE:
550 case TCODE_LOCK_REQUEST:
551 case TCODE_LOCK_RESPONSE:
552 p.header[3] = cond_le32_to_cpu(buffer[3]);
553 p.header_length = 16;
554 p.payload_length = p.header[3] >> 16;
557 case TCODE_WRITE_RESPONSE:
558 case TCODE_READ_QUADLET_REQUEST:
559 case OHCI_TCODE_PHY_PACKET:
560 p.header_length = 12;
561 p.payload_length = 0;
565 /* FIXME: Stop context, discard everything, and restart? */
567 p.payload_length = 0;
570 p.payload = (void *) buffer + p.header_length;
572 /* FIXME: What to do about evt_* errors? */
573 length = (p.header_length + p.payload_length + 3) / 4;
574 status = cond_le32_to_cpu(buffer[length]);
575 evt = (status >> 16) & 0x1f;
578 p.speed = (status >> 21) & 0x7;
579 p.timestamp = status & 0xffff;
580 p.generation = ohci->request_generation;
582 log_ar_at_event('R', p.speed, p.header, evt);
585 * The OHCI bus reset handler synthesizes a phy packet with
586 * the new generation number when a bus reset happens (see
587 * section 8.4.2.3). This helps us determine when a request
588 * was received and make sure we send the response in the same
589 * generation. We only need this for requests; for responses
590 * we use the unique tlabel for finding the matching
593 * Alas some chips sometimes emit bus reset packets with a
594 * wrong generation. We set the correct generation for these
595 * at a slightly incorrect time (in bus_reset_tasklet).
597 if (evt == OHCI1394_evt_bus_reset) {
598 if (!ohci->bus_reset_packet_quirk)
599 ohci->request_generation = (p.header[2] >> 16) & 0xff;
600 } else if (ctx == &ohci->ar_request_ctx) {
601 fw_core_handle_request(&ohci->card, &p);
603 fw_core_handle_response(&ohci->card, &p);
606 return buffer + length + 1;
609 static void ar_context_tasklet(unsigned long data)
611 struct ar_context *ctx = (struct ar_context *)data;
612 struct fw_ohci *ohci = ctx->ohci;
613 struct ar_buffer *ab;
614 struct descriptor *d;
617 ab = ctx->current_buffer;
620 if (d->res_count == 0) {
621 size_t size, rest, offset;
622 dma_addr_t start_bus;
626 * This descriptor is finished and we may have a
627 * packet split across this and the next buffer. We
628 * reuse the page for reassembling the split packet.
631 offset = offsetof(struct ar_buffer, data);
633 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
637 size = buffer + PAGE_SIZE - ctx->pointer;
638 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
639 memmove(buffer, ctx->pointer, size);
640 memcpy(buffer + size, ab->data, rest);
641 ctx->current_buffer = ab;
642 ctx->pointer = (void *) ab->data + rest;
643 end = buffer + size + rest;
646 buffer = handle_ar_packet(ctx, buffer);
648 dma_free_coherent(ohci->card.device, PAGE_SIZE,
650 ar_context_add_page(ctx);
652 buffer = ctx->pointer;
654 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
657 buffer = handle_ar_packet(ctx, buffer);
661 static int ar_context_init(struct ar_context *ctx,
662 struct fw_ohci *ohci, u32 regs)
668 ctx->last_buffer = &ab;
669 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
671 ar_context_add_page(ctx);
672 ar_context_add_page(ctx);
673 ctx->current_buffer = ab.next;
674 ctx->pointer = ctx->current_buffer->data;
679 static void ar_context_run(struct ar_context *ctx)
681 struct ar_buffer *ab = ctx->current_buffer;
685 offset = offsetof(struct ar_buffer, data);
686 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
688 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
689 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
690 flush_writes(ctx->ohci);
693 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
697 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
698 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
700 /* figure out which descriptor the branch address goes in */
701 if (z == 2 && (b == 3 || key == 2))
707 static void context_tasklet(unsigned long data)
709 struct context *ctx = (struct context *) data;
710 struct descriptor *d, *last;
713 struct descriptor_buffer *desc;
715 desc = list_entry(ctx->buffer_list.next,
716 struct descriptor_buffer, list);
718 while (last->branch_address != 0) {
719 struct descriptor_buffer *old_desc = desc;
720 address = le32_to_cpu(last->branch_address);
724 /* If the branch address points to a buffer outside of the
725 * current buffer, advance to the next buffer. */
726 if (address < desc->buffer_bus ||
727 address >= desc->buffer_bus + desc->used)
728 desc = list_entry(desc->list.next,
729 struct descriptor_buffer, list);
730 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
731 last = find_branch_descriptor(d, z);
733 if (!ctx->callback(ctx, d, last))
736 if (old_desc != desc) {
737 /* If we've advanced to the next buffer, move the
738 * previous buffer to the free list. */
741 spin_lock_irqsave(&ctx->ohci->lock, flags);
742 list_move_tail(&old_desc->list, &ctx->buffer_list);
743 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
750 * Allocate a new buffer and add it to the list of free buffers for this
751 * context. Must be called with ohci->lock held.
753 static int context_add_buffer(struct context *ctx)
755 struct descriptor_buffer *desc;
756 dma_addr_t uninitialized_var(bus_addr);
760 * 16MB of descriptors should be far more than enough for any DMA
761 * program. This will catch run-away userspace or DoS attacks.
763 if (ctx->total_allocation >= 16*1024*1024)
766 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
767 &bus_addr, GFP_ATOMIC);
771 offset = (void *)&desc->buffer - (void *)desc;
772 desc->buffer_size = PAGE_SIZE - offset;
773 desc->buffer_bus = bus_addr + offset;
776 list_add_tail(&desc->list, &ctx->buffer_list);
777 ctx->total_allocation += PAGE_SIZE;
782 static int context_init(struct context *ctx, struct fw_ohci *ohci,
783 u32 regs, descriptor_callback_t callback)
787 ctx->total_allocation = 0;
789 INIT_LIST_HEAD(&ctx->buffer_list);
790 if (context_add_buffer(ctx) < 0)
793 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
794 struct descriptor_buffer, list);
796 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
797 ctx->callback = callback;
800 * We put a dummy descriptor in the buffer that has a NULL
801 * branch address and looks like it's been sent. That way we
802 * have a descriptor to append DMA programs to.
804 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
805 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
806 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
807 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
808 ctx->last = ctx->buffer_tail->buffer;
809 ctx->prev = ctx->buffer_tail->buffer;
814 static void context_release(struct context *ctx)
816 struct fw_card *card = &ctx->ohci->card;
817 struct descriptor_buffer *desc, *tmp;
819 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
820 dma_free_coherent(card->device, PAGE_SIZE, desc,
822 ((void *)&desc->buffer - (void *)desc));
825 /* Must be called with ohci->lock held */
826 static struct descriptor *context_get_descriptors(struct context *ctx,
827 int z, dma_addr_t *d_bus)
829 struct descriptor *d = NULL;
830 struct descriptor_buffer *desc = ctx->buffer_tail;
832 if (z * sizeof(*d) > desc->buffer_size)
835 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
836 /* No room for the descriptor in this buffer, so advance to the
839 if (desc->list.next == &ctx->buffer_list) {
840 /* If there is no free buffer next in the list,
842 if (context_add_buffer(ctx) < 0)
845 desc = list_entry(desc->list.next,
846 struct descriptor_buffer, list);
847 ctx->buffer_tail = desc;
850 d = desc->buffer + desc->used / sizeof(*d);
851 memset(d, 0, z * sizeof(*d));
852 *d_bus = desc->buffer_bus + desc->used;
857 static void context_run(struct context *ctx, u32 extra)
859 struct fw_ohci *ohci = ctx->ohci;
861 reg_write(ohci, COMMAND_PTR(ctx->regs),
862 le32_to_cpu(ctx->last->branch_address));
863 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
864 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
868 static void context_append(struct context *ctx,
869 struct descriptor *d, int z, int extra)
872 struct descriptor_buffer *desc = ctx->buffer_tail;
874 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
876 desc->used += (z + extra) * sizeof(*d);
877 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
878 ctx->prev = find_branch_descriptor(d, z);
880 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
881 flush_writes(ctx->ohci);
884 static void context_stop(struct context *ctx)
889 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
890 flush_writes(ctx->ohci);
892 for (i = 0; i < 10; i++) {
893 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
894 if ((reg & CONTEXT_ACTIVE) == 0)
899 fw_error("Error: DMA context still active (0x%08x)\n", reg);
903 struct fw_packet *packet;
907 * This function apppends a packet to the DMA queue for transmission.
908 * Must always be called with the ochi->lock held to ensure proper
909 * generation handling and locking around packet queue manipulation.
911 static int at_context_queue_packet(struct context *ctx,
912 struct fw_packet *packet)
914 struct fw_ohci *ohci = ctx->ohci;
915 dma_addr_t d_bus, uninitialized_var(payload_bus);
916 struct driver_data *driver_data;
917 struct descriptor *d, *last;
922 d = context_get_descriptors(ctx, 4, &d_bus);
924 packet->ack = RCODE_SEND_ERROR;
928 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
929 d[0].res_count = cpu_to_le16(packet->timestamp);
932 * The DMA format for asyncronous link packets is different
933 * from the IEEE1394 layout, so shift the fields around
934 * accordingly. If header_length is 8, it's a PHY packet, to
935 * which we need to prepend an extra quadlet.
938 header = (__le32 *) &d[1];
939 if (packet->header_length > 8) {
940 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
941 (packet->speed << 16));
942 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
943 (packet->header[0] & 0xffff0000));
944 header[2] = cpu_to_le32(packet->header[2]);
946 tcode = (packet->header[0] >> 4) & 0x0f;
947 if (TCODE_IS_BLOCK_PACKET(tcode))
948 header[3] = cpu_to_le32(packet->header[3]);
950 header[3] = (__force __le32) packet->header[3];
952 d[0].req_count = cpu_to_le16(packet->header_length);
954 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
955 (packet->speed << 16));
956 header[1] = cpu_to_le32(packet->header[0]);
957 header[2] = cpu_to_le32(packet->header[1]);
958 d[0].req_count = cpu_to_le16(12);
961 driver_data = (struct driver_data *) &d[3];
962 driver_data->packet = packet;
963 packet->driver_data = driver_data;
965 if (packet->payload_length > 0) {
967 dma_map_single(ohci->card.device, packet->payload,
968 packet->payload_length, DMA_TO_DEVICE);
969 if (dma_mapping_error(ohci->card.device, payload_bus)) {
970 packet->ack = RCODE_SEND_ERROR;
973 packet->payload_bus = payload_bus;
975 d[2].req_count = cpu_to_le16(packet->payload_length);
976 d[2].data_address = cpu_to_le32(payload_bus);
984 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
985 DESCRIPTOR_IRQ_ALWAYS |
986 DESCRIPTOR_BRANCH_ALWAYS);
989 * If the controller and packet generations don't match, we need to
990 * bail out and try again. If IntEvent.busReset is set, the AT context
991 * is halted, so appending to the context and trying to run it is
992 * futile. Most controllers do the right thing and just flush the AT
993 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
994 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
995 * up stalling out. So we just bail out in software and try again
996 * later, and everyone is happy.
997 * FIXME: Document how the locking works.
999 if (ohci->generation != packet->generation ||
1000 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1001 if (packet->payload_length > 0)
1002 dma_unmap_single(ohci->card.device, payload_bus,
1003 packet->payload_length, DMA_TO_DEVICE);
1004 packet->ack = RCODE_GENERATION;
1008 context_append(ctx, d, z, 4 - z);
1010 /* If the context isn't already running, start it up. */
1011 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1012 if ((reg & CONTEXT_RUN) == 0)
1013 context_run(ctx, 0);
1018 static int handle_at_packet(struct context *context,
1019 struct descriptor *d,
1020 struct descriptor *last)
1022 struct driver_data *driver_data;
1023 struct fw_packet *packet;
1024 struct fw_ohci *ohci = context->ohci;
1027 if (last->transfer_status == 0)
1028 /* This descriptor isn't done yet, stop iteration. */
1031 driver_data = (struct driver_data *) &d[3];
1032 packet = driver_data->packet;
1034 /* This packet was cancelled, just continue. */
1037 if (packet->payload_bus)
1038 dma_unmap_single(ohci->card.device, packet->payload_bus,
1039 packet->payload_length, DMA_TO_DEVICE);
1041 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1042 packet->timestamp = le16_to_cpu(last->res_count);
1044 log_ar_at_event('T', packet->speed, packet->header, evt);
1047 case OHCI1394_evt_timeout:
1048 /* Async response transmit timed out. */
1049 packet->ack = RCODE_CANCELLED;
1052 case OHCI1394_evt_flushed:
1054 * The packet was flushed should give same error as
1055 * when we try to use a stale generation count.
1057 packet->ack = RCODE_GENERATION;
1060 case OHCI1394_evt_missing_ack:
1062 * Using a valid (current) generation count, but the
1063 * node is not on the bus or not sending acks.
1065 packet->ack = RCODE_NO_ACK;
1068 case ACK_COMPLETE + 0x10:
1069 case ACK_PENDING + 0x10:
1070 case ACK_BUSY_X + 0x10:
1071 case ACK_BUSY_A + 0x10:
1072 case ACK_BUSY_B + 0x10:
1073 case ACK_DATA_ERROR + 0x10:
1074 case ACK_TYPE_ERROR + 0x10:
1075 packet->ack = evt - 0x10;
1079 packet->ack = RCODE_SEND_ERROR;
1083 packet->callback(packet, &ohci->card, packet->ack);
1088 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1089 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1090 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1091 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1092 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1094 static void handle_local_rom(struct fw_ohci *ohci,
1095 struct fw_packet *packet, u32 csr)
1097 struct fw_packet response;
1098 int tcode, length, i;
1100 tcode = HEADER_GET_TCODE(packet->header[0]);
1101 if (TCODE_IS_BLOCK_PACKET(tcode))
1102 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1106 i = csr - CSR_CONFIG_ROM;
1107 if (i + length > CONFIG_ROM_SIZE) {
1108 fw_fill_response(&response, packet->header,
1109 RCODE_ADDRESS_ERROR, NULL, 0);
1110 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1111 fw_fill_response(&response, packet->header,
1112 RCODE_TYPE_ERROR, NULL, 0);
1114 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1115 (void *) ohci->config_rom + i, length);
1118 fw_core_handle_response(&ohci->card, &response);
1121 static void handle_local_lock(struct fw_ohci *ohci,
1122 struct fw_packet *packet, u32 csr)
1124 struct fw_packet response;
1125 int tcode, length, ext_tcode, sel;
1126 __be32 *payload, lock_old;
1127 u32 lock_arg, lock_data;
1129 tcode = HEADER_GET_TCODE(packet->header[0]);
1130 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1131 payload = packet->payload;
1132 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1134 if (tcode == TCODE_LOCK_REQUEST &&
1135 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1136 lock_arg = be32_to_cpu(payload[0]);
1137 lock_data = be32_to_cpu(payload[1]);
1138 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1142 fw_fill_response(&response, packet->header,
1143 RCODE_TYPE_ERROR, NULL, 0);
1147 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1148 reg_write(ohci, OHCI1394_CSRData, lock_data);
1149 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1150 reg_write(ohci, OHCI1394_CSRControl, sel);
1152 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1153 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1155 fw_notify("swap not done yet\n");
1157 fw_fill_response(&response, packet->header,
1158 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1160 fw_core_handle_response(&ohci->card, &response);
1163 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1168 if (ctx == &ctx->ohci->at_request_ctx) {
1169 packet->ack = ACK_PENDING;
1170 packet->callback(packet, &ctx->ohci->card, packet->ack);
1174 ((unsigned long long)
1175 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1177 csr = offset - CSR_REGISTER_BASE;
1179 /* Handle config rom reads. */
1180 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1181 handle_local_rom(ctx->ohci, packet, csr);
1183 case CSR_BUS_MANAGER_ID:
1184 case CSR_BANDWIDTH_AVAILABLE:
1185 case CSR_CHANNELS_AVAILABLE_HI:
1186 case CSR_CHANNELS_AVAILABLE_LO:
1187 handle_local_lock(ctx->ohci, packet, csr);
1190 if (ctx == &ctx->ohci->at_request_ctx)
1191 fw_core_handle_request(&ctx->ohci->card, packet);
1193 fw_core_handle_response(&ctx->ohci->card, packet);
1197 if (ctx == &ctx->ohci->at_response_ctx) {
1198 packet->ack = ACK_COMPLETE;
1199 packet->callback(packet, &ctx->ohci->card, packet->ack);
1203 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1205 unsigned long flags;
1208 spin_lock_irqsave(&ctx->ohci->lock, flags);
1210 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1211 ctx->ohci->generation == packet->generation) {
1212 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1213 handle_local_request(ctx, packet);
1217 ret = at_context_queue_packet(ctx, packet);
1218 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1221 packet->callback(packet, &ctx->ohci->card, packet->ack);
1225 static void bus_reset_tasklet(unsigned long data)
1227 struct fw_ohci *ohci = (struct fw_ohci *)data;
1228 int self_id_count, i, j, reg;
1229 int generation, new_generation;
1230 unsigned long flags;
1231 void *free_rom = NULL;
1232 dma_addr_t free_rom_bus = 0;
1234 reg = reg_read(ohci, OHCI1394_NodeID);
1235 if (!(reg & OHCI1394_NodeID_idValid)) {
1236 fw_notify("node ID not valid, new bus reset in progress\n");
1239 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1240 fw_notify("malconfigured bus\n");
1243 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1244 OHCI1394_NodeID_nodeNumber);
1246 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1247 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1248 fw_notify("inconsistent self IDs\n");
1252 * The count in the SelfIDCount register is the number of
1253 * bytes in the self ID receive buffer. Since we also receive
1254 * the inverted quadlets and a header quadlet, we shift one
1255 * bit extra to get the actual number of self IDs.
1257 self_id_count = (reg >> 3) & 0x3ff;
1258 if (self_id_count == 0) {
1259 fw_notify("inconsistent self IDs\n");
1262 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1265 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1266 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1267 fw_notify("inconsistent self IDs\n");
1270 ohci->self_id_buffer[j] =
1271 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1276 * Check the consistency of the self IDs we just read. The
1277 * problem we face is that a new bus reset can start while we
1278 * read out the self IDs from the DMA buffer. If this happens,
1279 * the DMA buffer will be overwritten with new self IDs and we
1280 * will read out inconsistent data. The OHCI specification
1281 * (section 11.2) recommends a technique similar to
1282 * linux/seqlock.h, where we remember the generation of the
1283 * self IDs in the buffer before reading them out and compare
1284 * it to the current generation after reading them out. If
1285 * the two generations match we know we have a consistent set
1289 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1290 if (new_generation != generation) {
1291 fw_notify("recursive bus reset detected, "
1292 "discarding self ids\n");
1296 /* FIXME: Document how the locking works. */
1297 spin_lock_irqsave(&ohci->lock, flags);
1299 ohci->generation = generation;
1300 context_stop(&ohci->at_request_ctx);
1301 context_stop(&ohci->at_response_ctx);
1302 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1304 if (ohci->bus_reset_packet_quirk)
1305 ohci->request_generation = generation;
1308 * This next bit is unrelated to the AT context stuff but we
1309 * have to do it under the spinlock also. If a new config rom
1310 * was set up before this reset, the old one is now no longer
1311 * in use and we can free it. Update the config rom pointers
1312 * to point to the current config rom and clear the
1313 * next_config_rom pointer so a new udpate can take place.
1316 if (ohci->next_config_rom != NULL) {
1317 if (ohci->next_config_rom != ohci->config_rom) {
1318 free_rom = ohci->config_rom;
1319 free_rom_bus = ohci->config_rom_bus;
1321 ohci->config_rom = ohci->next_config_rom;
1322 ohci->config_rom_bus = ohci->next_config_rom_bus;
1323 ohci->next_config_rom = NULL;
1326 * Restore config_rom image and manually update
1327 * config_rom registers. Writing the header quadlet
1328 * will indicate that the config rom is ready, so we
1331 reg_write(ohci, OHCI1394_BusOptions,
1332 be32_to_cpu(ohci->config_rom[2]));
1333 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1334 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1337 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1338 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1339 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1342 spin_unlock_irqrestore(&ohci->lock, flags);
1345 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1346 free_rom, free_rom_bus);
1348 log_selfids(ohci->node_id, generation,
1349 self_id_count, ohci->self_id_buffer);
1351 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1352 self_id_count, ohci->self_id_buffer);
1355 static irqreturn_t irq_handler(int irq, void *data)
1357 struct fw_ohci *ohci = data;
1358 u32 event, iso_event, cycle_time;
1361 event = reg_read(ohci, OHCI1394_IntEventClear);
1363 if (!event || !~event)
1366 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1367 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1370 if (event & OHCI1394_selfIDComplete)
1371 tasklet_schedule(&ohci->bus_reset_tasklet);
1373 if (event & OHCI1394_RQPkt)
1374 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1376 if (event & OHCI1394_RSPkt)
1377 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1379 if (event & OHCI1394_reqTxComplete)
1380 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1382 if (event & OHCI1394_respTxComplete)
1383 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1385 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1386 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1389 i = ffs(iso_event) - 1;
1390 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1391 iso_event &= ~(1 << i);
1394 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1395 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1398 i = ffs(iso_event) - 1;
1399 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1400 iso_event &= ~(1 << i);
1403 if (unlikely(event & OHCI1394_regAccessFail))
1404 fw_error("Register access failure - "
1405 "please notify linux1394-devel@lists.sf.net\n");
1407 if (unlikely(event & OHCI1394_postedWriteErr))
1408 fw_error("PCI posted write error\n");
1410 if (unlikely(event & OHCI1394_cycleTooLong)) {
1411 if (printk_ratelimit())
1412 fw_notify("isochronous cycle too long\n");
1413 reg_write(ohci, OHCI1394_LinkControlSet,
1414 OHCI1394_LinkControl_cycleMaster);
1417 if (event & OHCI1394_cycle64Seconds) {
1418 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1419 if ((cycle_time & 0x80000000) == 0)
1420 ohci->bus_seconds++;
1426 static int software_reset(struct fw_ohci *ohci)
1430 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1432 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1433 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1434 OHCI1394_HCControl_softReset) == 0)
1442 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1444 struct fw_ohci *ohci = fw_ohci(card);
1445 struct pci_dev *dev = to_pci_dev(card->device);
1449 if (software_reset(ohci)) {
1450 fw_error("Failed to reset ohci card.\n");
1455 * Now enable LPS, which we need in order to start accessing
1456 * most of the registers. In fact, on some cards (ALI M5251),
1457 * accessing registers in the SClk domain without LPS enabled
1458 * will lock up the machine. Wait 50msec to make sure we have
1459 * full link enabled. However, with some cards (well, at least
1460 * a JMicron PCIe card), we have to try again sometimes.
1462 reg_write(ohci, OHCI1394_HCControlSet,
1463 OHCI1394_HCControl_LPS |
1464 OHCI1394_HCControl_postedWriteEnable);
1467 for (lps = 0, i = 0; !lps && i < 3; i++) {
1469 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1470 OHCI1394_HCControl_LPS;
1474 fw_error("Failed to set Link Power Status\n");
1478 reg_write(ohci, OHCI1394_HCControlClear,
1479 OHCI1394_HCControl_noByteSwapData);
1481 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1482 reg_write(ohci, OHCI1394_LinkControlClear,
1483 OHCI1394_LinkControl_rcvPhyPkt);
1484 reg_write(ohci, OHCI1394_LinkControlSet,
1485 OHCI1394_LinkControl_rcvSelfID |
1486 OHCI1394_LinkControl_cycleTimerEnable |
1487 OHCI1394_LinkControl_cycleMaster);
1489 reg_write(ohci, OHCI1394_ATRetries,
1490 OHCI1394_MAX_AT_REQ_RETRIES |
1491 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1492 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1494 ar_context_run(&ohci->ar_request_ctx);
1495 ar_context_run(&ohci->ar_response_ctx);
1497 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1498 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1499 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1500 reg_write(ohci, OHCI1394_IntMaskSet,
1501 OHCI1394_selfIDComplete |
1502 OHCI1394_RQPkt | OHCI1394_RSPkt |
1503 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1504 OHCI1394_isochRx | OHCI1394_isochTx |
1505 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1506 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1507 OHCI1394_masterIntEnable);
1508 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1509 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1511 /* Activate link_on bit and contender bit in our self ID packets.*/
1512 if (ohci_update_phy_reg(card, 4, 0,
1513 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1517 * When the link is not yet enabled, the atomic config rom
1518 * update mechanism described below in ohci_set_config_rom()
1519 * is not active. We have to update ConfigRomHeader and
1520 * BusOptions manually, and the write to ConfigROMmap takes
1521 * effect immediately. We tie this to the enabling of the
1522 * link, so we have a valid config rom before enabling - the
1523 * OHCI requires that ConfigROMhdr and BusOptions have valid
1524 * values before enabling.
1526 * However, when the ConfigROMmap is written, some controllers
1527 * always read back quadlets 0 and 2 from the config rom to
1528 * the ConfigRomHeader and BusOptions registers on bus reset.
1529 * They shouldn't do that in this initial case where the link
1530 * isn't enabled. This means we have to use the same
1531 * workaround here, setting the bus header to 0 and then write
1532 * the right values in the bus reset tasklet.
1536 ohci->next_config_rom =
1537 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1538 &ohci->next_config_rom_bus,
1540 if (ohci->next_config_rom == NULL)
1543 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1544 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1547 * In the suspend case, config_rom is NULL, which
1548 * means that we just reuse the old config rom.
1550 ohci->next_config_rom = ohci->config_rom;
1551 ohci->next_config_rom_bus = ohci->config_rom_bus;
1554 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1555 ohci->next_config_rom[0] = 0;
1556 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1557 reg_write(ohci, OHCI1394_BusOptions,
1558 be32_to_cpu(ohci->next_config_rom[2]));
1559 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1561 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1563 if (request_irq(dev->irq, irq_handler,
1564 IRQF_SHARED, ohci_driver_name, ohci)) {
1565 fw_error("Failed to allocate shared interrupt %d.\n",
1567 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1568 ohci->config_rom, ohci->config_rom_bus);
1572 reg_write(ohci, OHCI1394_HCControlSet,
1573 OHCI1394_HCControl_linkEnable |
1574 OHCI1394_HCControl_BIBimageValid);
1578 * We are ready to go, initiate bus reset to finish the
1582 fw_core_initiate_bus_reset(&ohci->card, 1);
1587 static int ohci_set_config_rom(struct fw_card *card,
1588 u32 *config_rom, size_t length)
1590 struct fw_ohci *ohci;
1591 unsigned long flags;
1593 __be32 *next_config_rom;
1594 dma_addr_t uninitialized_var(next_config_rom_bus);
1596 ohci = fw_ohci(card);
1599 * When the OHCI controller is enabled, the config rom update
1600 * mechanism is a bit tricky, but easy enough to use. See
1601 * section 5.5.6 in the OHCI specification.
1603 * The OHCI controller caches the new config rom address in a
1604 * shadow register (ConfigROMmapNext) and needs a bus reset
1605 * for the changes to take place. When the bus reset is
1606 * detected, the controller loads the new values for the
1607 * ConfigRomHeader and BusOptions registers from the specified
1608 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1609 * shadow register. All automatically and atomically.
1611 * Now, there's a twist to this story. The automatic load of
1612 * ConfigRomHeader and BusOptions doesn't honor the
1613 * noByteSwapData bit, so with a be32 config rom, the
1614 * controller will load be32 values in to these registers
1615 * during the atomic update, even on litte endian
1616 * architectures. The workaround we use is to put a 0 in the
1617 * header quadlet; 0 is endian agnostic and means that the
1618 * config rom isn't ready yet. In the bus reset tasklet we
1619 * then set up the real values for the two registers.
1621 * We use ohci->lock to avoid racing with the code that sets
1622 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1626 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1627 &next_config_rom_bus, GFP_KERNEL);
1628 if (next_config_rom == NULL)
1631 spin_lock_irqsave(&ohci->lock, flags);
1633 if (ohci->next_config_rom == NULL) {
1634 ohci->next_config_rom = next_config_rom;
1635 ohci->next_config_rom_bus = next_config_rom_bus;
1637 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1638 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1641 ohci->next_header = config_rom[0];
1642 ohci->next_config_rom[0] = 0;
1644 reg_write(ohci, OHCI1394_ConfigROMmap,
1645 ohci->next_config_rom_bus);
1649 spin_unlock_irqrestore(&ohci->lock, flags);
1652 * Now initiate a bus reset to have the changes take
1653 * effect. We clean up the old config rom memory and DMA
1654 * mappings in the bus reset tasklet, since the OHCI
1655 * controller could need to access it before the bus reset
1659 fw_core_initiate_bus_reset(&ohci->card, 1);
1661 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1662 next_config_rom, next_config_rom_bus);
1667 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1669 struct fw_ohci *ohci = fw_ohci(card);
1671 at_context_transmit(&ohci->at_request_ctx, packet);
1674 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1676 struct fw_ohci *ohci = fw_ohci(card);
1678 at_context_transmit(&ohci->at_response_ctx, packet);
1681 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1683 struct fw_ohci *ohci = fw_ohci(card);
1684 struct context *ctx = &ohci->at_request_ctx;
1685 struct driver_data *driver_data = packet->driver_data;
1688 tasklet_disable(&ctx->tasklet);
1690 if (packet->ack != 0)
1693 if (packet->payload_bus)
1694 dma_unmap_single(ohci->card.device, packet->payload_bus,
1695 packet->payload_length, DMA_TO_DEVICE);
1697 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1698 driver_data->packet = NULL;
1699 packet->ack = RCODE_CANCELLED;
1700 packet->callback(packet, &ohci->card, packet->ack);
1703 tasklet_enable(&ctx->tasklet);
1708 static int ohci_enable_phys_dma(struct fw_card *card,
1709 int node_id, int generation)
1711 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1714 struct fw_ohci *ohci = fw_ohci(card);
1715 unsigned long flags;
1719 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1720 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1723 spin_lock_irqsave(&ohci->lock, flags);
1725 if (ohci->generation != generation) {
1731 * Note, if the node ID contains a non-local bus ID, physical DMA is
1732 * enabled for _all_ nodes on remote buses.
1735 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1737 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1739 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1743 spin_unlock_irqrestore(&ohci->lock, flags);
1746 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1749 static u64 ohci_get_bus_time(struct fw_card *card)
1751 struct fw_ohci *ohci = fw_ohci(card);
1755 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1756 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1761 static void copy_iso_headers(struct iso_context *ctx, void *p)
1763 int i = ctx->header_length;
1765 if (i + ctx->base.header_size > PAGE_SIZE)
1769 * The iso header is byteswapped to little endian by
1770 * the controller, but the remaining header quadlets
1771 * are big endian. We want to present all the headers
1772 * as big endian, so we have to swap the first quadlet.
1774 if (ctx->base.header_size > 0)
1775 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1776 if (ctx->base.header_size > 4)
1777 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1778 if (ctx->base.header_size > 8)
1779 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1780 ctx->header_length += ctx->base.header_size;
1783 static int handle_ir_dualbuffer_packet(struct context *context,
1784 struct descriptor *d,
1785 struct descriptor *last)
1787 struct iso_context *ctx =
1788 container_of(context, struct iso_context, context);
1789 struct db_descriptor *db = (struct db_descriptor *) d;
1791 size_t header_length;
1794 if (db->first_res_count != 0 && db->second_res_count != 0) {
1795 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1796 /* This descriptor isn't done yet, stop iteration. */
1799 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1802 header_length = le16_to_cpu(db->first_req_count) -
1803 le16_to_cpu(db->first_res_count);
1806 end = p + header_length;
1808 copy_iso_headers(ctx, p);
1809 ctx->excess_bytes +=
1810 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1811 p += max(ctx->base.header_size, (size_t)8);
1814 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1815 le16_to_cpu(db->second_res_count);
1817 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1818 ir_header = (__le32 *) (db + 1);
1819 ctx->base.callback(&ctx->base,
1820 le32_to_cpu(ir_header[0]) & 0xffff,
1821 ctx->header_length, ctx->header,
1822 ctx->base.callback_data);
1823 ctx->header_length = 0;
1829 static int handle_ir_packet_per_buffer(struct context *context,
1830 struct descriptor *d,
1831 struct descriptor *last)
1833 struct iso_context *ctx =
1834 container_of(context, struct iso_context, context);
1835 struct descriptor *pd;
1839 for (pd = d; pd <= last; pd++) {
1840 if (pd->transfer_status)
1844 /* Descriptor(s) not done yet, stop iteration */
1848 copy_iso_headers(ctx, p);
1850 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1851 ir_header = (__le32 *) p;
1852 ctx->base.callback(&ctx->base,
1853 le32_to_cpu(ir_header[0]) & 0xffff,
1854 ctx->header_length, ctx->header,
1855 ctx->base.callback_data);
1856 ctx->header_length = 0;
1862 static int handle_it_packet(struct context *context,
1863 struct descriptor *d,
1864 struct descriptor *last)
1866 struct iso_context *ctx =
1867 container_of(context, struct iso_context, context);
1869 if (last->transfer_status == 0)
1870 /* This descriptor isn't done yet, stop iteration. */
1873 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1874 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1875 0, NULL, ctx->base.callback_data);
1880 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1881 int type, int channel, size_t header_size)
1883 struct fw_ohci *ohci = fw_ohci(card);
1884 struct iso_context *ctx, *list;
1885 descriptor_callback_t callback;
1886 u64 *channels, dont_care = ~0ULL;
1888 unsigned long flags;
1889 int index, ret = -ENOMEM;
1891 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1892 channels = &dont_care;
1893 mask = &ohci->it_context_mask;
1894 list = ohci->it_context_list;
1895 callback = handle_it_packet;
1897 channels = &ohci->ir_context_channels;
1898 mask = &ohci->ir_context_mask;
1899 list = ohci->ir_context_list;
1900 if (ohci->use_dualbuffer)
1901 callback = handle_ir_dualbuffer_packet;
1903 callback = handle_ir_packet_per_buffer;
1906 spin_lock_irqsave(&ohci->lock, flags);
1907 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1909 *channels &= ~(1ULL << channel);
1910 *mask &= ~(1 << index);
1912 spin_unlock_irqrestore(&ohci->lock, flags);
1915 return ERR_PTR(-EBUSY);
1917 if (type == FW_ISO_CONTEXT_TRANSMIT)
1918 regs = OHCI1394_IsoXmitContextBase(index);
1920 regs = OHCI1394_IsoRcvContextBase(index);
1923 memset(ctx, 0, sizeof(*ctx));
1924 ctx->header_length = 0;
1925 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1926 if (ctx->header == NULL)
1929 ret = context_init(&ctx->context, ohci, regs, callback);
1931 goto out_with_header;
1936 free_page((unsigned long)ctx->header);
1938 spin_lock_irqsave(&ohci->lock, flags);
1939 *mask |= 1 << index;
1940 spin_unlock_irqrestore(&ohci->lock, flags);
1942 return ERR_PTR(ret);
1945 static int ohci_start_iso(struct fw_iso_context *base,
1946 s32 cycle, u32 sync, u32 tags)
1948 struct iso_context *ctx = container_of(base, struct iso_context, base);
1949 struct fw_ohci *ohci = ctx->context.ohci;
1953 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1954 index = ctx - ohci->it_context_list;
1957 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1958 (cycle & 0x7fff) << 16;
1960 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1961 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1962 context_run(&ctx->context, match);
1964 index = ctx - ohci->ir_context_list;
1965 control = IR_CONTEXT_ISOCH_HEADER;
1966 if (ohci->use_dualbuffer)
1967 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1968 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1970 match |= (cycle & 0x07fff) << 12;
1971 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1974 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1975 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1976 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1977 context_run(&ctx->context, control);
1983 static int ohci_stop_iso(struct fw_iso_context *base)
1985 struct fw_ohci *ohci = fw_ohci(base->card);
1986 struct iso_context *ctx = container_of(base, struct iso_context, base);
1989 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1990 index = ctx - ohci->it_context_list;
1991 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1993 index = ctx - ohci->ir_context_list;
1994 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1997 context_stop(&ctx->context);
2002 static void ohci_free_iso_context(struct fw_iso_context *base)
2004 struct fw_ohci *ohci = fw_ohci(base->card);
2005 struct iso_context *ctx = container_of(base, struct iso_context, base);
2006 unsigned long flags;
2009 ohci_stop_iso(base);
2010 context_release(&ctx->context);
2011 free_page((unsigned long)ctx->header);
2013 spin_lock_irqsave(&ohci->lock, flags);
2015 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2016 index = ctx - ohci->it_context_list;
2017 ohci->it_context_mask |= 1 << index;
2019 index = ctx - ohci->ir_context_list;
2020 ohci->ir_context_mask |= 1 << index;
2021 ohci->ir_context_channels |= 1ULL << base->channel;
2024 spin_unlock_irqrestore(&ohci->lock, flags);
2027 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2028 struct fw_iso_packet *packet,
2029 struct fw_iso_buffer *buffer,
2030 unsigned long payload)
2032 struct iso_context *ctx = container_of(base, struct iso_context, base);
2033 struct descriptor *d, *last, *pd;
2034 struct fw_iso_packet *p;
2036 dma_addr_t d_bus, page_bus;
2037 u32 z, header_z, payload_z, irq;
2038 u32 payload_index, payload_end_index, next_page_index;
2039 int page, end_page, i, length, offset;
2042 * FIXME: Cycle lost behavior should be configurable: lose
2043 * packet, retransmit or terminate..
2047 payload_index = payload;
2053 if (p->header_length > 0)
2056 /* Determine the first page the payload isn't contained in. */
2057 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2058 if (p->payload_length > 0)
2059 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2065 /* Get header size in number of descriptors. */
2066 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2068 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2073 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2074 d[0].req_count = cpu_to_le16(8);
2076 header = (__le32 *) &d[1];
2077 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2078 IT_HEADER_TAG(p->tag) |
2079 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2080 IT_HEADER_CHANNEL(ctx->base.channel) |
2081 IT_HEADER_SPEED(ctx->base.speed));
2083 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2084 p->payload_length));
2087 if (p->header_length > 0) {
2088 d[2].req_count = cpu_to_le16(p->header_length);
2089 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2090 memcpy(&d[z], p->header, p->header_length);
2093 pd = d + z - payload_z;
2094 payload_end_index = payload_index + p->payload_length;
2095 for (i = 0; i < payload_z; i++) {
2096 page = payload_index >> PAGE_SHIFT;
2097 offset = payload_index & ~PAGE_MASK;
2098 next_page_index = (page + 1) << PAGE_SHIFT;
2100 min(next_page_index, payload_end_index) - payload_index;
2101 pd[i].req_count = cpu_to_le16(length);
2103 page_bus = page_private(buffer->pages[page]);
2104 pd[i].data_address = cpu_to_le32(page_bus + offset);
2106 payload_index += length;
2110 irq = DESCRIPTOR_IRQ_ALWAYS;
2112 irq = DESCRIPTOR_NO_IRQ;
2114 last = z == 2 ? d : d + z - 1;
2115 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2117 DESCRIPTOR_BRANCH_ALWAYS |
2120 context_append(&ctx->context, d, z, header_z);
2125 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2126 struct fw_iso_packet *packet,
2127 struct fw_iso_buffer *buffer,
2128 unsigned long payload)
2130 struct iso_context *ctx = container_of(base, struct iso_context, base);
2131 struct db_descriptor *db = NULL;
2132 struct descriptor *d;
2133 struct fw_iso_packet *p;
2134 dma_addr_t d_bus, page_bus;
2135 u32 z, header_z, length, rest;
2136 int page, offset, packet_count, header_size;
2139 * FIXME: Cycle lost behavior should be configurable: lose
2140 * packet, retransmit or terminate..
2147 * The OHCI controller puts the isochronous header and trailer in the
2148 * buffer, so we need at least 8 bytes.
2150 packet_count = p->header_length / ctx->base.header_size;
2151 header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2153 /* Get header size in number of descriptors. */
2154 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2155 page = payload >> PAGE_SHIFT;
2156 offset = payload & ~PAGE_MASK;
2157 rest = p->payload_length;
2159 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2161 d = context_get_descriptors(&ctx->context,
2162 z + header_z, &d_bus);
2166 db = (struct db_descriptor *) d;
2167 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2168 DESCRIPTOR_BRANCH_ALWAYS);
2170 cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2171 if (p->skip && rest == p->payload_length) {
2172 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2173 db->first_req_count = db->first_size;
2175 db->first_req_count = cpu_to_le16(header_size);
2177 db->first_res_count = db->first_req_count;
2178 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2180 if (p->skip && rest == p->payload_length)
2182 else if (offset + rest < PAGE_SIZE)
2185 length = PAGE_SIZE - offset;
2187 db->second_req_count = cpu_to_le16(length);
2188 db->second_res_count = db->second_req_count;
2189 page_bus = page_private(buffer->pages[page]);
2190 db->second_buffer = cpu_to_le32(page_bus + offset);
2192 if (p->interrupt && length == rest)
2193 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2195 context_append(&ctx->context, d, z, header_z);
2196 offset = (offset + length) & ~PAGE_MASK;
2205 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2206 struct fw_iso_packet *packet,
2207 struct fw_iso_buffer *buffer,
2208 unsigned long payload)
2210 struct iso_context *ctx = container_of(base, struct iso_context, base);
2211 struct descriptor *d = NULL, *pd = NULL;
2212 struct fw_iso_packet *p = packet;
2213 dma_addr_t d_bus, page_bus;
2214 u32 z, header_z, rest;
2216 int page, offset, packet_count, header_size, payload_per_buffer;
2219 * The OHCI controller puts the isochronous header and trailer in the
2220 * buffer, so we need at least 8 bytes.
2222 packet_count = p->header_length / ctx->base.header_size;
2223 header_size = max(ctx->base.header_size, (size_t)8);
2225 /* Get header size in number of descriptors. */
2226 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2227 page = payload >> PAGE_SHIFT;
2228 offset = payload & ~PAGE_MASK;
2229 payload_per_buffer = p->payload_length / packet_count;
2231 for (i = 0; i < packet_count; i++) {
2232 /* d points to the header descriptor */
2233 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2234 d = context_get_descriptors(&ctx->context,
2235 z + header_z, &d_bus);
2239 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2240 DESCRIPTOR_INPUT_MORE);
2241 if (p->skip && i == 0)
2242 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2243 d->req_count = cpu_to_le16(header_size);
2244 d->res_count = d->req_count;
2245 d->transfer_status = 0;
2246 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2248 rest = payload_per_buffer;
2249 for (j = 1; j < z; j++) {
2251 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2252 DESCRIPTOR_INPUT_MORE);
2254 if (offset + rest < PAGE_SIZE)
2257 length = PAGE_SIZE - offset;
2258 pd->req_count = cpu_to_le16(length);
2259 pd->res_count = pd->req_count;
2260 pd->transfer_status = 0;
2262 page_bus = page_private(buffer->pages[page]);
2263 pd->data_address = cpu_to_le32(page_bus + offset);
2265 offset = (offset + length) & ~PAGE_MASK;
2270 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2271 DESCRIPTOR_INPUT_LAST |
2272 DESCRIPTOR_BRANCH_ALWAYS);
2273 if (p->interrupt && i == packet_count - 1)
2274 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2276 context_append(&ctx->context, d, z, header_z);
2282 static int ohci_queue_iso(struct fw_iso_context *base,
2283 struct fw_iso_packet *packet,
2284 struct fw_iso_buffer *buffer,
2285 unsigned long payload)
2287 struct iso_context *ctx = container_of(base, struct iso_context, base);
2288 unsigned long flags;
2291 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2292 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2293 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2294 else if (ctx->context.ohci->use_dualbuffer)
2295 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2298 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2300 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2305 static const struct fw_card_driver ohci_driver = {
2306 .enable = ohci_enable,
2307 .update_phy_reg = ohci_update_phy_reg,
2308 .set_config_rom = ohci_set_config_rom,
2309 .send_request = ohci_send_request,
2310 .send_response = ohci_send_response,
2311 .cancel_packet = ohci_cancel_packet,
2312 .enable_phys_dma = ohci_enable_phys_dma,
2313 .get_bus_time = ohci_get_bus_time,
2315 .allocate_iso_context = ohci_allocate_iso_context,
2316 .free_iso_context = ohci_free_iso_context,
2317 .queue_iso = ohci_queue_iso,
2318 .start_iso = ohci_start_iso,
2319 .stop_iso = ohci_stop_iso,
2322 #ifdef CONFIG_PPC_PMAC
2323 static void ohci_pmac_on(struct pci_dev *dev)
2325 if (machine_is(powermac)) {
2326 struct device_node *ofn = pci_device_to_OF_node(dev);
2329 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2330 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2335 static void ohci_pmac_off(struct pci_dev *dev)
2337 if (machine_is(powermac)) {
2338 struct device_node *ofn = pci_device_to_OF_node(dev);
2341 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2342 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2347 #define ohci_pmac_on(dev)
2348 #define ohci_pmac_off(dev)
2349 #endif /* CONFIG_PPC_PMAC */
2351 static int __devinit pci_probe(struct pci_dev *dev,
2352 const struct pci_device_id *ent)
2354 struct fw_ohci *ohci;
2355 u32 bus_options, max_receive, link_speed, version;
2360 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2366 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2370 err = pci_enable_device(dev);
2372 fw_error("Failed to enable OHCI hardware\n");
2376 pci_set_master(dev);
2377 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2378 pci_set_drvdata(dev, ohci);
2380 spin_lock_init(&ohci->lock);
2382 tasklet_init(&ohci->bus_reset_tasklet,
2383 bus_reset_tasklet, (unsigned long)ohci);
2385 err = pci_request_region(dev, 0, ohci_driver_name);
2387 fw_error("MMIO resource unavailable\n");
2391 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2392 if (ohci->registers == NULL) {
2393 fw_error("Failed to remap registers\n");
2398 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2399 ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2401 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2402 #if !defined(CONFIG_X86_32)
2403 /* dual-buffer mode is broken with descriptor addresses above 2G */
2404 if (dev->vendor == PCI_VENDOR_ID_TI &&
2405 dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2406 ohci->use_dualbuffer = false;
2409 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2410 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2411 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2413 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2415 ar_context_init(&ohci->ar_request_ctx, ohci,
2416 OHCI1394_AsReqRcvContextControlSet);
2418 ar_context_init(&ohci->ar_response_ctx, ohci,
2419 OHCI1394_AsRspRcvContextControlSet);
2421 context_init(&ohci->at_request_ctx, ohci,
2422 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2424 context_init(&ohci->at_response_ctx, ohci,
2425 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2427 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2428 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2429 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2430 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2431 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2433 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2434 ohci->ir_context_channels = ~0ULL;
2435 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2436 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2437 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2438 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2440 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2445 /* self-id dma buffer allocation */
2446 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2450 if (ohci->self_id_cpu == NULL) {
2455 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2456 max_receive = (bus_options >> 12) & 0xf;
2457 link_speed = bus_options & 0x7;
2458 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2459 reg_read(ohci, OHCI1394_GUIDLo);
2461 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2465 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2466 dev_name(&dev->dev), version >> 16, version & 0xff);
2471 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2472 ohci->self_id_cpu, ohci->self_id_bus);
2474 kfree(ohci->ir_context_list);
2475 kfree(ohci->it_context_list);
2476 context_release(&ohci->at_response_ctx);
2477 context_release(&ohci->at_request_ctx);
2478 ar_context_release(&ohci->ar_response_ctx);
2479 ar_context_release(&ohci->ar_request_ctx);
2480 pci_iounmap(dev, ohci->registers);
2482 pci_release_region(dev, 0);
2484 pci_disable_device(dev);
2490 fw_error("Out of memory\n");
2495 static void pci_remove(struct pci_dev *dev)
2497 struct fw_ohci *ohci;
2499 ohci = pci_get_drvdata(dev);
2500 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2502 fw_core_remove_card(&ohci->card);
2505 * FIXME: Fail all pending packets here, now that the upper
2506 * layers can't queue any more.
2509 software_reset(ohci);
2510 free_irq(dev->irq, ohci);
2512 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2513 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2514 ohci->next_config_rom, ohci->next_config_rom_bus);
2515 if (ohci->config_rom)
2516 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2517 ohci->config_rom, ohci->config_rom_bus);
2518 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2519 ohci->self_id_cpu, ohci->self_id_bus);
2520 ar_context_release(&ohci->ar_request_ctx);
2521 ar_context_release(&ohci->ar_response_ctx);
2522 context_release(&ohci->at_request_ctx);
2523 context_release(&ohci->at_response_ctx);
2524 kfree(ohci->it_context_list);
2525 kfree(ohci->ir_context_list);
2526 pci_iounmap(dev, ohci->registers);
2527 pci_release_region(dev, 0);
2528 pci_disable_device(dev);
2532 fw_notify("Removed fw-ohci device.\n");
2536 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2538 struct fw_ohci *ohci = pci_get_drvdata(dev);
2541 software_reset(ohci);
2542 free_irq(dev->irq, ohci);
2543 err = pci_save_state(dev);
2545 fw_error("pci_save_state failed\n");
2548 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2550 fw_error("pci_set_power_state failed with %d\n", err);
2556 static int pci_resume(struct pci_dev *dev)
2558 struct fw_ohci *ohci = pci_get_drvdata(dev);
2562 pci_set_power_state(dev, PCI_D0);
2563 pci_restore_state(dev);
2564 err = pci_enable_device(dev);
2566 fw_error("pci_enable_device failed\n");
2570 return ohci_enable(&ohci->card, NULL, 0);
2574 static struct pci_device_id pci_table[] = {
2575 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2579 MODULE_DEVICE_TABLE(pci, pci_table);
2581 static struct pci_driver fw_ohci_pci_driver = {
2582 .name = ohci_driver_name,
2583 .id_table = pci_table,
2585 .remove = pci_remove,
2587 .resume = pci_resume,
2588 .suspend = pci_suspend,
2592 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2593 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2594 MODULE_LICENSE("GPL");
2596 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2597 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2598 MODULE_ALIAS("ohci1394");
2601 static int __init fw_ohci_init(void)
2603 return pci_register_driver(&fw_ohci_pci_driver);
2606 static void __exit fw_ohci_cleanup(void)
2608 pci_unregister_driver(&fw_ohci_pci_driver);
2611 module_init(fw_ohci_init);
2612 module_exit(fw_ohci_cleanup);