1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
32 #define INTEL_GMCH_CTRL 0x52
33 #define INTEL_GMCH_ENABLED 0x4
34 #define INTEL_GMCH_MEM_MASK 0x1
35 #define INTEL_GMCH_MEM_64M 0x1
36 #define INTEL_GMCH_MEM_128M 0
38 #define INTEL_GMCH_GMS_MASK (0xf << 4)
39 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
40 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
41 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
42 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
46 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
47 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
48 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
49 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
50 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
51 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
52 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
53 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
55 /* PCI config space */
57 #define HPLLCC 0xc0 /* 855 only */
58 #define GC_CLOCK_CONTROL_MASK (3 << 0)
59 #define GC_CLOCK_133_200 (0 << 0)
60 #define GC_CLOCK_100_200 (1 << 0)
61 #define GC_CLOCK_100_133 (2 << 0)
62 #define GC_CLOCK_166_250 (3 << 0)
63 #define GCFGC 0xf0 /* 915+ only */
64 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
65 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
66 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
67 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
72 #define VGA_ST01_MDA 0x3ba
73 #define VGA_ST01_CGA 0x3da
75 #define VGA_MSR_WRITE 0x3c2
76 #define VGA_MSR_READ 0x3cc
77 #define VGA_MSR_MEM_EN (1<<1)
78 #define VGA_MSR_CGA_MODE (1<<0)
80 #define VGA_SR_INDEX 0x3c4
81 #define VGA_SR_DATA 0x3c5
83 #define VGA_AR_INDEX 0x3c0
84 #define VGA_AR_VID_EN (1<<5)
85 #define VGA_AR_DATA_WRITE 0x3c0
86 #define VGA_AR_DATA_READ 0x3c1
88 #define VGA_GR_INDEX 0x3ce
89 #define VGA_GR_DATA 0x3cf
91 #define VGA_GR_MEM_READ_MODE_SHIFT 3
92 #define VGA_GR_MEM_READ_MODE_PLANE 1
94 #define VGA_GR_MEM_MODE_MASK 0xc
95 #define VGA_GR_MEM_MODE_SHIFT 2
96 #define VGA_GR_MEM_A0000_AFFFF 0
97 #define VGA_GR_MEM_A0000_BFFFF 1
98 #define VGA_GR_MEM_B0000_B7FFF 2
99 #define VGA_GR_MEM_B0000_BFFFF 3
101 #define VGA_DACMASK 0x3c6
102 #define VGA_DACRX 0x3c7
103 #define VGA_DACWX 0x3c8
104 #define VGA_DACDATA 0x3c9
106 #define VGA_CR_INDEX_MDA 0x3b4
107 #define VGA_CR_DATA_MDA 0x3b5
108 #define VGA_CR_INDEX_CGA 0x3d4
109 #define VGA_CR_DATA_CGA 0x3d5
112 * Memory interface instructions used by the kernel
114 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
116 #define MI_NOOP MI_INSTR(0, 0)
117 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
118 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
119 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
120 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
121 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
122 #define MI_FLUSH MI_INSTR(0x04, 0)
123 #define MI_READ_FLUSH (1 << 0)
124 #define MI_EXE_FLUSH (1 << 1)
125 #define MI_NO_WRITE_FLUSH (1 << 2)
126 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
127 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
128 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
129 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
130 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
131 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
132 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
133 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
134 #define MI_STORE_DWORD_INDEX_SHIFT 2
135 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
136 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
137 #define MI_BATCH_NON_SECURE (1)
138 #define MI_BATCH_NON_SECURE_I965 (1<<8)
139 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
142 * 3D instructions used by the kernel
144 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
146 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
147 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
148 #define SC_UPDATE_SCISSOR (0x1<<1)
149 #define SC_ENABLE_MASK (0x1<<0)
150 #define SC_ENABLE (0x1<<0)
151 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
152 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
153 #define SCI_YMIN_MASK (0xffff<<16)
154 #define SCI_XMIN_MASK (0xffff<<0)
155 #define SCI_YMAX_MASK (0xffff<<16)
156 #define SCI_XMAX_MASK (0xffff<<0)
157 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
158 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
159 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
160 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
161 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
162 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
163 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
164 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
165 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
166 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
167 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
168 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
169 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
170 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
171 #define BLT_DEPTH_8 (0<<24)
172 #define BLT_DEPTH_16_565 (1<<24)
173 #define BLT_DEPTH_16_1555 (2<<24)
174 #define BLT_DEPTH_32 (3<<24)
175 #define BLT_ROP_GXCOPY (0xcc<<16)
176 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
177 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
178 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
179 #define ASYNC_FLIP (1<<22)
180 #define DISPLAY_PLANE_A (0<<20)
181 #define DISPLAY_PLANE_B (1<<20)
186 #define FENCE_REG_830_0 0x2000
187 #define FENCE_REG_945_8 0x3000
188 #define I830_FENCE_START_MASK 0x07f80000
189 #define I830_FENCE_TILING_Y_SHIFT 12
190 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
191 #define I830_FENCE_PITCH_SHIFT 4
192 #define I830_FENCE_REG_VALID (1<<0)
193 #define I830_FENCE_MAX_PITCH_VAL 0x10
194 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
196 #define I915_FENCE_START_MASK 0x0ff00000
197 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
199 #define FENCE_REG_965_0 0x03000
200 #define I965_FENCE_PITCH_SHIFT 2
201 #define I965_FENCE_TILING_Y_SHIFT 1
202 #define I965_FENCE_REG_VALID (1<<0)
203 #define I965_FENCE_MAX_PITCH_VAL 0x0400
206 * Instruction and interrupt control regs
208 #define PRB0_TAIL 0x02030
209 #define PRB0_HEAD 0x02034
210 #define PRB0_START 0x02038
211 #define PRB0_CTL 0x0203c
212 #define TAIL_ADDR 0x001FFFF8
213 #define HEAD_WRAP_COUNT 0xFFE00000
214 #define HEAD_WRAP_ONE 0x00200000
215 #define HEAD_ADDR 0x001FFFFC
216 #define RING_NR_PAGES 0x001FF000
217 #define RING_REPORT_MASK 0x00000006
218 #define RING_REPORT_64K 0x00000002
219 #define RING_REPORT_128K 0x00000004
220 #define RING_NO_REPORT 0x00000000
221 #define RING_VALID_MASK 0x00000001
222 #define RING_VALID 0x00000001
223 #define RING_INVALID 0x00000000
224 #define PRB1_TAIL 0x02040 /* 915+ only */
225 #define PRB1_HEAD 0x02044 /* 915+ only */
226 #define PRB1_START 0x02048 /* 915+ only */
227 #define PRB1_CTL 0x0204c /* 915+ only */
228 #define ACTHD_I965 0x02074
229 #define HWS_PGA 0x02080
230 #define HWS_ADDRESS_MASK 0xfffff000
231 #define HWS_START_ADDRESS_SHIFT 4
232 #define IPEIR 0x02088
233 #define NOPID 0x02094
234 #define HWSTAM 0x02098
235 #define SCPD0 0x0209c /* 915+ only */
240 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
241 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
242 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
243 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
244 #define I915_HWB_OOM_INTERRUPT (1<<13)
245 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
246 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
247 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
248 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
249 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
250 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
251 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
252 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
253 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
254 #define I915_DEBUG_INTERRUPT (1<<2)
255 #define I915_USER_INTERRUPT (1<<1)
256 #define I915_ASLE_INTERRUPT (1<<0)
260 #define INSTPM 0x020c0
261 #define ACTHD 0x020c8
262 #define FW_BLC 0x020d8
263 #define FW_BLC_SELF 0x020e0 /* 915+ only */
264 #define MI_ARB_STATE 0x020e4 /* 915+ only */
265 #define CACHE_MODE_0 0x02120 /* 915+ only */
266 #define CM0_MASK_SHIFT 16
267 #define CM0_IZ_OPT_DISABLE (1<<6)
268 #define CM0_ZR_OPT_DISABLE (1<<5)
269 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
270 #define CM0_COLOR_EVICT_DISABLE (1<<3)
271 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
272 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
273 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
277 * Framebuffer compression (915+ only)
280 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
281 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
282 #define FBC_CONTROL 0x03208
283 #define FBC_CTL_EN (1<<31)
284 #define FBC_CTL_PERIODIC (1<<30)
285 #define FBC_CTL_INTERVAL_SHIFT (16)
286 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
287 #define FBC_CTL_STRIDE_SHIFT (5)
288 #define FBC_CTL_FENCENO (1<<0)
289 #define FBC_COMMAND 0x0320c
290 #define FBC_CMD_COMPRESS (1<<0)
291 #define FBC_STATUS 0x03210
292 #define FBC_STAT_COMPRESSING (1<<31)
293 #define FBC_STAT_COMPRESSED (1<<30)
294 #define FBC_STAT_MODIFIED (1<<29)
295 #define FBC_STAT_CURRENT_LINE (1<<0)
296 #define FBC_CONTROL2 0x03214
297 #define FBC_CTL_FENCE_DBL (0<<4)
298 #define FBC_CTL_IDLE_IMM (0<<2)
299 #define FBC_CTL_IDLE_FULL (1<<2)
300 #define FBC_CTL_IDLE_LINE (2<<2)
301 #define FBC_CTL_IDLE_DEBUG (3<<2)
302 #define FBC_CTL_CPU_FENCE (1<<1)
303 #define FBC_CTL_PLANEA (0<<0)
304 #define FBC_CTL_PLANEB (1<<0)
305 #define FBC_FENCE_OFF 0x0321b
307 #define FBC_LL_SIZE (1536)
320 # define GPIO_CLOCK_DIR_MASK (1 << 0)
321 # define GPIO_CLOCK_DIR_IN (0 << 1)
322 # define GPIO_CLOCK_DIR_OUT (1 << 1)
323 # define GPIO_CLOCK_VAL_MASK (1 << 2)
324 # define GPIO_CLOCK_VAL_OUT (1 << 3)
325 # define GPIO_CLOCK_VAL_IN (1 << 4)
326 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
327 # define GPIO_DATA_DIR_MASK (1 << 8)
328 # define GPIO_DATA_DIR_IN (0 << 9)
329 # define GPIO_DATA_DIR_OUT (1 << 9)
330 # define GPIO_DATA_VAL_MASK (1 << 10)
331 # define GPIO_DATA_VAL_OUT (1 << 11)
332 # define GPIO_DATA_VAL_IN (1 << 12)
333 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
336 * Clock control & power management
341 #define VGA_PD 0x6010
342 #define VGA0_PD_P2_DIV_4 (1 << 7)
343 #define VGA0_PD_P1_DIV_2 (1 << 5)
344 #define VGA0_PD_P1_SHIFT 0
345 #define VGA0_PD_P1_MASK (0x1f << 0)
346 #define VGA1_PD_P2_DIV_4 (1 << 15)
347 #define VGA1_PD_P1_DIV_2 (1 << 13)
348 #define VGA1_PD_P1_SHIFT 8
349 #define VGA1_PD_P1_MASK (0x1f << 8)
350 #define DPLL_A 0x06014
351 #define DPLL_B 0x06018
352 #define DPLL_VCO_ENABLE (1 << 31)
353 #define DPLL_DVO_HIGH_SPEED (1 << 30)
354 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
355 #define DPLL_VGA_MODE_DIS (1 << 28)
356 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
357 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
358 #define DPLL_MODE_MASK (3 << 26)
359 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
360 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
361 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
362 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
363 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
364 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
365 #define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
367 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
368 #define I915_CRC_ERROR_ENABLE (1UL<<29)
369 #define I915_CRC_DONE_ENABLE (1UL<<28)
370 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
371 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
372 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
373 #define I915_DPST_EVENT_ENABLE (1UL<<23)
374 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
375 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
376 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
377 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
378 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
379 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
380 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
381 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
382 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
383 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
384 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
385 #define I915_DPST_EVENT_STATUS (1UL<<7)
386 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
387 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
388 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
389 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
390 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
391 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
393 #define SRX_INDEX 0x3c4
394 #define SRX_DATA 0x3c5
396 #define SR01_SCREEN_OFF (1<<5)
399 #define PPCR_ON (1<<0)
402 #define DVOB_ON (1<<31)
404 #define DVOC_ON (1<<31)
406 #define LVDS_ON (1<<31)
409 #define ADPA_DPMS_MASK (~(3<<10))
410 #define ADPA_DPMS_ON (0<<10)
411 #define ADPA_DPMS_SUSPEND (1<<10)
412 #define ADPA_DPMS_STANDBY (2<<10)
413 #define ADPA_DPMS_OFF (3<<10)
415 #define RING_TAIL 0x00
416 #define TAIL_ADDR 0x001FFFF8
417 #define RING_HEAD 0x04
418 #define HEAD_WRAP_COUNT 0xFFE00000
419 #define HEAD_WRAP_ONE 0x00200000
420 #define HEAD_ADDR 0x001FFFFC
421 #define RING_START 0x08
422 #define START_ADDR 0xFFFFF000
423 #define RING_LEN 0x0C
424 #define RING_NR_PAGES 0x001FF000
425 #define RING_REPORT_MASK 0x00000006
426 #define RING_REPORT_64K 0x00000002
427 #define RING_REPORT_128K 0x00000004
428 #define RING_NO_REPORT 0x00000000
429 #define RING_VALID_MASK 0x00000001
430 #define RING_VALID 0x00000001
431 #define RING_INVALID 0x00000000
433 /* Scratch pad debug 0 reg:
435 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
437 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
438 * this field (only one bit may be set).
440 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
441 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
442 #define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
443 /* i830, required in DVO non-gang */
444 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
445 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
446 #define PLL_REF_INPUT_DREFCLK (0 << 13)
447 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
448 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
449 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
450 #define PLL_REF_INPUT_MASK (3 << 13)
451 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
453 * Parallel to Serial Load Pulse phase selection.
454 * Selects the phase for the 10X DPLL clock for the PCIe
455 * digital display port. The range is 4 to 13; 10 or more
456 * is just a flip delay. The default is 6
458 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
459 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
461 * SDVO multiplier for 945G/GM. Not used on 965.
463 #define SDVO_MULTIPLIER_MASK 0x000000ff
464 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
465 #define SDVO_MULTIPLIER_SHIFT_VGA 0
466 #define DPLL_A_MD 0x0601c /* 965+ only */
468 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
470 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
472 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
473 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
474 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
475 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
476 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
478 * SDVO/UDI pixel multiplier.
480 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
481 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
482 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
483 * dummy bytes in the datastream at an increased clock rate, with both sides of
484 * the link knowing how many bytes are fill.
486 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
487 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
488 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
489 * through an SDVO command.
491 * This register field has values of multiplication factor minus 1, with
492 * a maximum multiplier of 5 for SDVO.
494 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
495 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
497 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
498 * This best be set to the default value (3) or the CRT won't work. No,
499 * I don't entirely understand what this does...
501 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
502 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
503 #define DPLL_B_MD 0x06020 /* 965+ only */
508 #define FP_N_DIV_MASK 0x003f0000
509 #define FP_N_IGD_DIV_MASK 0x00ff0000
510 #define FP_N_DIV_SHIFT 16
511 #define FP_M1_DIV_MASK 0x00003f00
512 #define FP_M1_DIV_SHIFT 8
513 #define FP_M2_DIV_MASK 0x0000003f
514 #define FP_M2_IGD_DIV_MASK 0x000000ff
515 #define FP_M2_DIV_SHIFT 0
516 #define DPLL_TEST 0x606c
517 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
518 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
519 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
520 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
521 #define DPLLB_TEST_N_BYPASS (1 << 19)
522 #define DPLLB_TEST_M_BYPASS (1 << 18)
523 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
524 #define DPLLA_TEST_N_BYPASS (1 << 3)
525 #define DPLLA_TEST_M_BYPASS (1 << 2)
526 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
527 #define D_STATE 0x6104
528 #define CG_2D_DIS 0x6200
529 #define CG_3D_DIS 0x6204
535 #define PALETTE_A 0x0a000
536 #define PALETTE_B 0x0a800
543 * This mirrors the MCHBAR MMIO space whose location is determined by
544 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
545 * every way. It is not accessible from the CP register read instructions.
548 #define MCHBAR_MIRROR_BASE 0x10000
550 /** 915-945 and GM965 MCH register controlling DRAM channel access */
552 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
553 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
554 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
555 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
556 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
557 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
559 /** 965 MCH register controlling DRAM channel configuration */
560 #define C0DRB3 0x10206
561 #define C1DRB3 0x10606
563 /** GM965 GM45 render standby register */
564 #define MCHBAR_RENDER_STANDBY 0x111B8
566 #define PEG_BAND_GAP_DATA 0x14d68
572 #define OVADD 0x30000
573 #define DOVSTA 0x30008
574 #define OC_BUF (0x3<<20)
575 #define OGAMC5 0x30010
576 #define OGAMC4 0x30014
577 #define OGAMC3 0x30018
578 #define OGAMC2 0x3001c
579 #define OGAMC1 0x30020
580 #define OGAMC0 0x30024
583 * Display engine regs
586 /* Pipe A timing regs */
587 #define HTOTAL_A 0x60000
588 #define HBLANK_A 0x60004
589 #define HSYNC_A 0x60008
590 #define VTOTAL_A 0x6000c
591 #define VBLANK_A 0x60010
592 #define VSYNC_A 0x60014
593 #define PIPEASRC 0x6001c
594 #define BCLRPAT_A 0x60020
596 /* Pipe B timing regs */
597 #define HTOTAL_B 0x61000
598 #define HBLANK_B 0x61004
599 #define HSYNC_B 0x61008
600 #define VTOTAL_B 0x6100c
601 #define VBLANK_B 0x61010
602 #define VSYNC_B 0x61014
603 #define PIPEBSRC 0x6101c
604 #define BCLRPAT_B 0x61020
606 /* VGA port control */
608 #define ADPA_DAC_ENABLE (1<<31)
609 #define ADPA_DAC_DISABLE 0
610 #define ADPA_PIPE_SELECT_MASK (1<<30)
611 #define ADPA_PIPE_A_SELECT 0
612 #define ADPA_PIPE_B_SELECT (1<<30)
613 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
614 #define ADPA_SETS_HVPOLARITY 0
615 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
616 #define ADPA_VSYNC_CNTL_ENABLE 0
617 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
618 #define ADPA_HSYNC_CNTL_ENABLE 0
619 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
620 #define ADPA_VSYNC_ACTIVE_LOW 0
621 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
622 #define ADPA_HSYNC_ACTIVE_LOW 0
623 #define ADPA_DPMS_MASK (~(3<<10))
624 #define ADPA_DPMS_ON (0<<10)
625 #define ADPA_DPMS_SUSPEND (1<<10)
626 #define ADPA_DPMS_STANDBY (2<<10)
627 #define ADPA_DPMS_OFF (3<<10)
629 /* Hotplug control (945+ only) */
630 #define PORT_HOTPLUG_EN 0x61110
631 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
632 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
633 #define HDMID_HOTPLUG_INT_EN (1 << 27)
634 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
635 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
636 #define TV_HOTPLUG_INT_EN (1 << 18)
637 #define CRT_HOTPLUG_INT_EN (1 << 9)
638 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
639 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
640 /* must use period 64 on GM45 according to docs */
641 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
642 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
643 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
644 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
645 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
646 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
647 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
648 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
649 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
650 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
651 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
652 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
653 #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
656 #define PORT_HOTPLUG_STAT 0x61114
657 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
658 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
659 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
660 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
661 #define TV_HOTPLUG_INT_STATUS (1 << 10)
662 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
663 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
664 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
665 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
666 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
667 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
669 /* SDVO port control */
670 #define SDVOB 0x61140
671 #define SDVOC 0x61160
672 #define SDVO_ENABLE (1 << 31)
673 #define SDVO_PIPE_B_SELECT (1 << 30)
674 #define SDVO_STALL_SELECT (1 << 29)
675 #define SDVO_INTERRUPT_ENABLE (1 << 26)
677 * 915G/GM SDVO pixel multiplier.
679 * Programmed value is multiplier - 1, up to 5x.
681 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
683 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
684 #define SDVO_PORT_MULTIPLY_SHIFT 23
685 #define SDVO_PHASE_SELECT_MASK (15 << 19)
686 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
687 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
688 #define SDVOC_GANG_MODE (1 << 16)
689 #define SDVO_ENCODING_SDVO (0x0 << 10)
690 #define SDVO_ENCODING_HDMI (0x2 << 10)
691 /** Requird for HDMI operation */
692 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
693 #define SDVO_BORDER_ENABLE (1 << 7)
694 #define SDVO_AUDIO_ENABLE (1 << 6)
695 /** New with 965, default is to be set */
696 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
697 /** New with 965, default is to be set */
698 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
699 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
700 #define SDVO_DETECTED (1 << 2)
701 /* Bits to be preserved when writing */
702 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
703 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
705 /* DVO port control */
709 #define DVO_ENABLE (1 << 31)
710 #define DVO_PIPE_B_SELECT (1 << 30)
711 #define DVO_PIPE_STALL_UNUSED (0 << 28)
712 #define DVO_PIPE_STALL (1 << 28)
713 #define DVO_PIPE_STALL_TV (2 << 28)
714 #define DVO_PIPE_STALL_MASK (3 << 28)
715 #define DVO_USE_VGA_SYNC (1 << 15)
716 #define DVO_DATA_ORDER_I740 (0 << 14)
717 #define DVO_DATA_ORDER_FP (1 << 14)
718 #define DVO_VSYNC_DISABLE (1 << 11)
719 #define DVO_HSYNC_DISABLE (1 << 10)
720 #define DVO_VSYNC_TRISTATE (1 << 9)
721 #define DVO_HSYNC_TRISTATE (1 << 8)
722 #define DVO_BORDER_ENABLE (1 << 7)
723 #define DVO_DATA_ORDER_GBRG (1 << 6)
724 #define DVO_DATA_ORDER_RGGB (0 << 6)
725 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
726 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
727 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
728 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
729 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
730 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
731 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
732 #define DVO_PRESERVE_MASK (0x7<<24)
733 #define DVOA_SRCDIM 0x61124
734 #define DVOB_SRCDIM 0x61144
735 #define DVOC_SRCDIM 0x61164
736 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
737 #define DVO_SRCDIM_VERTICAL_SHIFT 0
739 /* LVDS port control */
742 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
743 * the DPLL semantics change when the LVDS is assigned to that pipe.
745 #define LVDS_PORT_EN (1 << 31)
746 /* Selects pipe B for LVDS data. Must be set on pre-965. */
747 #define LVDS_PIPEB_SELECT (1 << 30)
749 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
752 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
753 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
754 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
756 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
757 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
760 #define LVDS_A3_POWER_MASK (3 << 6)
761 #define LVDS_A3_POWER_DOWN (0 << 6)
762 #define LVDS_A3_POWER_UP (3 << 6)
764 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
767 #define LVDS_CLKB_POWER_MASK (3 << 4)
768 #define LVDS_CLKB_POWER_DOWN (0 << 4)
769 #define LVDS_CLKB_POWER_UP (3 << 4)
771 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
772 * setting for whether we are in dual-channel mode. The B3 pair will
773 * additionally only be powered up when LVDS_A3_POWER_UP is set.
775 #define LVDS_B0B3_POWER_MASK (3 << 2)
776 #define LVDS_B0B3_POWER_DOWN (0 << 2)
777 #define LVDS_B0B3_POWER_UP (3 << 2)
779 /* Panel power sequencing */
780 #define PP_STATUS 0x61200
781 #define PP_ON (1 << 31)
783 * Indicates that all dependencies of the panel are on:
787 * - LVDS/DVOB/DVOC on
789 #define PP_READY (1 << 30)
790 #define PP_SEQUENCE_NONE (0 << 28)
791 #define PP_SEQUENCE_ON (1 << 28)
792 #define PP_SEQUENCE_OFF (2 << 28)
793 #define PP_SEQUENCE_MASK 0x30000000
794 #define PP_CONTROL 0x61204
795 #define POWER_TARGET_ON (1 << 0)
796 #define PP_ON_DELAYS 0x61208
797 #define PP_OFF_DELAYS 0x6120c
798 #define PP_DIVISOR 0x61210
801 #define PFIT_CONTROL 0x61230
802 #define PFIT_ENABLE (1 << 31)
803 #define PFIT_PIPE_MASK (3 << 29)
804 #define PFIT_PIPE_SHIFT 29
805 #define VERT_INTERP_DISABLE (0 << 10)
806 #define VERT_INTERP_BILINEAR (1 << 10)
807 #define VERT_INTERP_MASK (3 << 10)
808 #define VERT_AUTO_SCALE (1 << 9)
809 #define HORIZ_INTERP_DISABLE (0 << 6)
810 #define HORIZ_INTERP_BILINEAR (1 << 6)
811 #define HORIZ_INTERP_MASK (3 << 6)
812 #define HORIZ_AUTO_SCALE (1 << 5)
813 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
814 #define PFIT_PGM_RATIOS 0x61234
815 #define PFIT_VERT_SCALE_MASK 0xfff00000
816 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
817 #define PFIT_AUTO_RATIOS 0x61238
819 /* Backlight control */
820 #define BLC_PWM_CTL 0x61254
821 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
822 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
823 #define BLM_COMBINATION_MODE (1 << 30)
825 * This is the most significant 15 bits of the number of backlight cycles in a
826 * complete cycle of the modulated backlight control.
828 * The actual value is this field multiplied by two.
830 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
831 #define BLM_LEGACY_MODE (1 << 16)
833 * This is the number of cycles out of the backlight modulation cycle for which
834 * the backlight is on.
836 * This field must be no greater than the number of cycles in the complete
837 * backlight modulation cycle.
839 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
840 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
842 /* TV port control */
843 #define TV_CTL 0x68000
844 /** Enables the TV encoder */
845 # define TV_ENC_ENABLE (1 << 31)
846 /** Sources the TV encoder input from pipe B instead of A. */
847 # define TV_ENC_PIPEB_SELECT (1 << 30)
848 /** Outputs composite video (DAC A only) */
849 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
850 /** Outputs SVideo video (DAC B/C) */
851 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
852 /** Outputs Component video (DAC A/B/C) */
853 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
854 /** Outputs Composite and SVideo (DAC A/B/C) */
855 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
856 # define TV_TRILEVEL_SYNC (1 << 21)
857 /** Enables slow sync generation (945GM only) */
858 # define TV_SLOW_SYNC (1 << 20)
859 /** Selects 4x oversampling for 480i and 576p */
860 # define TV_OVERSAMPLE_4X (0 << 18)
861 /** Selects 2x oversampling for 720p and 1080i */
862 # define TV_OVERSAMPLE_2X (1 << 18)
863 /** Selects no oversampling for 1080p */
864 # define TV_OVERSAMPLE_NONE (2 << 18)
865 /** Selects 8x oversampling */
866 # define TV_OVERSAMPLE_8X (3 << 18)
867 /** Selects progressive mode rather than interlaced */
868 # define TV_PROGRESSIVE (1 << 17)
869 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
870 # define TV_PAL_BURST (1 << 16)
871 /** Field for setting delay of Y compared to C */
872 # define TV_YC_SKEW_MASK (7 << 12)
873 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
874 # define TV_ENC_SDP_FIX (1 << 11)
876 * Enables a fix for the 915GM only.
878 * Not sure what it does.
880 # define TV_ENC_C0_FIX (1 << 10)
881 /** Bits that must be preserved by software */
882 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
883 # define TV_FUSE_STATE_MASK (3 << 4)
884 /** Read-only state that reports all features enabled */
885 # define TV_FUSE_STATE_ENABLED (0 << 4)
886 /** Read-only state that reports that Macrovision is disabled in hardware*/
887 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
888 /** Read-only state that reports that TV-out is disabled in hardware. */
889 # define TV_FUSE_STATE_DISABLED (2 << 4)
890 /** Normal operation */
891 # define TV_TEST_MODE_NORMAL (0 << 0)
892 /** Encoder test pattern 1 - combo pattern */
893 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
894 /** Encoder test pattern 2 - full screen vertical 75% color bars */
895 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
896 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
897 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
898 /** Encoder test pattern 4 - random noise */
899 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
900 /** Encoder test pattern 5 - linear color ramps */
901 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
903 * This test mode forces the DACs to 50% of full output.
905 * This is used for load detection in combination with TVDAC_SENSE_MASK
907 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
908 # define TV_TEST_MODE_MASK (7 << 0)
910 #define TV_DAC 0x68004
912 * Reports that DAC state change logic has reported change (RO).
914 * This gets cleared when TV_DAC_STATE_EN is cleared
916 # define TVDAC_STATE_CHG (1 << 31)
917 # define TVDAC_SENSE_MASK (7 << 28)
918 /** Reports that DAC A voltage is above the detect threshold */
919 # define TVDAC_A_SENSE (1 << 30)
920 /** Reports that DAC B voltage is above the detect threshold */
921 # define TVDAC_B_SENSE (1 << 29)
922 /** Reports that DAC C voltage is above the detect threshold */
923 # define TVDAC_C_SENSE (1 << 28)
925 * Enables DAC state detection logic, for load-based TV detection.
927 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
928 * to off, for load detection to work.
930 # define TVDAC_STATE_CHG_EN (1 << 27)
931 /** Sets the DAC A sense value to high */
932 # define TVDAC_A_SENSE_CTL (1 << 26)
933 /** Sets the DAC B sense value to high */
934 # define TVDAC_B_SENSE_CTL (1 << 25)
935 /** Sets the DAC C sense value to high */
936 # define TVDAC_C_SENSE_CTL (1 << 24)
937 /** Overrides the ENC_ENABLE and DAC voltage levels */
938 # define DAC_CTL_OVERRIDE (1 << 7)
939 /** Sets the slew rate. Must be preserved in software */
940 # define ENC_TVDAC_SLEW_FAST (1 << 6)
941 # define DAC_A_1_3_V (0 << 4)
942 # define DAC_A_1_1_V (1 << 4)
943 # define DAC_A_0_7_V (2 << 4)
944 # define DAC_A_OFF (3 << 4)
945 # define DAC_B_1_3_V (0 << 2)
946 # define DAC_B_1_1_V (1 << 2)
947 # define DAC_B_0_7_V (2 << 2)
948 # define DAC_B_OFF (3 << 2)
949 # define DAC_C_1_3_V (0 << 0)
950 # define DAC_C_1_1_V (1 << 0)
951 # define DAC_C_0_7_V (2 << 0)
952 # define DAC_C_OFF (3 << 0)
955 * CSC coefficients are stored in a floating point format with 9 bits of
956 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
957 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
958 * -1 (0x3) being the only legal negative value.
960 #define TV_CSC_Y 0x68010
961 # define TV_RY_MASK 0x07ff0000
962 # define TV_RY_SHIFT 16
963 # define TV_GY_MASK 0x00000fff
964 # define TV_GY_SHIFT 0
966 #define TV_CSC_Y2 0x68014
967 # define TV_BY_MASK 0x07ff0000
968 # define TV_BY_SHIFT 16
970 * Y attenuation for component video.
972 * Stored in 1.9 fixed point.
974 # define TV_AY_MASK 0x000003ff
975 # define TV_AY_SHIFT 0
977 #define TV_CSC_U 0x68018
978 # define TV_RU_MASK 0x07ff0000
979 # define TV_RU_SHIFT 16
980 # define TV_GU_MASK 0x000007ff
981 # define TV_GU_SHIFT 0
983 #define TV_CSC_U2 0x6801c
984 # define TV_BU_MASK 0x07ff0000
985 # define TV_BU_SHIFT 16
987 * U attenuation for component video.
989 * Stored in 1.9 fixed point.
991 # define TV_AU_MASK 0x000003ff
992 # define TV_AU_SHIFT 0
994 #define TV_CSC_V 0x68020
995 # define TV_RV_MASK 0x0fff0000
996 # define TV_RV_SHIFT 16
997 # define TV_GV_MASK 0x000007ff
998 # define TV_GV_SHIFT 0
1000 #define TV_CSC_V2 0x68024
1001 # define TV_BV_MASK 0x07ff0000
1002 # define TV_BV_SHIFT 16
1004 * V attenuation for component video.
1006 * Stored in 1.9 fixed point.
1008 # define TV_AV_MASK 0x000007ff
1009 # define TV_AV_SHIFT 0
1011 #define TV_CLR_KNOBS 0x68028
1012 /** 2s-complement brightness adjustment */
1013 # define TV_BRIGHTNESS_MASK 0xff000000
1014 # define TV_BRIGHTNESS_SHIFT 24
1015 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1016 # define TV_CONTRAST_MASK 0x00ff0000
1017 # define TV_CONTRAST_SHIFT 16
1018 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1019 # define TV_SATURATION_MASK 0x0000ff00
1020 # define TV_SATURATION_SHIFT 8
1021 /** Hue adjustment, as an integer phase angle in degrees */
1022 # define TV_HUE_MASK 0x000000ff
1023 # define TV_HUE_SHIFT 0
1025 #define TV_CLR_LEVEL 0x6802c
1026 /** Controls the DAC level for black */
1027 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1028 # define TV_BLACK_LEVEL_SHIFT 16
1029 /** Controls the DAC level for blanking */
1030 # define TV_BLANK_LEVEL_MASK 0x000001ff
1031 # define TV_BLANK_LEVEL_SHIFT 0
1033 #define TV_H_CTL_1 0x68030
1034 /** Number of pixels in the hsync. */
1035 # define TV_HSYNC_END_MASK 0x1fff0000
1036 # define TV_HSYNC_END_SHIFT 16
1037 /** Total number of pixels minus one in the line (display and blanking). */
1038 # define TV_HTOTAL_MASK 0x00001fff
1039 # define TV_HTOTAL_SHIFT 0
1041 #define TV_H_CTL_2 0x68034
1042 /** Enables the colorburst (needed for non-component color) */
1043 # define TV_BURST_ENA (1 << 31)
1044 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1045 # define TV_HBURST_START_SHIFT 16
1046 # define TV_HBURST_START_MASK 0x1fff0000
1047 /** Length of the colorburst */
1048 # define TV_HBURST_LEN_SHIFT 0
1049 # define TV_HBURST_LEN_MASK 0x0001fff
1051 #define TV_H_CTL_3 0x68038
1052 /** End of hblank, measured in pixels minus one from start of hsync */
1053 # define TV_HBLANK_END_SHIFT 16
1054 # define TV_HBLANK_END_MASK 0x1fff0000
1055 /** Start of hblank, measured in pixels minus one from start of hsync */
1056 # define TV_HBLANK_START_SHIFT 0
1057 # define TV_HBLANK_START_MASK 0x0001fff
1059 #define TV_V_CTL_1 0x6803c
1061 # define TV_NBR_END_SHIFT 16
1062 # define TV_NBR_END_MASK 0x07ff0000
1064 # define TV_VI_END_F1_SHIFT 8
1065 # define TV_VI_END_F1_MASK 0x00003f00
1067 # define TV_VI_END_F2_SHIFT 0
1068 # define TV_VI_END_F2_MASK 0x0000003f
1070 #define TV_V_CTL_2 0x68040
1071 /** Length of vsync, in half lines */
1072 # define TV_VSYNC_LEN_MASK 0x07ff0000
1073 # define TV_VSYNC_LEN_SHIFT 16
1074 /** Offset of the start of vsync in field 1, measured in one less than the
1075 * number of half lines.
1077 # define TV_VSYNC_START_F1_MASK 0x00007f00
1078 # define TV_VSYNC_START_F1_SHIFT 8
1080 * Offset of the start of vsync in field 2, measured in one less than the
1081 * number of half lines.
1083 # define TV_VSYNC_START_F2_MASK 0x0000007f
1084 # define TV_VSYNC_START_F2_SHIFT 0
1086 #define TV_V_CTL_3 0x68044
1087 /** Enables generation of the equalization signal */
1088 # define TV_EQUAL_ENA (1 << 31)
1089 /** Length of vsync, in half lines */
1090 # define TV_VEQ_LEN_MASK 0x007f0000
1091 # define TV_VEQ_LEN_SHIFT 16
1092 /** Offset of the start of equalization in field 1, measured in one less than
1093 * the number of half lines.
1095 # define TV_VEQ_START_F1_MASK 0x0007f00
1096 # define TV_VEQ_START_F1_SHIFT 8
1098 * Offset of the start of equalization in field 2, measured in one less than
1099 * the number of half lines.
1101 # define TV_VEQ_START_F2_MASK 0x000007f
1102 # define TV_VEQ_START_F2_SHIFT 0
1104 #define TV_V_CTL_4 0x68048
1106 * Offset to start of vertical colorburst, measured in one less than the
1107 * number of lines from vertical start.
1109 # define TV_VBURST_START_F1_MASK 0x003f0000
1110 # define TV_VBURST_START_F1_SHIFT 16
1112 * Offset to the end of vertical colorburst, measured in one less than the
1113 * number of lines from the start of NBR.
1115 # define TV_VBURST_END_F1_MASK 0x000000ff
1116 # define TV_VBURST_END_F1_SHIFT 0
1118 #define TV_V_CTL_5 0x6804c
1120 * Offset to start of vertical colorburst, measured in one less than the
1121 * number of lines from vertical start.
1123 # define TV_VBURST_START_F2_MASK 0x003f0000
1124 # define TV_VBURST_START_F2_SHIFT 16
1126 * Offset to the end of vertical colorburst, measured in one less than the
1127 * number of lines from the start of NBR.
1129 # define TV_VBURST_END_F2_MASK 0x000000ff
1130 # define TV_VBURST_END_F2_SHIFT 0
1132 #define TV_V_CTL_6 0x68050
1134 * Offset to start of vertical colorburst, measured in one less than the
1135 * number of lines from vertical start.
1137 # define TV_VBURST_START_F3_MASK 0x003f0000
1138 # define TV_VBURST_START_F3_SHIFT 16
1140 * Offset to the end of vertical colorburst, measured in one less than the
1141 * number of lines from the start of NBR.
1143 # define TV_VBURST_END_F3_MASK 0x000000ff
1144 # define TV_VBURST_END_F3_SHIFT 0
1146 #define TV_V_CTL_7 0x68054
1148 * Offset to start of vertical colorburst, measured in one less than the
1149 * number of lines from vertical start.
1151 # define TV_VBURST_START_F4_MASK 0x003f0000
1152 # define TV_VBURST_START_F4_SHIFT 16
1154 * Offset to the end of vertical colorburst, measured in one less than the
1155 * number of lines from the start of NBR.
1157 # define TV_VBURST_END_F4_MASK 0x000000ff
1158 # define TV_VBURST_END_F4_SHIFT 0
1160 #define TV_SC_CTL_1 0x68060
1161 /** Turns on the first subcarrier phase generation DDA */
1162 # define TV_SC_DDA1_EN (1 << 31)
1163 /** Turns on the first subcarrier phase generation DDA */
1164 # define TV_SC_DDA2_EN (1 << 30)
1165 /** Turns on the first subcarrier phase generation DDA */
1166 # define TV_SC_DDA3_EN (1 << 29)
1167 /** Sets the subcarrier DDA to reset frequency every other field */
1168 # define TV_SC_RESET_EVERY_2 (0 << 24)
1169 /** Sets the subcarrier DDA to reset frequency every fourth field */
1170 # define TV_SC_RESET_EVERY_4 (1 << 24)
1171 /** Sets the subcarrier DDA to reset frequency every eighth field */
1172 # define TV_SC_RESET_EVERY_8 (2 << 24)
1173 /** Sets the subcarrier DDA to never reset the frequency */
1174 # define TV_SC_RESET_NEVER (3 << 24)
1175 /** Sets the peak amplitude of the colorburst.*/
1176 # define TV_BURST_LEVEL_MASK 0x00ff0000
1177 # define TV_BURST_LEVEL_SHIFT 16
1178 /** Sets the increment of the first subcarrier phase generation DDA */
1179 # define TV_SCDDA1_INC_MASK 0x00000fff
1180 # define TV_SCDDA1_INC_SHIFT 0
1182 #define TV_SC_CTL_2 0x68064
1183 /** Sets the rollover for the second subcarrier phase generation DDA */
1184 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1185 # define TV_SCDDA2_SIZE_SHIFT 16
1186 /** Sets the increent of the second subcarrier phase generation DDA */
1187 # define TV_SCDDA2_INC_MASK 0x00007fff
1188 # define TV_SCDDA2_INC_SHIFT 0
1190 #define TV_SC_CTL_3 0x68068
1191 /** Sets the rollover for the third subcarrier phase generation DDA */
1192 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1193 # define TV_SCDDA3_SIZE_SHIFT 16
1194 /** Sets the increent of the third subcarrier phase generation DDA */
1195 # define TV_SCDDA3_INC_MASK 0x00007fff
1196 # define TV_SCDDA3_INC_SHIFT 0
1198 #define TV_WIN_POS 0x68070
1199 /** X coordinate of the display from the start of horizontal active */
1200 # define TV_XPOS_MASK 0x1fff0000
1201 # define TV_XPOS_SHIFT 16
1202 /** Y coordinate of the display from the start of vertical active (NBR) */
1203 # define TV_YPOS_MASK 0x00000fff
1204 # define TV_YPOS_SHIFT 0
1206 #define TV_WIN_SIZE 0x68074
1207 /** Horizontal size of the display window, measured in pixels*/
1208 # define TV_XSIZE_MASK 0x1fff0000
1209 # define TV_XSIZE_SHIFT 16
1211 * Vertical size of the display window, measured in pixels.
1213 * Must be even for interlaced modes.
1215 # define TV_YSIZE_MASK 0x00000fff
1216 # define TV_YSIZE_SHIFT 0
1218 #define TV_FILTER_CTL_1 0x68080
1220 * Enables automatic scaling calculation.
1222 * If set, the rest of the registers are ignored, and the calculated values can
1223 * be read back from the register.
1225 # define TV_AUTO_SCALE (1 << 31)
1227 * Disables the vertical filter.
1229 * This is required on modes more than 1024 pixels wide */
1230 # define TV_V_FILTER_BYPASS (1 << 29)
1231 /** Enables adaptive vertical filtering */
1232 # define TV_VADAPT (1 << 28)
1233 # define TV_VADAPT_MODE_MASK (3 << 26)
1234 /** Selects the least adaptive vertical filtering mode */
1235 # define TV_VADAPT_MODE_LEAST (0 << 26)
1236 /** Selects the moderately adaptive vertical filtering mode */
1237 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1238 /** Selects the most adaptive vertical filtering mode */
1239 # define TV_VADAPT_MODE_MOST (3 << 26)
1241 * Sets the horizontal scaling factor.
1243 * This should be the fractional part of the horizontal scaling factor divided
1244 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1246 * (src width - 1) / ((oversample * dest width) - 1)
1248 # define TV_HSCALE_FRAC_MASK 0x00003fff
1249 # define TV_HSCALE_FRAC_SHIFT 0
1251 #define TV_FILTER_CTL_2 0x68084
1253 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1255 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1257 # define TV_VSCALE_INT_MASK 0x00038000
1258 # define TV_VSCALE_INT_SHIFT 15
1260 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1262 * \sa TV_VSCALE_INT_MASK
1264 # define TV_VSCALE_FRAC_MASK 0x00007fff
1265 # define TV_VSCALE_FRAC_SHIFT 0
1267 #define TV_FILTER_CTL_3 0x68088
1269 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1271 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1273 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1275 # define TV_VSCALE_IP_INT_MASK 0x00038000
1276 # define TV_VSCALE_IP_INT_SHIFT 15
1278 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1280 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1282 * \sa TV_VSCALE_IP_INT_MASK
1284 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1285 # define TV_VSCALE_IP_FRAC_SHIFT 0
1287 #define TV_CC_CONTROL 0x68090
1288 # define TV_CC_ENABLE (1 << 31)
1290 * Specifies which field to send the CC data in.
1292 * CC data is usually sent in field 0.
1294 # define TV_CC_FID_MASK (1 << 27)
1295 # define TV_CC_FID_SHIFT 27
1296 /** Sets the horizontal position of the CC data. Usually 135. */
1297 # define TV_CC_HOFF_MASK 0x03ff0000
1298 # define TV_CC_HOFF_SHIFT 16
1299 /** Sets the vertical position of the CC data. Usually 21 */
1300 # define TV_CC_LINE_MASK 0x0000003f
1301 # define TV_CC_LINE_SHIFT 0
1303 #define TV_CC_DATA 0x68094
1304 # define TV_CC_RDY (1 << 31)
1305 /** Second word of CC data to be transmitted. */
1306 # define TV_CC_DATA_2_MASK 0x007f0000
1307 # define TV_CC_DATA_2_SHIFT 16
1308 /** First word of CC data to be transmitted. */
1309 # define TV_CC_DATA_1_MASK 0x0000007f
1310 # define TV_CC_DATA_1_SHIFT 0
1312 #define TV_H_LUMA_0 0x68100
1313 #define TV_H_LUMA_59 0x681ec
1314 #define TV_H_CHROMA_0 0x68200
1315 #define TV_H_CHROMA_59 0x682ec
1316 #define TV_V_LUMA_0 0x68300
1317 #define TV_V_LUMA_42 0x683a8
1318 #define TV_V_CHROMA_0 0x68400
1319 #define TV_V_CHROMA_42 0x684a8
1321 /* Display & cursor control */
1324 #define PIPEADSL 0x70000
1325 #define PIPEACONF 0x70008
1326 #define PIPEACONF_ENABLE (1<<31)
1327 #define PIPEACONF_DISABLE 0
1328 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1329 #define I965_PIPECONF_ACTIVE (1<<30)
1330 #define PIPEACONF_SINGLE_WIDE 0
1331 #define PIPEACONF_PIPE_UNLOCKED 0
1332 #define PIPEACONF_PIPE_LOCKED (1<<25)
1333 #define PIPEACONF_PALETTE 0
1334 #define PIPEACONF_GAMMA (1<<24)
1335 #define PIPECONF_FORCE_BORDER (1<<25)
1336 #define PIPECONF_PROGRESSIVE (0 << 21)
1337 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1338 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1339 #define PIPEASTAT 0x70024
1340 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1341 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1342 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
1343 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1344 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1345 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1346 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1347 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1348 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1349 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1350 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1351 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1352 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1353 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1354 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1355 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1356 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1357 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1358 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1359 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1360 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1361 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
1362 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1363 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1364 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1365 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1366 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1367 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1368 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1370 #define DSPARB 0x70030
1371 #define DSPARB_CSTART_MASK (0x7f << 7)
1372 #define DSPARB_CSTART_SHIFT 7
1373 #define DSPARB_BSTART_MASK (0x7f)
1374 #define DSPARB_BSTART_SHIFT 0
1376 * The two pipe frame counter registers are not synchronized, so
1377 * reading a stable value is somewhat tricky. The following code
1381 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1382 * PIPE_FRAME_HIGH_SHIFT;
1383 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1384 * PIPE_FRAME_LOW_SHIFT);
1385 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1386 * PIPE_FRAME_HIGH_SHIFT);
1387 * } while (high1 != high2);
1388 * frame = (high1 << 8) | low1;
1390 #define PIPEAFRAMEHIGH 0x70040
1391 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
1392 #define PIPE_FRAME_HIGH_SHIFT 0
1393 #define PIPEAFRAMEPIXEL 0x70044
1394 #define PIPE_FRAME_LOW_MASK 0xff000000
1395 #define PIPE_FRAME_LOW_SHIFT 24
1396 #define PIPE_PIXEL_MASK 0x00ffffff
1397 #define PIPE_PIXEL_SHIFT 0
1398 /* GM45+ just has to be different */
1399 #define PIPEA_FRMCOUNT_GM45 0x70040
1400 #define PIPEA_FLIPCOUNT_GM45 0x70044
1402 /* Cursor A & B regs */
1403 #define CURACNTR 0x70080
1404 #define CURSOR_MODE_DISABLE 0x00
1405 #define CURSOR_MODE_64_32B_AX 0x07
1406 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
1407 #define MCURSOR_GAMMA_ENABLE (1 << 26)
1408 #define CURABASE 0x70084
1409 #define CURAPOS 0x70088
1410 #define CURSOR_POS_MASK 0x007FF
1411 #define CURSOR_POS_SIGN 0x8000
1412 #define CURSOR_X_SHIFT 0
1413 #define CURSOR_Y_SHIFT 16
1414 #define CURBCNTR 0x700c0
1415 #define CURBBASE 0x700c4
1416 #define CURBPOS 0x700c8
1418 /* Display A control */
1419 #define DSPACNTR 0x70180
1420 #define DISPLAY_PLANE_ENABLE (1<<31)
1421 #define DISPLAY_PLANE_DISABLE 0
1422 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1423 #define DISPPLANE_GAMMA_DISABLE 0
1424 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1425 #define DISPPLANE_8BPP (0x2<<26)
1426 #define DISPPLANE_15_16BPP (0x4<<26)
1427 #define DISPPLANE_16BPP (0x5<<26)
1428 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1429 #define DISPPLANE_32BPP (0x7<<26)
1430 #define DISPPLANE_STEREO_ENABLE (1<<25)
1431 #define DISPPLANE_STEREO_DISABLE 0
1432 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1433 #define DISPPLANE_SEL_PIPE_A 0
1434 #define DISPPLANE_SEL_PIPE_B (1<<24)
1435 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1436 #define DISPPLANE_SRC_KEY_DISABLE 0
1437 #define DISPPLANE_LINE_DOUBLE (1<<20)
1438 #define DISPPLANE_NO_LINE_DOUBLE 0
1439 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1440 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1441 #define DSPAADDR 0x70184
1442 #define DSPASTRIDE 0x70188
1443 #define DSPAPOS 0x7018C /* reserved */
1444 #define DSPASIZE 0x70190
1445 #define DSPASURF 0x7019C /* 965+ only */
1446 #define DSPATILEOFF 0x701A4 /* 965+ only */
1449 #define SWF00 0x71410
1450 #define SWF01 0x71414
1451 #define SWF02 0x71418
1452 #define SWF03 0x7141c
1453 #define SWF04 0x71420
1454 #define SWF05 0x71424
1455 #define SWF06 0x71428
1456 #define SWF10 0x70410
1457 #define SWF11 0x70414
1458 #define SWF14 0x71420
1459 #define SWF30 0x72414
1460 #define SWF31 0x72418
1461 #define SWF32 0x7241c
1464 #define PIPEBDSL 0x71000
1465 #define PIPEBCONF 0x71008
1466 #define PIPEBSTAT 0x71024
1467 #define PIPEBFRAMEHIGH 0x71040
1468 #define PIPEBFRAMEPIXEL 0x71044
1469 #define PIPEB_FRMCOUNT_GM45 0x71040
1470 #define PIPEB_FLIPCOUNT_GM45 0x71044
1473 /* Display B control */
1474 #define DSPBCNTR 0x71180
1475 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1476 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1477 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
1478 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1479 #define DSPBADDR 0x71184
1480 #define DSPBSTRIDE 0x71188
1481 #define DSPBPOS 0x7118C
1482 #define DSPBSIZE 0x71190
1483 #define DSPBSURF 0x7119C
1484 #define DSPBTILEOFF 0x711A4
1487 #define VGACNTRL 0x71400
1488 # define VGA_DISP_DISABLE (1 << 31)
1489 # define VGA_2X_MODE (1 << 30)
1490 # define VGA_PIPE_B_SELECT (1 << 29)
1492 #endif /* _I915_REG_H_ */
projects / linux-2.6-omap-h63xx.git / blob