drivers/gpu/drm/radeon/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #include "radeon_microcode.h"
  40
  41 #define RADEON_FIFO_DEBUG       0
  42
  43 static int radeon_do_cleanup_cp(struct drm_device * dev);
  44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  45
  46 static u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  47 {
  48         u32 val;
  49
  50         if (dev_priv->flags & RADEON_IS_AGP) {
  51                 val = DRM_READ32(dev_priv->ring_rptr, off);
  52         } else {
  53                 val = *(((volatile u32 *)
  54                          dev_priv->ring_rptr->handle) +
  55                         (off / sizeof(u32)));
  56                 val = le32_to_cpu(val);
  57         }
  58         return val;
  59 }
  60
  61 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  62 {
  63         if (dev_priv->writeback_works)
  64                 return radeon_read_ring_rptr(dev_priv, 0);
  65         else
  66                 return RADEON_READ(RADEON_CP_RB_RPTR);
  67 }
  68
  69 static void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  70 {
  71         if (dev_priv->flags & RADEON_IS_AGP)
  72                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  73         else
  74                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  75                   (off / sizeof(u32))) = cpu_to_le32(val);
  76 }
  77
  78 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  79 {
  80         radeon_write_ring_rptr(dev_priv, 0, val);
  81 }
  82
  83 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
  84 {
  85         if (dev_priv->writeback_works)
  86                 return radeon_read_ring_rptr(dev_priv,
  87                                              RADEON_SCRATCHOFF(index));
  88         else
  89                 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
  90 }
  91
  92 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
  93 {
  94         u32 ret;
  95
  96         if (addr < 0x10000)
  97                 ret = DRM_READ32(dev_priv->mmio, addr);
  98         else {
  99                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
 100                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
 101         }
 102
 103         return ret;
 104 }
 105
 106 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 107 {
 108         u32 ret;
 109         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 110         ret = RADEON_READ(R520_MC_IND_DATA);
 111         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 112         return ret;
 113 }
 114
 115 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 116 {
 117         u32 ret;
 118         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 119         ret = RADEON_READ(RS480_NB_MC_DATA);
 120         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 121         return ret;
 122 }
 123
 124 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 125 {
 126         u32 ret;
 127         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 128         ret = RADEON_READ(RS690_MC_DATA);
 129         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 130         return ret;
 131 }
 132
 133 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 134 {
 135         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 136             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 137                 return RS690_READ_MCIND(dev_priv, addr);
 138         else
 139                 return RS480_READ_MCIND(dev_priv, addr);
 140 }
 141
 142 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 143 {
 144
 145         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 146                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 147         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 148                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 149                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 150         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 151                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 152         else
 153                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 154 }
 155
 156 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 157 {
 158         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 159                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 160         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 161                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 162                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 163         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 164                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 165         else
 166                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 167 }
 168
 169 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 170 {
 171         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 172                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 173         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 174                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 175                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 176         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 177                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 178         else
 179                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 180 }
 181
 182 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 183 {
 184         u32 agp_base_hi = upper_32_bits(agp_base);
 185         u32 agp_base_lo = agp_base & 0xffffffff;
 186
 187         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 188                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 189                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 190         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 191                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 192                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 193                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 194         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 195                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 196                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 197         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 198                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 199                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 200                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 201         } else {
 202                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 203                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 204                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 205         }
 206 }
 207
 208 static void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 209 {
 210         u32 tmp;
 211         /* Turn on bus mastering */
 212         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 213             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 214                 /* rs600/rs690/rs740 */
 215                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 216                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 217         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 218                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 219                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 220                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 221                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 222                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 223                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 224         } /* PCIE cards appears to not need this */
 225 }
 226
 227 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 228 {
 229         drm_radeon_private_t *dev_priv = dev->dev_private;
 230
 231         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 232         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 233 }
 234
 235 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 236 {
 237         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 238         return RADEON_READ(RADEON_PCIE_DATA);
 239 }
 240
 241 #if RADEON_FIFO_DEBUG
 242 static void radeon_status(drm_radeon_private_t * dev_priv)
 243 {
 244         printk("%s:\n", __func__);
 245         printk("RBBM_STATUS = 0x%08x\n",
 246                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 247         printk("CP_RB_RTPR = 0x%08x\n",
 248                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 249         printk("CP_RB_WTPR = 0x%08x\n",
 250                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 251         printk("AIC_CNTL = 0x%08x\n",
 252                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 253         printk("AIC_STAT = 0x%08x\n",
 254                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 255         printk("AIC_PT_BASE = 0x%08x\n",
 256                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 257         printk("TLB_ADDR = 0x%08x\n",
 258                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 259         printk("TLB_DATA = 0x%08x\n",
 260                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 261 }
 262 #endif
 263
 264 /* ================================================================
 265  * Engine, FIFO control
 266  */
 267
 268 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 269 {
 270         u32 tmp;
 271         int i;
 272
 273         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 274
 275         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 276                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 277                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 278                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 279
 280                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 281                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 282                               & RADEON_RB3D_DC_BUSY)) {
 283                                 return 0;
 284                         }
 285                         DRM_UDELAY(1);
 286                 }
 287         } else {
 288                 /* don't flush or purge cache here or lockup */
 289                 return 0;
 290         }
 291
 292 #if RADEON_FIFO_DEBUG
 293         DRM_ERROR("failed!\n");
 294         radeon_status(dev_priv);
 295 #endif
 296         return -EBUSY;
 297 }
 298
 299 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 300 {
 301         int i;
 302
 303         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 304
 305         for (i = 0; i < dev_priv->usec_timeout; i++) {
 306                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 307                              & RADEON_RBBM_FIFOCNT_MASK);
 308                 if (slots >= entries)
 309                         return 0;
 310                 DRM_UDELAY(1);
 311         }
 312         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 313                  RADEON_READ(RADEON_RBBM_STATUS),
 314                  RADEON_READ(R300_VAP_CNTL_STATUS));
 315
 316 #if RADEON_FIFO_DEBUG
 317         DRM_ERROR("failed!\n");
 318         radeon_status(dev_priv);
 319 #endif
 320         return -EBUSY;
 321 }
 322
 323 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 324 {
 325         int i, ret;
 326
 327         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 328
 329         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 330         if (ret)
 331                 return ret;
 332
 333         for (i = 0; i < dev_priv->usec_timeout; i++) {
 334                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 335                       & RADEON_RBBM_ACTIVE)) {
 336                         radeon_do_pixcache_flush(dev_priv);
 337                         return 0;
 338                 }
 339                 DRM_UDELAY(1);
 340         }
 341         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 342                  RADEON_READ(RADEON_RBBM_STATUS),
 343                  RADEON_READ(R300_VAP_CNTL_STATUS));
 344
 345 #if RADEON_FIFO_DEBUG
 346         DRM_ERROR("failed!\n");
 347         radeon_status(dev_priv);
 348 #endif
 349         return -EBUSY;
 350 }
 351
 352 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 353 {
 354         uint32_t gb_tile_config, gb_pipe_sel = 0;
 355
 356         /* RS4xx/RS6xx/R4xx/R5xx */
 357         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 358                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 359                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 360         } else {
 361                 /* R3xx */
 362                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 363                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 364                         dev_priv->num_gb_pipes = 2;
 365                 } else {
 366                         /* R3Vxx */
 367                         dev_priv->num_gb_pipes = 1;
 368                 }
 369         }
 370         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 371
 372         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 373
 374         switch (dev_priv->num_gb_pipes) {
 375         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 376         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 377         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 378         default:
 379         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 380         }
 381
 382         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 383                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 384                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 385         }
 386         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 387         radeon_do_wait_for_idle(dev_priv);
 388         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 389         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 390                                                R300_DC_AUTOFLUSH_ENABLE |
 391                                                R300_DC_DC_DISABLE_IGNORE_PE));
 392
 393
 394 }
 395
 396 /* ================================================================
 397  * CP control, initialization
 398  */
 399
 400 /* Load the microcode for the CP */
 401 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 402 {
 403         int i;
 404         DRM_DEBUG("\n");
 405
 406         radeon_do_wait_for_idle(dev_priv);
 407
 408         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 409         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 410             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 411             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 412             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 413             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 414                 DRM_INFO("Loading R100 Microcode\n");
 415                 for (i = 0; i < 256; i++) {
 416                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 417                                      R100_cp_microcode[i][1]);
 418                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 419                                      R100_cp_microcode[i][0]);
 420                 }
 421         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 422                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 423                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 424                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 425                 DRM_INFO("Loading R200 Microcode\n");
 426                 for (i = 0; i < 256; i++) {
 427                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 428                                      R200_cp_microcode[i][1]);
 429                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 430                                      R200_cp_microcode[i][0]);
 431                 }
 432         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 433                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 434                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 435                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 436                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 437                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 438                 DRM_INFO("Loading R300 Microcode\n");
 439                 for (i = 0; i < 256; i++) {
 440                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 441                                      R300_cp_microcode[i][1]);
 442                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 443                                      R300_cp_microcode[i][0]);
 444                 }
 445         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 446                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 447                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 448                 DRM_INFO("Loading R400 Microcode\n");
 449                 for (i = 0; i < 256; i++) {
 450                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 451                                      R420_cp_microcode[i][1]);
 452                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 453                                      R420_cp_microcode[i][0]);
 454                 }
 455         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 456                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 457                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 458                 for (i = 0; i < 256; i++) {
 459                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 460                                      RS690_cp_microcode[i][1]);
 461                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 462                                      RS690_cp_microcode[i][0]);
 463                 }
 464         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 465                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 466                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 467                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 468                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 469                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 470                 DRM_INFO("Loading R500 Microcode\n");
 471                 for (i = 0; i < 256; i++) {
 472                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 473                                      R520_cp_microcode[i][1]);
 474                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 475                                      R520_cp_microcode[i][0]);
 476                 }
 477         }
 478 }
 479
 480 /* Flush any pending commands to the CP.  This should only be used just
 481  * prior to a wait for idle, as it informs the engine that the command
 482  * stream is ending.
 483  */
 484 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 485 {
 486         DRM_DEBUG("\n");
 487 #if 0
 488         u32 tmp;
 489
 490         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 491         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 492 #endif
 493 }
 494
 495 /* Wait for the CP to go idle.
 496  */
 497 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 498 {
 499         RING_LOCALS;
 500         DRM_DEBUG("\n");
 501
 502         BEGIN_RING(6);
 503
 504         RADEON_PURGE_CACHE();
 505         RADEON_PURGE_ZCACHE();
 506         RADEON_WAIT_UNTIL_IDLE();
 507
 508         ADVANCE_RING();
 509         COMMIT_RING();
 510
 511         return radeon_do_wait_for_idle(dev_priv);
 512 }
 513
 514 /* Start the Command Processor.
 515  */
 516 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 517 {
 518         RING_LOCALS;
 519         DRM_DEBUG("\n");
 520
 521         radeon_do_wait_for_idle(dev_priv);
 522
 523         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 524
 525         dev_priv->cp_running = 1;
 526
 527         BEGIN_RING(8);
 528         /* isync can only be written through cp on r5xx write it here */
 529         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 530         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 531                  RADEON_ISYNC_ANY3D_IDLE2D |
 532                  RADEON_ISYNC_WAIT_IDLEGUI |
 533                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 534         RADEON_PURGE_CACHE();
 535         RADEON_PURGE_ZCACHE();
 536         RADEON_WAIT_UNTIL_IDLE();
 537         ADVANCE_RING();
 538         COMMIT_RING();
 539
 540         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 541 }
 542
 543 /* Reset the Command Processor.  This will not flush any pending
 544  * commands, so you must wait for the CP command stream to complete
 545  * before calling this routine.
 546  */
 547 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 548 {
 549         u32 cur_read_ptr;
 550         DRM_DEBUG("\n");
 551
 552         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 553         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 554         SET_RING_HEAD(dev_priv, cur_read_ptr);
 555         dev_priv->ring.tail = cur_read_ptr;
 556 }
 557
 558 /* Stop the Command Processor.  This will not flush any pending
 559  * commands, so you must flush the command stream and wait for the CP
 560  * to go idle before calling this routine.
 561  */
 562 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 563 {
 564         DRM_DEBUG("\n");
 565
 566         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 567
 568         dev_priv->cp_running = 0;
 569 }
 570
 571 /* Reset the engine.  This will stop the CP if it is running.
 572  */
 573 static int radeon_do_engine_reset(struct drm_device * dev)
 574 {
 575         drm_radeon_private_t *dev_priv = dev->dev_private;
 576         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 577         DRM_DEBUG("\n");
 578
 579         radeon_do_pixcache_flush(dev_priv);
 580
 581         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 582                 /* may need something similar for newer chips */
 583                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 584                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 585
 586                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 587                                                     RADEON_FORCEON_MCLKA |
 588                                                     RADEON_FORCEON_MCLKB |
 589                                                     RADEON_FORCEON_YCLKA |
 590                                                     RADEON_FORCEON_YCLKB |
 591                                                     RADEON_FORCEON_MC |
 592                                                     RADEON_FORCEON_AIC));
 593         }
 594
 595         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 596
 597         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 598                                               RADEON_SOFT_RESET_CP |
 599                                               RADEON_SOFT_RESET_HI |
 600                                               RADEON_SOFT_RESET_SE |
 601                                               RADEON_SOFT_RESET_RE |
 602                                               RADEON_SOFT_RESET_PP |
 603                                               RADEON_SOFT_RESET_E2 |
 604                                               RADEON_SOFT_RESET_RB));
 605         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 606         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 607                                               ~(RADEON_SOFT_RESET_CP |
 608                                                 RADEON_SOFT_RESET_HI |
 609                                                 RADEON_SOFT_RESET_SE |
 610                                                 RADEON_SOFT_RESET_RE |
 611                                                 RADEON_SOFT_RESET_PP |
 612                                                 RADEON_SOFT_RESET_E2 |
 613                                                 RADEON_SOFT_RESET_RB)));
 614         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 615
 616         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 617                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 618                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 619                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 620         }
 621
 622         /* setup the raster pipes */
 623         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 624             radeon_init_pipes(dev_priv);
 625
 626         /* Reset the CP ring */
 627         radeon_do_cp_reset(dev_priv);
 628
 629         /* The CP is no longer running after an engine reset */
 630         dev_priv->cp_running = 0;
 631
 632         /* Reset any pending vertex, indirect buffers */
 633         radeon_freelist_reset(dev);
 634
 635         return 0;
 636 }
 637
 638 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 639                                        drm_radeon_private_t *dev_priv,
 640                                        struct drm_file *file_priv)
 641 {
 642         struct drm_radeon_master_private *master_priv;
 643         u32 ring_start, cur_read_ptr;
 644
 645         /* Initialize the memory controller. With new memory map, the fb location
 646          * is not changed, it should have been properly initialized already. Part
 647          * of the problem is that the code below is bogus, assuming the GART is
 648          * always appended to the fb which is not necessarily the case
 649          */
 650         if (!dev_priv->new_memmap)
 651                 radeon_write_fb_location(dev_priv,
 652                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 653                              | (dev_priv->fb_location >> 16));
 654
 655 #if __OS_HAS_AGP
 656         if (dev_priv->flags & RADEON_IS_AGP) {
 657                 radeon_write_agp_base(dev_priv, dev->agp->base);
 658
 659                 radeon_write_agp_location(dev_priv,
 660                              (((dev_priv->gart_vm_start - 1 +
 661                                 dev_priv->gart_size) & 0xffff0000) |
 662                               (dev_priv->gart_vm_start >> 16)));
 663
 664                 ring_start = (dev_priv->cp_ring->offset
 665                               - dev->agp->base
 666                               + dev_priv->gart_vm_start);
 667         } else
 668 #endif
 669                 ring_start = (dev_priv->cp_ring->offset
 670                               - (unsigned long)dev->sg->virtual
 671                               + dev_priv->gart_vm_start);
 672
 673         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 674
 675         /* Set the write pointer delay */
 676         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 677
 678         /* Initialize the ring buffer's read and write pointers */
 679         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 680         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 681         SET_RING_HEAD(dev_priv, cur_read_ptr);
 682         dev_priv->ring.tail = cur_read_ptr;
 683
 684 #if __OS_HAS_AGP
 685         if (dev_priv->flags & RADEON_IS_AGP) {
 686                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 687                              dev_priv->ring_rptr->offset
 688                              - dev->agp->base + dev_priv->gart_vm_start);
 689         } else
 690 #endif
 691         {
 692                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 693                              dev_priv->ring_rptr->offset
 694                              - ((unsigned long) dev->sg->virtual)
 695                              + dev_priv->gart_vm_start);
 696         }
 697
 698         /* Set ring buffer size */
 699 #ifdef __BIG_ENDIAN
 700         RADEON_WRITE(RADEON_CP_RB_CNTL,
 701                      RADEON_BUF_SWAP_32BIT |
 702                      (dev_priv->ring.fetch_size_l2ow << 18) |
 703                      (dev_priv->ring.rptr_update_l2qw << 8) |
 704                      dev_priv->ring.size_l2qw);
 705 #else
 706         RADEON_WRITE(RADEON_CP_RB_CNTL,
 707                      (dev_priv->ring.fetch_size_l2ow << 18) |
 708                      (dev_priv->ring.rptr_update_l2qw << 8) |
 709                      dev_priv->ring.size_l2qw);
 710 #endif
 711
 712
 713         /* Initialize the scratch register pointer.  This will cause
 714          * the scratch register values to be written out to memory
 715          * whenever they are updated.
 716          *
 717          * We simply put this behind the ring read pointer, this works
 718          * with PCI GART as well as (whatever kind of) AGP GART
 719          */
 720         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 721                      + RADEON_SCRATCH_REG_OFFSET);
 722
 723         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 724
 725         radeon_enable_bm(dev_priv);
 726
 727         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 728         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 729
 730         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 731         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 732
 733         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 734         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 735
 736         /* reset sarea copies of these */
 737         master_priv = file_priv->master->driver_priv;
 738         if (master_priv->sarea_priv) {
 739                 master_priv->sarea_priv->last_frame = 0;
 740                 master_priv->sarea_priv->last_dispatch = 0;
 741                 master_priv->sarea_priv->last_clear = 0;
 742         }
 743
 744         radeon_do_wait_for_idle(dev_priv);
 745
 746         /* Sync everything up */
 747         RADEON_WRITE(RADEON_ISYNC_CNTL,
 748                      (RADEON_ISYNC_ANY2D_IDLE3D |
 749                       RADEON_ISYNC_ANY3D_IDLE2D |
 750                       RADEON_ISYNC_WAIT_IDLEGUI |
 751                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 752
 753 }
 754
 755 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 756 {
 757         u32 tmp;
 758
 759         /* Start with assuming that writeback doesn't work */
 760         dev_priv->writeback_works = 0;
 761
 762         /* Writeback doesn't seem to work everywhere, test it here and possibly
 763          * enable it if it appears to work
 764          */
 765         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 766
 767         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 768
 769         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 770                 u32 val;
 771
 772                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 773                 if (val == 0xdeadbeef)
 774                         break;
 775                 DRM_UDELAY(1);
 776         }
 777
 778         if (tmp < dev_priv->usec_timeout) {
 779                 dev_priv->writeback_works = 1;
 780                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 781         } else {
 782                 dev_priv->writeback_works = 0;
 783                 DRM_INFO("writeback test failed\n");
 784         }
 785         if (radeon_no_wb == 1) {
 786                 dev_priv->writeback_works = 0;
 787                 DRM_INFO("writeback forced off\n");
 788         }
 789
 790         if (!dev_priv->writeback_works) {
 791                 /* Disable writeback to avoid unnecessary bus master transfer */
 792                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 793                              RADEON_RB_NO_UPDATE);
 794                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 795         }
 796 }
 797
 798 /* Enable or disable IGP GART on the chip */
 799 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 800 {
 801         u32 temp;
 802
 803         if (on) {
 804                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 805                           dev_priv->gart_vm_start,
 806                           (long)dev_priv->gart_info.bus_addr,
 807                           dev_priv->gart_size);
 808
 809                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 810                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 811                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 812                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 813                                                              RS690_BLOCK_GFX_D3_EN));
 814                 else
 815                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 816
 817                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 818                                                                RS480_VA_SIZE_32MB));
 819
 820                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 821                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 822                                                         RS480_TLB_ENABLE |
 823                                                         RS480_GTW_LAC_EN |
 824                                                         RS480_1LEVEL_GART));
 825
 826                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 827                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 828                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 829
 830                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 831                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 832                                                       RS480_REQ_TYPE_SNOOP_DIS));
 833
 834                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 835
 836                 dev_priv->gart_size = 32*1024*1024;
 837                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 838                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 839
 840                 radeon_write_agp_location(dev_priv, temp);
 841
 842                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 843                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 844                                                                RS480_VA_SIZE_32MB));
 845
 846                 do {
 847                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 848                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 849                                 break;
 850                         DRM_UDELAY(1);
 851                 } while (1);
 852
 853                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 854                                 RS480_GART_CACHE_INVALIDATE);
 855
 856                 do {
 857                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 858                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 859                                 break;
 860                         DRM_UDELAY(1);
 861                 } while (1);
 862
 863                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 864         } else {
 865                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 866         }
 867 }
 868
 869 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 870 {
 871         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 872         if (on) {
 873
 874                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 875                           dev_priv->gart_vm_start,
 876                           (long)dev_priv->gart_info.bus_addr,
 877                           dev_priv->gart_size);
 878                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 879                                   dev_priv->gart_vm_start);
 880                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 881                                   dev_priv->gart_info.bus_addr);
 882                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 883                                   dev_priv->gart_vm_start);
 884                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 885                                   dev_priv->gart_vm_start +
 886                                   dev_priv->gart_size - 1);
 887
 888                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 889
 890                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 891                                   RADEON_PCIE_TX_GART_EN);
 892         } else {
 893                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 894                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 895         }
 896 }
 897
 898 /* Enable or disable PCI GART on the chip */
 899 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 900 {
 901         u32 tmp;
 902
 903         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 904             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
 905             (dev_priv->flags & RADEON_IS_IGPGART)) {
 906                 radeon_set_igpgart(dev_priv, on);
 907                 return;
 908         }
 909
 910         if (dev_priv->flags & RADEON_IS_PCIE) {
 911                 radeon_set_pciegart(dev_priv, on);
 912                 return;
 913         }
 914
 915         tmp = RADEON_READ(RADEON_AIC_CNTL);
 916
 917         if (on) {
 918                 RADEON_WRITE(RADEON_AIC_CNTL,
 919                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 920
 921                 /* set PCI GART page-table base address
 922                  */
 923                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 924
 925                 /* set address range for PCI address translate
 926                  */
 927                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 928                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 929                              + dev_priv->gart_size - 1);
 930
 931                 /* Turn off AGP aperture -- is this required for PCI GART?
 932                  */
 933                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 934                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 935         } else {
 936                 RADEON_WRITE(RADEON_AIC_CNTL,
 937                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 938         }
 939 }
 940
 941 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
 942 {
 943         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 944         struct radeon_virt_surface *vp;
 945         int i;
 946
 947         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
 948                 if (!dev_priv->virt_surfaces[i].file_priv ||
 949                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
 950                         break;
 951         }
 952         if (i >= 2 * RADEON_MAX_SURFACES)
 953                 return -ENOMEM;
 954         vp = &dev_priv->virt_surfaces[i];
 955
 956         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
 957                 struct radeon_surface *sp = &dev_priv->surfaces[i];
 958                 if (sp->refcount)
 959                         continue;
 960
 961                 vp->surface_index = i;
 962                 vp->lower = gart_info->bus_addr;
 963                 vp->upper = vp->lower + gart_info->table_size;
 964                 vp->flags = 0;
 965                 vp->file_priv = PCIGART_FILE_PRIV;
 966
 967                 sp->refcount = 1;
 968                 sp->lower = vp->lower;
 969                 sp->upper = vp->upper;
 970                 sp->flags = 0;
 971
 972                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
 973                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
 974                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
 975                 return 0;
 976         }
 977
 978         return -ENOMEM;
 979 }
 980
 981 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 982                              struct drm_file *file_priv)
 983 {
 984         drm_radeon_private_t *dev_priv = dev->dev_private;
 985         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
 986
 987         DRM_DEBUG("\n");
 988
 989         /* if we require new memory map but we don't have it fail */
 990         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 991                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 992                 radeon_do_cleanup_cp(dev);
 993                 return -EINVAL;
 994         }
 995
 996         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
 997                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 998                 dev_priv->flags &= ~RADEON_IS_AGP;
 999         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1000                    && !init->is_pci) {
1001                 DRM_DEBUG("Restoring AGP flag\n");
1002                 dev_priv->flags |= RADEON_IS_AGP;
1003         }
1004
1005         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1006                 DRM_ERROR("PCI GART memory not allocated!\n");
1007                 radeon_do_cleanup_cp(dev);
1008                 return -EINVAL;
1009         }
1010
1011         dev_priv->usec_timeout = init->usec_timeout;
1012         if (dev_priv->usec_timeout < 1 ||
1013             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1014                 DRM_DEBUG("TIMEOUT problem!\n");
1015                 radeon_do_cleanup_cp(dev);
1016                 return -EINVAL;
1017         }
1018
1019         /* Enable vblank on CRTC1 for older X servers
1020          */
1021         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1022
1023         switch(init->func) {
1024         case RADEON_INIT_R200_CP:
1025                 dev_priv->microcode_version = UCODE_R200;
1026                 break;
1027         case RADEON_INIT_R300_CP:
1028                 dev_priv->microcode_version = UCODE_R300;
1029                 break;
1030         default:
1031                 dev_priv->microcode_version = UCODE_R100;
1032         }
1033
1034         dev_priv->do_boxes = 0;
1035         dev_priv->cp_mode = init->cp_mode;
1036
1037         /* We don't support anything other than bus-mastering ring mode,
1038          * but the ring can be in either AGP or PCI space for the ring
1039          * read pointer.
1040          */
1041         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1042             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1043                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1044                 radeon_do_cleanup_cp(dev);
1045                 return -EINVAL;
1046         }
1047
1048         switch (init->fb_bpp) {
1049         case 16:
1050                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1051                 break;
1052         case 32:
1053         default:
1054                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1055                 break;
1056         }
1057         dev_priv->front_offset = init->front_offset;
1058         dev_priv->front_pitch = init->front_pitch;
1059         dev_priv->back_offset = init->back_offset;
1060         dev_priv->back_pitch = init->back_pitch;
1061
1062         switch (init->depth_bpp) {
1063         case 16:
1064                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1065                 break;
1066         case 32:
1067         default:
1068                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1069                 break;
1070         }
1071         dev_priv->depth_offset = init->depth_offset;
1072         dev_priv->depth_pitch = init->depth_pitch;
1073
1074         /* Hardware state for depth clears.  Remove this if/when we no
1075          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1076          * all values to prevent unwanted 3D state from slipping through
1077          * and screwing with the clear operation.
1078          */
1079         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1080                                            (dev_priv->color_fmt << 10) |
1081                                            (dev_priv->microcode_version ==
1082                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1083
1084         dev_priv->depth_clear.rb3d_zstencilcntl =
1085             (dev_priv->depth_fmt |
1086              RADEON_Z_TEST_ALWAYS |
1087              RADEON_STENCIL_TEST_ALWAYS |
1088              RADEON_STENCIL_S_FAIL_REPLACE |
1089              RADEON_STENCIL_ZPASS_REPLACE |
1090              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1091
1092         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1093                                          RADEON_BFACE_SOLID |
1094                                          RADEON_FFACE_SOLID |
1095                                          RADEON_FLAT_SHADE_VTX_LAST |
1096                                          RADEON_DIFFUSE_SHADE_FLAT |
1097                                          RADEON_ALPHA_SHADE_FLAT |
1098                                          RADEON_SPECULAR_SHADE_FLAT |
1099                                          RADEON_FOG_SHADE_FLAT |
1100                                          RADEON_VTX_PIX_CENTER_OGL |
1101                                          RADEON_ROUND_MODE_TRUNC |
1102                                          RADEON_ROUND_PREC_8TH_PIX);
1103
1104
1105         dev_priv->ring_offset = init->ring_offset;
1106         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1107         dev_priv->buffers_offset = init->buffers_offset;
1108         dev_priv->gart_textures_offset = init->gart_textures_offset;
1109
1110         master_priv->sarea = drm_getsarea(dev);
1111         if (!master_priv->sarea) {
1112                 DRM_ERROR("could not find sarea!\n");
1113                 radeon_do_cleanup_cp(dev);
1114                 return -EINVAL;
1115         }
1116
1117         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1118         if (!dev_priv->cp_ring) {
1119                 DRM_ERROR("could not find cp ring region!\n");
1120                 radeon_do_cleanup_cp(dev);
1121                 return -EINVAL;
1122         }
1123         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1124         if (!dev_priv->ring_rptr) {
1125                 DRM_ERROR("could not find ring read pointer!\n");
1126                 radeon_do_cleanup_cp(dev);
1127                 return -EINVAL;
1128         }
1129         dev->agp_buffer_token = init->buffers_offset;
1130         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1131         if (!dev->agp_buffer_map) {
1132                 DRM_ERROR("could not find dma buffer region!\n");
1133                 radeon_do_cleanup_cp(dev);
1134                 return -EINVAL;
1135         }
1136
1137         if (init->gart_textures_offset) {
1138                 dev_priv->gart_textures =
1139                     drm_core_findmap(dev, init->gart_textures_offset);
1140                 if (!dev_priv->gart_textures) {
1141                         DRM_ERROR("could not find GART texture region!\n");
1142                         radeon_do_cleanup_cp(dev);
1143                         return -EINVAL;
1144                 }
1145         }
1146
1147 #if __OS_HAS_AGP
1148         if (dev_priv->flags & RADEON_IS_AGP) {
1149                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1150                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1151                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1152                 if (!dev_priv->cp_ring->handle ||
1153                     !dev_priv->ring_rptr->handle ||
1154                     !dev->agp_buffer_map->handle) {
1155                         DRM_ERROR("could not find ioremap agp regions!\n");
1156                         radeon_do_cleanup_cp(dev);
1157                         return -EINVAL;
1158                 }
1159         } else
1160 #endif
1161         {
1162                 dev_priv->cp_ring->handle =
1163                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1164                 dev_priv->ring_rptr->handle =
1165                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1166                 dev->agp_buffer_map->handle =
1167                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1168
1169                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1170                           dev_priv->cp_ring->handle);
1171                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1172                           dev_priv->ring_rptr->handle);
1173                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1174                           dev->agp_buffer_map->handle);
1175         }
1176
1177         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1178         dev_priv->fb_size =
1179                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1180                 - dev_priv->fb_location;
1181
1182         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1183                                         ((dev_priv->front_offset
1184                                           + dev_priv->fb_location) >> 10));
1185
1186         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1187                                        ((dev_priv->back_offset
1188                                          + dev_priv->fb_location) >> 10));
1189
1190         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1191                                         ((dev_priv->depth_offset
1192                                           + dev_priv->fb_location) >> 10));
1193
1194         dev_priv->gart_size = init->gart_size;
1195
1196         /* New let's set the memory map ... */
1197         if (dev_priv->new_memmap) {
1198                 u32 base = 0;
1199
1200                 DRM_INFO("Setting GART location based on new memory map\n");
1201
1202                 /* If using AGP, try to locate the AGP aperture at the same
1203                  * location in the card and on the bus, though we have to
1204                  * align it down.
1205                  */
1206 #if __OS_HAS_AGP
1207                 if (dev_priv->flags & RADEON_IS_AGP) {
1208                         base = dev->agp->base;
1209                         /* Check if valid */
1210                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1211                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1212                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1213                                          dev->agp->base);
1214                                 base = 0;
1215                         }
1216                 }
1217 #endif
1218                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1219                 if (base == 0) {
1220                         base = dev_priv->fb_location + dev_priv->fb_size;
1221                         if (base < dev_priv->fb_location ||
1222                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1223                                 base = dev_priv->fb_location
1224                                         - dev_priv->gart_size;
1225                 }
1226                 dev_priv->gart_vm_start = base & 0xffc00000u;
1227                 if (dev_priv->gart_vm_start != base)
1228                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1229                                  base, dev_priv->gart_vm_start);
1230         } else {
1231                 DRM_INFO("Setting GART location based on old memory map\n");
1232                 dev_priv->gart_vm_start = dev_priv->fb_location +
1233                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1234         }
1235
1236 #if __OS_HAS_AGP
1237         if (dev_priv->flags & RADEON_IS_AGP)
1238                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1239                                                  - dev->agp->base
1240                                                  + dev_priv->gart_vm_start);
1241         else
1242 #endif
1243                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1244                                         - (unsigned long)dev->sg->virtual
1245                                         + dev_priv->gart_vm_start);
1246
1247         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1248         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1249         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1250                   dev_priv->gart_buffers_offset);
1251
1252         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1253         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1254                               + init->ring_size / sizeof(u32));
1255         dev_priv->ring.size = init->ring_size;
1256         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1257
1258         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1259         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1260
1261         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1262         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1263         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1264
1265         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1266
1267 #if __OS_HAS_AGP
1268         if (dev_priv->flags & RADEON_IS_AGP) {
1269                 /* Turn off PCI GART */
1270                 radeon_set_pcigart(dev_priv, 0);
1271         } else
1272 #endif
1273         {
1274                 u32 sctrl;
1275                 int ret;
1276
1277                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1278                 /* if we have an offset set from userspace */
1279                 if (dev_priv->pcigart_offset_set) {
1280                         dev_priv->gart_info.bus_addr =
1281                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1282                         dev_priv->gart_info.mapping.offset =
1283                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1284                         dev_priv->gart_info.mapping.size =
1285                             dev_priv->gart_info.table_size;
1286
1287                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1288                         dev_priv->gart_info.addr =
1289                             dev_priv->gart_info.mapping.handle;
1290
1291                         if (dev_priv->flags & RADEON_IS_PCIE)
1292                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1293                         else
1294                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1295                         dev_priv->gart_info.gart_table_location =
1296                             DRM_ATI_GART_FB;
1297
1298                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1299                                   dev_priv->gart_info.addr,
1300                                   dev_priv->pcigart_offset);
1301                 } else {
1302                         if (dev_priv->flags & RADEON_IS_IGPGART)
1303                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1304                         else
1305                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1306                         dev_priv->gart_info.gart_table_location =
1307                             DRM_ATI_GART_MAIN;
1308                         dev_priv->gart_info.addr = NULL;
1309                         dev_priv->gart_info.bus_addr = 0;
1310                         if (dev_priv->flags & RADEON_IS_PCIE) {
1311                                 DRM_ERROR
1312                                     ("Cannot use PCI Express without GART in FB memory\n");
1313                                 radeon_do_cleanup_cp(dev);
1314                                 return -EINVAL;
1315                         }
1316                 }
1317
1318                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1319                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1320                 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1321                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1322
1323                 if (!ret) {
1324                         DRM_ERROR("failed to init PCI GART!\n");
1325                         radeon_do_cleanup_cp(dev);
1326                         return -ENOMEM;
1327                 }
1328
1329                 ret = radeon_setup_pcigart_surface(dev_priv);
1330                 if (ret) {
1331                         DRM_ERROR("failed to setup GART surface!\n");
1332                         drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1333                         radeon_do_cleanup_cp(dev);
1334                         return ret;
1335                 }
1336
1337                 /* Turn on PCI GART */
1338                 radeon_set_pcigart(dev_priv, 1);
1339         }
1340
1341         radeon_cp_load_microcode(dev_priv);
1342         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1343
1344         dev_priv->last_buf = 0;
1345
1346         radeon_do_engine_reset(dev);
1347         radeon_test_writeback(dev_priv);
1348
1349         return 0;
1350 }
1351
1352 static int radeon_do_cleanup_cp(struct drm_device * dev)
1353 {
1354         drm_radeon_private_t *dev_priv = dev->dev_private;
1355         DRM_DEBUG("\n");
1356
1357         /* Make sure interrupts are disabled here because the uninstall ioctl
1358          * may not have been called from userspace and after dev_private
1359          * is freed, it's too late.
1360          */
1361         if (dev->irq_enabled)
1362                 drm_irq_uninstall(dev);
1363
1364 #if __OS_HAS_AGP
1365         if (dev_priv->flags & RADEON_IS_AGP) {
1366                 if (dev_priv->cp_ring != NULL) {
1367                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1368                         dev_priv->cp_ring = NULL;
1369                 }
1370                 if (dev_priv->ring_rptr != NULL) {
1371                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1372                         dev_priv->ring_rptr = NULL;
1373                 }
1374                 if (dev->agp_buffer_map != NULL) {
1375                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1376                         dev->agp_buffer_map = NULL;
1377                 }
1378         } else
1379 #endif
1380         {
1381
1382                 if (dev_priv->gart_info.bus_addr) {
1383                         /* Turn off PCI GART */
1384                         radeon_set_pcigart(dev_priv, 0);
1385                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1386                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1387                 }
1388
1389                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1390                 {
1391                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1392                         dev_priv->gart_info.addr = 0;
1393                 }
1394         }
1395         /* only clear to the start of flags */
1396         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1397
1398         return 0;
1399 }
1400
1401 /* This code will reinit the Radeon CP hardware after a resume from disc.
1402  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1403  * here we make sure that all Radeon hardware initialisation is re-done without
1404  * affecting running applications.
1405  *
1406  * Charl P. Botha <http://cpbotha.net>
1407  */
1408 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1409 {
1410         drm_radeon_private_t *dev_priv = dev->dev_private;
1411
1412         if (!dev_priv) {
1413                 DRM_ERROR("Called with no initialization\n");
1414                 return -EINVAL;
1415         }
1416
1417         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1418
1419 #if __OS_HAS_AGP
1420         if (dev_priv->flags & RADEON_IS_AGP) {
1421                 /* Turn off PCI GART */
1422                 radeon_set_pcigart(dev_priv, 0);
1423         } else
1424 #endif
1425         {
1426                 /* Turn on PCI GART */
1427                 radeon_set_pcigart(dev_priv, 1);
1428         }
1429
1430         radeon_cp_load_microcode(dev_priv);
1431         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1432
1433         radeon_do_engine_reset(dev);
1434         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1435
1436         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1437
1438         return 0;
1439 }
1440
1441 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1442 {
1443         drm_radeon_init_t *init = data;
1444
1445         LOCK_TEST_WITH_RETURN(dev, file_priv);
1446
1447         if (init->func == RADEON_INIT_R300_CP)
1448                 r300_init_reg_flags(dev);
1449
1450         switch (init->func) {
1451         case RADEON_INIT_CP:
1452         case RADEON_INIT_R200_CP:
1453         case RADEON_INIT_R300_CP:
1454                 return radeon_do_init_cp(dev, init, file_priv);
1455         case RADEON_CLEANUP_CP:
1456                 return radeon_do_cleanup_cp(dev);
1457         }
1458
1459         return -EINVAL;
1460 }
1461
1462 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1463 {
1464         drm_radeon_private_t *dev_priv = dev->dev_private;
1465         DRM_DEBUG("\n");
1466
1467         LOCK_TEST_WITH_RETURN(dev, file_priv);
1468
1469         if (dev_priv->cp_running) {
1470                 DRM_DEBUG("while CP running\n");
1471                 return 0;
1472         }
1473         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1474                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1475                           dev_priv->cp_mode);
1476                 return 0;
1477         }
1478
1479         radeon_do_cp_start(dev_priv);
1480
1481         return 0;
1482 }
1483
1484 /* Stop the CP.  The engine must have been idled before calling this
1485  * routine.
1486  */
1487 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1488 {
1489         drm_radeon_private_t *dev_priv = dev->dev_private;
1490         drm_radeon_cp_stop_t *stop = data;
1491         int ret;
1492         DRM_DEBUG("\n");
1493
1494         LOCK_TEST_WITH_RETURN(dev, file_priv);
1495
1496         if (!dev_priv->cp_running)
1497                 return 0;
1498
1499         /* Flush any pending CP commands.  This ensures any outstanding
1500          * commands are exectuted by the engine before we turn it off.
1501          */
1502         if (stop->flush) {
1503                 radeon_do_cp_flush(dev_priv);
1504         }
1505
1506         /* If we fail to make the engine go idle, we return an error
1507          * code so that the DRM ioctl wrapper can try again.
1508          */
1509         if (stop->idle) {
1510                 ret = radeon_do_cp_idle(dev_priv);
1511                 if (ret)
1512                         return ret;
1513         }
1514
1515         /* Finally, we can turn off the CP.  If the engine isn't idle,
1516          * we will get some dropped triangles as they won't be fully
1517          * rendered before the CP is shut down.
1518          */
1519         radeon_do_cp_stop(dev_priv);
1520
1521         /* Reset the engine */
1522         radeon_do_engine_reset(dev);
1523
1524         return 0;
1525 }
1526
1527 void radeon_do_release(struct drm_device * dev)
1528 {
1529         drm_radeon_private_t *dev_priv = dev->dev_private;
1530         int i, ret;
1531
1532         if (dev_priv) {
1533                 if (dev_priv->cp_running) {
1534                         /* Stop the cp */
1535                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1536                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1537 #ifdef __linux__
1538                                 schedule();
1539 #else
1540                                 tsleep(&ret, PZERO, "rdnrel", 1);
1541 #endif
1542                         }
1543                         radeon_do_cp_stop(dev_priv);
1544                         radeon_do_engine_reset(dev);
1545                 }
1546
1547                 /* Disable *all* interrupts */
1548                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1549                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1550
1551                 if (dev_priv->mmio) {   /* remove all surfaces */
1552                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1553                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1554                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1555                                              16 * i, 0);
1556                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1557                                              16 * i, 0);
1558                         }
1559                 }
1560
1561                 /* Free memory heap structures */
1562                 radeon_mem_takedown(&(dev_priv->gart_heap));
1563                 radeon_mem_takedown(&(dev_priv->fb_heap));
1564
1565                 /* deallocate kernel resources */
1566                 radeon_do_cleanup_cp(dev);
1567         }
1568 }
1569
1570 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1571  */
1572 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1573 {
1574         drm_radeon_private_t *dev_priv = dev->dev_private;
1575         DRM_DEBUG("\n");
1576
1577         LOCK_TEST_WITH_RETURN(dev, file_priv);
1578
1579         if (!dev_priv) {
1580                 DRM_DEBUG("called before init done\n");
1581                 return -EINVAL;
1582         }
1583
1584         radeon_do_cp_reset(dev_priv);
1585
1586         /* The CP is no longer running after an engine reset */
1587         dev_priv->cp_running = 0;
1588
1589         return 0;
1590 }
1591
1592 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1593 {
1594         drm_radeon_private_t *dev_priv = dev->dev_private;
1595         DRM_DEBUG("\n");
1596
1597         LOCK_TEST_WITH_RETURN(dev, file_priv);
1598
1599         return radeon_do_cp_idle(dev_priv);
1600 }
1601
1602 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1603  */
1604 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1605 {
1606         return radeon_do_resume_cp(dev, file_priv);
1607 }
1608
1609 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1610 {
1611         DRM_DEBUG("\n");
1612
1613         LOCK_TEST_WITH_RETURN(dev, file_priv);
1614
1615         return radeon_do_engine_reset(dev);
1616 }
1617
1618 /* ================================================================
1619  * Fullscreen mode
1620  */
1621
1622 /* KW: Deprecated to say the least:
1623  */
1624 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1625 {
1626         return 0;
1627 }
1628
1629 /* ================================================================
1630  * Freelist management
1631  */
1632
1633 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1634  *   bufs until freelist code is used.  Note this hides a problem with
1635  *   the scratch register * (used to keep track of last buffer
1636  *   completed) being written to before * the last buffer has actually
1637  *   completed rendering.
1638  *
1639  * KW:  It's also a good way to find free buffers quickly.
1640  *
1641  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1642  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1643  * we essentially have to do this, else old clients will break.
1644  *
1645  * However, it does leave open a potential deadlock where all the
1646  * buffers are held by other clients, which can't release them because
1647  * they can't get the lock.
1648  */
1649
1650 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1651 {
1652         struct drm_device_dma *dma = dev->dma;
1653         drm_radeon_private_t *dev_priv = dev->dev_private;
1654         drm_radeon_buf_priv_t *buf_priv;
1655         struct drm_buf *buf;
1656         int i, t;
1657         int start;
1658
1659         if (++dev_priv->last_buf >= dma->buf_count)
1660                 dev_priv->last_buf = 0;
1661
1662         start = dev_priv->last_buf;
1663
1664         for (t = 0; t < dev_priv->usec_timeout; t++) {
1665                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1666                 DRM_DEBUG("done_age = %d\n", done_age);
1667                 for (i = start; i < dma->buf_count; i++) {
1668                         buf = dma->buflist[i];
1669                         buf_priv = buf->dev_private;
1670                         if (buf->file_priv == NULL || (buf->pending &&
1671                                                        buf_priv->age <=
1672                                                        done_age)) {
1673                                 dev_priv->stats.requested_bufs++;
1674                                 buf->pending = 0;
1675                                 return buf;
1676                         }
1677                         start = 0;
1678                 }
1679
1680                 if (t) {
1681                         DRM_UDELAY(1);
1682                         dev_priv->stats.freelist_loops++;
1683                 }
1684         }
1685
1686         DRM_DEBUG("returning NULL!\n");
1687         return NULL;
1688 }
1689
1690 #if 0
1691 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1692 {
1693         struct drm_device_dma *dma = dev->dma;
1694         drm_radeon_private_t *dev_priv = dev->dev_private;
1695         drm_radeon_buf_priv_t *buf_priv;
1696         struct drm_buf *buf;
1697         int i, t;
1698         int start;
1699         u32 done_age;
1700
1701         done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1702         if (++dev_priv->last_buf >= dma->buf_count)
1703                 dev_priv->last_buf = 0;
1704
1705         start = dev_priv->last_buf;
1706         dev_priv->stats.freelist_loops++;
1707
1708         for (t = 0; t < 2; t++) {
1709                 for (i = start; i < dma->buf_count; i++) {
1710                         buf = dma->buflist[i];
1711                         buf_priv = buf->dev_private;
1712                         if (buf->file_priv == 0 || (buf->pending &&
1713                                                     buf_priv->age <=
1714                                                     done_age)) {
1715                                 dev_priv->stats.requested_bufs++;
1716                                 buf->pending = 0;
1717                                 return buf;
1718                         }
1719                 }
1720                 start = 0;
1721         }
1722
1723         return NULL;
1724 }
1725 #endif
1726
1727 void radeon_freelist_reset(struct drm_device * dev)
1728 {
1729         struct drm_device_dma *dma = dev->dma;
1730         drm_radeon_private_t *dev_priv = dev->dev_private;
1731         int i;
1732
1733         dev_priv->last_buf = 0;
1734         for (i = 0; i < dma->buf_count; i++) {
1735                 struct drm_buf *buf = dma->buflist[i];
1736                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1737                 buf_priv->age = 0;
1738         }
1739 }
1740
1741 /* ================================================================
1742  * CP command submission
1743  */
1744
1745 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1746 {
1747         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1748         int i;
1749         u32 last_head = GET_RING_HEAD(dev_priv);
1750
1751         for (i = 0; i < dev_priv->usec_timeout; i++) {
1752                 u32 head = GET_RING_HEAD(dev_priv);
1753
1754                 ring->space = (head - ring->tail) * sizeof(u32);
1755                 if (ring->space <= 0)
1756                         ring->space += ring->size;
1757                 if (ring->space > n)
1758                         return 0;
1759
1760                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1761
1762                 if (head != last_head)
1763                         i = 0;
1764                 last_head = head;
1765
1766                 DRM_UDELAY(1);
1767         }
1768
1769         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1770 #if RADEON_FIFO_DEBUG
1771         radeon_status(dev_priv);
1772         DRM_ERROR("failed!\n");
1773 #endif
1774         return -EBUSY;
1775 }
1776
1777 static int radeon_cp_get_buffers(struct drm_device *dev,
1778                                  struct drm_file *file_priv,
1779                                  struct drm_dma * d)
1780 {
1781         int i;
1782         struct drm_buf *buf;
1783
1784         for (i = d->granted_count; i < d->request_count; i++) {
1785                 buf = radeon_freelist_get(dev);
1786                 if (!buf)
1787                         return -EBUSY;  /* NOTE: broken client */
1788
1789                 buf->file_priv = file_priv;
1790
1791                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1792                                      sizeof(buf->idx)))
1793                         return -EFAULT;
1794                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1795                                      sizeof(buf->total)))
1796                         return -EFAULT;
1797
1798                 d->granted_count++;
1799         }
1800         return 0;
1801 }
1802
1803 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1804 {
1805         struct drm_device_dma *dma = dev->dma;
1806         int ret = 0;
1807         struct drm_dma *d = data;
1808
1809         LOCK_TEST_WITH_RETURN(dev, file_priv);
1810
1811         /* Please don't send us buffers.
1812          */
1813         if (d->send_count != 0) {
1814                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1815                           DRM_CURRENTPID, d->send_count);
1816                 return -EINVAL;
1817         }
1818
1819         /* We'll send you buffers.
1820          */
1821         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1822                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1823                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1824                 return -EINVAL;
1825         }
1826
1827         d->granted_count = 0;
1828
1829         if (d->request_count) {
1830                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1831         }
1832
1833         return ret;
1834 }
1835
1836 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1837 {
1838         drm_radeon_private_t *dev_priv;
1839         int ret = 0;
1840
1841         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1842         if (dev_priv == NULL)
1843                 return -ENOMEM;
1844
1845         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1846         dev->dev_private = (void *)dev_priv;
1847         dev_priv->flags = flags;
1848
1849         switch (flags & RADEON_FAMILY_MASK) {
1850         case CHIP_R100:
1851         case CHIP_RV200:
1852         case CHIP_R200:
1853         case CHIP_R300:
1854         case CHIP_R350:
1855         case CHIP_R420:
1856         case CHIP_R423:
1857         case CHIP_RV410:
1858         case CHIP_RV515:
1859         case CHIP_R520:
1860         case CHIP_RV570:
1861         case CHIP_R580:
1862                 dev_priv->flags |= RADEON_HAS_HIERZ;
1863                 break;
1864         default:
1865                 /* all other chips have no hierarchical z buffer */
1866                 break;
1867         }
1868
1869         if (drm_device_is_agp(dev))
1870                 dev_priv->flags |= RADEON_IS_AGP;
1871         else if (drm_device_is_pcie(dev))
1872                 dev_priv->flags |= RADEON_IS_PCIE;
1873         else
1874                 dev_priv->flags |= RADEON_IS_PCI;
1875
1876         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1877                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1878                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1879         if (ret != 0)
1880                 return ret;
1881
1882         ret = drm_vblank_init(dev, 2);
1883         if (ret) {
1884                 radeon_driver_unload(dev);
1885                 return ret;
1886         }
1887
1888         DRM_DEBUG("%s card detected\n",
1889                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1890         return ret;
1891 }
1892
1893 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1894 {
1895         struct drm_radeon_master_private *master_priv;
1896         unsigned long sareapage;
1897         int ret;
1898
1899         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1900         if (!master_priv)
1901                 return -ENOMEM;
1902
1903         /* prebuild the SAREA */
1904         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
1905         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1906                          &master_priv->sarea);
1907         if (ret) {
1908                 DRM_ERROR("SAREA setup failed\n");
1909                 return ret;
1910         }
1911         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
1912         master_priv->sarea_priv->pfCurrentPage = 0;
1913
1914         master->driver_priv = master_priv;
1915         return 0;
1916 }
1917
1918 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
1919 {
1920         struct drm_radeon_master_private *master_priv = master->driver_priv;
1921
1922         if (!master_priv)
1923                 return;
1924
1925         if (master_priv->sarea_priv &&
1926             master_priv->sarea_priv->pfCurrentPage != 0)
1927                 radeon_cp_dispatch_flip(dev, master);
1928
1929         master_priv->sarea_priv = NULL;
1930         if (master_priv->sarea)
1931                 drm_rmmap_locked(dev, master_priv->sarea);
1932
1933         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1934
1935         master->driver_priv = NULL;
1936 }
1937
1938 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1939  * have to find them.
1940  */
1941 int radeon_driver_firstopen(struct drm_device *dev)
1942 {
1943         int ret;
1944         drm_local_map_t *map;
1945         drm_radeon_private_t *dev_priv = dev->dev_private;
1946
1947         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1948
1949         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1950         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1951                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1952                          _DRM_WRITE_COMBINING, &map);
1953         if (ret != 0)
1954                 return ret;
1955
1956         return 0;
1957 }
1958
1959 int radeon_driver_unload(struct drm_device *dev)
1960 {
1961         drm_radeon_private_t *dev_priv = dev->dev_private;
1962
1963         DRM_DEBUG("\n");
1964
1965         drm_rmmap(dev, dev_priv->mmio);
1966
1967         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1968
1969         dev->dev_private = NULL;
1970         return 0;
1971 }
1972
1973 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
1974 {
1975         int i;
1976         u32 *ring;
1977         int tail_aligned;
1978
1979         /* check if the ring is padded out to 16-dword alignment */
1980
1981         tail_aligned = dev_priv->ring.tail & 0xf;
1982         if (tail_aligned) {
1983                 int num_p2 = 16 - tail_aligned;
1984
1985                 ring = dev_priv->ring.start;
1986                 /* pad with some CP_PACKET2 */
1987                 for (i = 0; i < num_p2; i++)
1988                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
1989
1990                 dev_priv->ring.tail += i;
1991
1992                 dev_priv->ring.space -= num_p2 * sizeof(u32);
1993         }
1994
1995         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
1996
1997         DRM_MEMORYBARRIER();
1998         GET_RING_HEAD( dev_priv );
1999
2000         RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );
2001         /* read from PCI bus to ensure correct posting */
2002         RADEON_READ( RADEON_CP_RB_RPTR );
2003 }