drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * drivers/i2c/busses/i2c-bfin-twi.c
   3  *
   4  * Description: Driver for Blackfin Two Wire Interface
   5  *
   6  * Author:      sonicz  <sonic.zhang@analog.com>
   7  *
   8  * Copyright (c) 2005-2007 Analog Devices, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/init.h>
  28 #include <linux/i2c.h>
  29 #include <linux/mm.h>
  30 #include <linux/timer.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/completion.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/platform_device.h>
  35
  36 #include <asm/blackfin.h>
  37 #include <asm/irq.h>
  38
  39 #define POLL_TIMEOUT       (2 * HZ)
  40
  41 /* SMBus mode*/
  42 #define TWI_I2C_MODE_STANDARD           1
  43 #define TWI_I2C_MODE_STANDARDSUB        2
  44 #define TWI_I2C_MODE_COMBINED           3
  45 #define TWI_I2C_MODE_REPEAT             4
  46
  47 struct bfin_twi_iface {
  48         int                     irq;
  49         spinlock_t              lock;
  50         char                    read_write;
  51         u8                      command;
  52         u8                      *transPtr;
  53         int                     readNum;
  54         int                     writeNum;
  55         int                     cur_mode;
  56         int                     manual_stop;
  57         int                     result;
  58         int                     timeout_count;
  59         struct timer_list       timeout_timer;
  60         struct i2c_adapter      adap;
  61         struct completion       complete;
  62         struct i2c_msg          *pmsg;
  63         int                     msg_num;
  64         int                     cur_msg;
  65         void __iomem            *regs_base;
  66 };
  67
  68
  69 #define DEFINE_TWI_REG(reg, off) \
  70 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  71         { return bfin_read16(iface->regs_base + (off)); } \
  72 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  73         { bfin_write16(iface->regs_base + (off), v); }
  74
  75 DEFINE_TWI_REG(CLKDIV, 0x00)
  76 DEFINE_TWI_REG(CONTROL, 0x04)
  77 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  78 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  79 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  80 DEFINE_TWI_REG(MASTER_CTL, 0x14)
  81 DEFINE_TWI_REG(MASTER_STAT, 0x18)
  82 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  83 DEFINE_TWI_REG(INT_STAT, 0x20)
  84 DEFINE_TWI_REG(INT_MASK, 0x24)
  85 DEFINE_TWI_REG(FIFO_CTL, 0x28)
  86 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  87 DEFINE_TWI_REG(XMT_DATA8, 0x80)
  88 DEFINE_TWI_REG(XMT_DATA16, 0x84)
  89 DEFINE_TWI_REG(RCV_DATA8, 0x88)
  90 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  91
  92 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
  93 {
  94         unsigned short twi_int_status = read_INT_STAT(iface);
  95         unsigned short mast_stat = read_MASTER_STAT(iface);
  96
  97         if (twi_int_status & XMTSERV) {
  98                 /* Transmit next data */
  99                 if (iface->writeNum > 0) {
 100                         write_XMT_DATA8(iface, *(iface->transPtr++));
 101                         iface->writeNum--;
 102                 }
 103                 /* start receive immediately after complete sending in
 104                  * combine mode.
 105                  */
 106                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
 107                         write_MASTER_CTL(iface,
 108                                 read_MASTER_CTL(iface) | MDIR | RSTART);
 109                 else if (iface->manual_stop)
 110                         write_MASTER_CTL(iface,
 111                                 read_MASTER_CTL(iface) | STOP);
 112                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 113                                 iface->cur_msg+1 < iface->msg_num)
 114                         write_MASTER_CTL(iface,
 115                                 read_MASTER_CTL(iface) | RSTART);
 116                 SSYNC();
 117                 /* Clear status */
 118                 write_INT_STAT(iface, XMTSERV);
 119                 SSYNC();
 120         }
 121         if (twi_int_status & RCVSERV) {
 122                 if (iface->readNum > 0) {
 123                         /* Receive next data */
 124                         *(iface->transPtr) = read_RCV_DATA8(iface);
 125                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 126                                 /* Change combine mode into sub mode after
 127                                  * read first data.
 128                                  */
 129                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 130                                 /* Get read number from first byte in block
 131                                  * combine mode.
 132                                  */
 133                                 if (iface->readNum == 1 && iface->manual_stop)
 134                                         iface->readNum = *iface->transPtr + 1;
 135                         }
 136                         iface->transPtr++;
 137                         iface->readNum--;
 138                 } else if (iface->manual_stop) {
 139                         write_MASTER_CTL(iface,
 140                                 read_MASTER_CTL(iface) | STOP);
 141                         SSYNC();
 142                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 143                                 iface->cur_msg+1 < iface->msg_num) {
 144                         write_MASTER_CTL(iface,
 145                                 read_MASTER_CTL(iface) | RSTART);
 146                         SSYNC();
 147                 }
 148                 /* Clear interrupt source */
 149                 write_INT_STAT(iface, RCVSERV);
 150                 SSYNC();
 151         }
 152         if (twi_int_status & MERR) {
 153                 write_INT_STAT(iface, MERR);
 154                 write_INT_MASK(iface, 0);
 155                 write_MASTER_STAT(iface, 0x3e);
 156                 write_MASTER_CTL(iface, 0);
 157                 SSYNC();
 158                 iface->result = -EIO;
 159                 /* if both err and complete int stats are set, return proper
 160                  * results.
 161                  */
 162                 if (twi_int_status & MCOMP) {
 163                         write_INT_STAT(iface, MCOMP);
 164                         write_INT_MASK(iface, 0);
 165                         write_MASTER_CTL(iface, 0);
 166                         SSYNC();
 167                         /* If it is a quick transfer, only address bug no data,
 168                          * not an err, return 1.
 169                          */
 170                         if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
 171                                 iface->result = 1;
 172                         /* If address not acknowledged return -1,
 173                          * else return 0.
 174                          */
 175                         else if (!(mast_stat & ANAK))
 176                                 iface->result = 0;
 177                 }
 178                 complete(&iface->complete);
 179                 return;
 180         }
 181         if (twi_int_status & MCOMP) {
 182                 write_INT_STAT(iface, MCOMP);
 183                 SSYNC();
 184                 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 185                         if (iface->readNum == 0) {
 186                                 /* set the read number to 1 and ask for manual
 187                                  * stop in block combine mode
 188                                  */
 189                                 iface->readNum = 1;
 190                                 iface->manual_stop = 1;
 191                                 write_MASTER_CTL(iface,
 192                                         read_MASTER_CTL(iface) | (0xff << 6));
 193                         } else {
 194                                 /* set the readd number in other
 195                                  * combine mode.
 196                                  */
 197                                 write_MASTER_CTL(iface,
 198                                         (read_MASTER_CTL(iface) &
 199                                         (~(0xff << 6))) |
 200                                         (iface->readNum << 6));
 201                         }
 202                         /* remove restart bit and enable master receive */
 203                         write_MASTER_CTL(iface,
 204                                 read_MASTER_CTL(iface) & ~RSTART);
 205                         write_MASTER_CTL(iface,
 206                                 read_MASTER_CTL(iface) | MEN | MDIR);
 207                         SSYNC();
 208                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 209                                 iface->cur_msg+1 < iface->msg_num) {
 210                         iface->cur_msg++;
 211                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 212                         iface->writeNum = iface->readNum =
 213                                 iface->pmsg[iface->cur_msg].len;
 214                         /* Set Transmit device address */
 215                         write_MASTER_ADDR(iface,
 216                                 iface->pmsg[iface->cur_msg].addr);
 217                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 218                                 iface->read_write = I2C_SMBUS_READ;
 219                         else {
 220                                 iface->read_write = I2C_SMBUS_WRITE;
 221                                 /* Transmit first data */
 222                                 if (iface->writeNum > 0) {
 223                                         write_XMT_DATA8(iface,
 224                                                 *(iface->transPtr++));
 225                                         iface->writeNum--;
 226                                         SSYNC();
 227                                 }
 228                         }
 229
 230                         if (iface->pmsg[iface->cur_msg].len <= 255)
 231                                 write_MASTER_CTL(iface,
 232                                 iface->pmsg[iface->cur_msg].len << 6);
 233                         else {
 234                                 write_MASTER_CTL(iface, 0xff << 6);
 235                                 iface->manual_stop = 1;
 236                         }
 237                         /* remove restart bit and enable master receive */
 238                         write_MASTER_CTL(iface,
 239                                 read_MASTER_CTL(iface) & ~RSTART);
 240                         write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
 241                                 MEN | ((iface->read_write == I2C_SMBUS_READ) ?
 242                                 MDIR : 0));
 243                         SSYNC();
 244                 } else {
 245                         iface->result = 1;
 246                         write_INT_MASK(iface, 0);
 247                         write_MASTER_CTL(iface, 0);
 248                         SSYNC();
 249                         complete(&iface->complete);
 250                 }
 251         }
 252 }
 253
 254 /* Interrupt handler */
 255 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 256 {
 257         struct bfin_twi_iface *iface = dev_id;
 258         unsigned long flags;
 259
 260         spin_lock_irqsave(&iface->lock, flags);
 261         del_timer(&iface->timeout_timer);
 262         bfin_twi_handle_interrupt(iface);
 263         spin_unlock_irqrestore(&iface->lock, flags);
 264         return IRQ_HANDLED;
 265 }
 266
 267 static void bfin_twi_timeout(unsigned long data)
 268 {
 269         struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
 270         unsigned long flags;
 271
 272         spin_lock_irqsave(&iface->lock, flags);
 273         bfin_twi_handle_interrupt(iface);
 274         if (iface->result == 0) {
 275                 iface->timeout_count--;
 276                 if (iface->timeout_count > 0) {
 277                         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 278                         add_timer(&iface->timeout_timer);
 279                 } else {
 280                         iface->result = -1;
 281                         complete(&iface->complete);
 282                 }
 283         }
 284         spin_unlock_irqrestore(&iface->lock, flags);
 285 }
 286
 287 /*
 288  * Generic i2c master transfer entrypoint
 289  */
 290 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 291                                 struct i2c_msg *msgs, int num)
 292 {
 293         struct bfin_twi_iface *iface = adap->algo_data;
 294         struct i2c_msg *pmsg;
 295         int rc = 0;
 296
 297         if (!(read_CONTROL(iface) & TWI_ENA))
 298                 return -ENXIO;
 299
 300         while (read_MASTER_STAT(iface) & BUSBUSY)
 301                 yield();
 302
 303         iface->pmsg = msgs;
 304         iface->msg_num = num;
 305         iface->cur_msg = 0;
 306
 307         pmsg = &msgs[0];
 308         if (pmsg->flags & I2C_M_TEN) {
 309                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 310                 return -EINVAL;
 311         }
 312
 313         iface->cur_mode = TWI_I2C_MODE_REPEAT;
 314         iface->manual_stop = 0;
 315         iface->transPtr = pmsg->buf;
 316         iface->writeNum = iface->readNum = pmsg->len;
 317         iface->result = 0;
 318         iface->timeout_count = 10;
 319         /* Set Transmit device address */
 320         write_MASTER_ADDR(iface, pmsg->addr);
 321
 322         /* FIFO Initiation. Data in FIFO should be
 323          *  discarded before start a new operation.
 324          */
 325         write_FIFO_CTL(iface, 0x3);
 326         SSYNC();
 327         write_FIFO_CTL(iface, 0);
 328         SSYNC();
 329
 330         if (pmsg->flags & I2C_M_RD)
 331                 iface->read_write = I2C_SMBUS_READ;
 332         else {
 333                 iface->read_write = I2C_SMBUS_WRITE;
 334                 /* Transmit first data */
 335                 if (iface->writeNum > 0) {
 336                         write_XMT_DATA8(iface, *(iface->transPtr++));
 337                         iface->writeNum--;
 338                         SSYNC();
 339                 }
 340         }
 341
 342         /* clear int stat */
 343         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 344
 345         /* Interrupt mask . Enable XMT, RCV interrupt */
 346         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 347         SSYNC();
 348
 349         if (pmsg->len <= 255)
 350                 write_MASTER_CTL(iface, pmsg->len << 6);
 351         else {
 352                 write_MASTER_CTL(iface, 0xff << 6);
 353                 iface->manual_stop = 1;
 354         }
 355
 356         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 357         add_timer(&iface->timeout_timer);
 358
 359         /* Master enable */
 360         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 361                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 362                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 363         SSYNC();
 364
 365         wait_for_completion(&iface->complete);
 366
 367         rc = iface->result;
 368
 369         if (rc == 1)
 370                 return num;
 371         else
 372                 return rc;
 373 }
 374
 375 /*
 376  * SMBus type transfer entrypoint
 377  */
 378
 379 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 380                         unsigned short flags, char read_write,
 381                         u8 command, int size, union i2c_smbus_data *data)
 382 {
 383         struct bfin_twi_iface *iface = adap->algo_data;
 384         int rc = 0;
 385
 386         if (!(read_CONTROL(iface) & TWI_ENA))
 387                 return -ENXIO;
 388
 389         while (read_MASTER_STAT(iface) & BUSBUSY)
 390                 yield();
 391
 392         iface->writeNum = 0;
 393         iface->readNum = 0;
 394
 395         /* Prepare datas & select mode */
 396         switch (size) {
 397         case I2C_SMBUS_QUICK:
 398                 iface->transPtr = NULL;
 399                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 400                 break;
 401         case I2C_SMBUS_BYTE:
 402                 if (data == NULL)
 403                         iface->transPtr = NULL;
 404                 else {
 405                         if (read_write == I2C_SMBUS_READ)
 406                                 iface->readNum = 1;
 407                         else
 408                                 iface->writeNum = 1;
 409                         iface->transPtr = &data->byte;
 410                 }
 411                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 412                 break;
 413         case I2C_SMBUS_BYTE_DATA:
 414                 if (read_write == I2C_SMBUS_READ) {
 415                         iface->readNum = 1;
 416                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 417                 } else {
 418                         iface->writeNum = 1;
 419                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 420                 }
 421                 iface->transPtr = &data->byte;
 422                 break;
 423         case I2C_SMBUS_WORD_DATA:
 424                 if (read_write == I2C_SMBUS_READ) {
 425                         iface->readNum = 2;
 426                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 427                 } else {
 428                         iface->writeNum = 2;
 429                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 430                 }
 431                 iface->transPtr = (u8 *)&data->word;
 432                 break;
 433         case I2C_SMBUS_PROC_CALL:
 434                 iface->writeNum = 2;
 435                 iface->readNum = 2;
 436                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 437                 iface->transPtr = (u8 *)&data->word;
 438                 break;
 439         case I2C_SMBUS_BLOCK_DATA:
 440                 if (read_write == I2C_SMBUS_READ) {
 441                         iface->readNum = 0;
 442                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 443                 } else {
 444                         iface->writeNum = data->block[0] + 1;
 445                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 446                 }
 447                 iface->transPtr = data->block;
 448                 break;
 449         default:
 450                 return -1;
 451         }
 452
 453         iface->result = 0;
 454         iface->manual_stop = 0;
 455         iface->read_write = read_write;
 456         iface->command = command;
 457         iface->timeout_count = 10;
 458
 459         /* FIFO Initiation. Data in FIFO should be discarded before
 460          * start a new operation.
 461          */
 462         write_FIFO_CTL(iface, 0x3);
 463         SSYNC();
 464         write_FIFO_CTL(iface, 0);
 465
 466         /* clear int stat */
 467         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 468
 469         /* Set Transmit device address */
 470         write_MASTER_ADDR(iface, addr);
 471         SSYNC();
 472
 473         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 474         add_timer(&iface->timeout_timer);
 475
 476         switch (iface->cur_mode) {
 477         case TWI_I2C_MODE_STANDARDSUB:
 478                 write_XMT_DATA8(iface, iface->command);
 479                 write_INT_MASK(iface, MCOMP | MERR |
 480                         ((iface->read_write == I2C_SMBUS_READ) ?
 481                         RCVSERV : XMTSERV));
 482                 SSYNC();
 483
 484                 if (iface->writeNum + 1 <= 255)
 485                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 486                 else {
 487                         write_MASTER_CTL(iface, 0xff << 6);
 488                         iface->manual_stop = 1;
 489                 }
 490                 /* Master enable */
 491                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 492                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 493                 break;
 494         case TWI_I2C_MODE_COMBINED:
 495                 write_XMT_DATA8(iface, iface->command);
 496                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 497                 SSYNC();
 498
 499                 if (iface->writeNum > 0)
 500                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 501                 else
 502                         write_MASTER_CTL(iface, 0x1 << 6);
 503                 /* Master enable */
 504                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 505                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 506                 break;
 507         default:
 508                 write_MASTER_CTL(iface, 0);
 509                 if (size != I2C_SMBUS_QUICK) {
 510                         /* Don't access xmit data register when this is a
 511                          * read operation.
 512                          */
 513                         if (iface->read_write != I2C_SMBUS_READ) {
 514                                 if (iface->writeNum > 0) {
 515                                         write_XMT_DATA8(iface,
 516                                                 *(iface->transPtr++));
 517                                         if (iface->writeNum <= 255)
 518                                                 write_MASTER_CTL(iface,
 519                                                         iface->writeNum << 6);
 520                                         else {
 521                                                 write_MASTER_CTL(iface,
 522                                                         0xff << 6);
 523                                                 iface->manual_stop = 1;
 524                                         }
 525                                         iface->writeNum--;
 526                                 } else {
 527                                         write_XMT_DATA8(iface, iface->command);
 528                                         write_MASTER_CTL(iface, 1 << 6);
 529                                 }
 530                         } else {
 531                                 if (iface->readNum > 0 && iface->readNum <= 255)
 532                                         write_MASTER_CTL(iface,
 533                                                 iface->readNum << 6);
 534                                 else if (iface->readNum > 255) {
 535                                         write_MASTER_CTL(iface, 0xff << 6);
 536                                         iface->manual_stop = 1;
 537                                 } else {
 538                                         del_timer(&iface->timeout_timer);
 539                                         break;
 540                                 }
 541                         }
 542                 }
 543                 write_INT_MASK(iface, MCOMP | MERR |
 544                         ((iface->read_write == I2C_SMBUS_READ) ?
 545                         RCVSERV : XMTSERV));
 546                 SSYNC();
 547
 548                 /* Master enable */
 549                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 550                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 551                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 552                 break;
 553         }
 554         SSYNC();
 555
 556         wait_for_completion(&iface->complete);
 557
 558         rc = (iface->result >= 0) ? 0 : -1;
 559
 560         return rc;
 561 }
 562
 563 /*
 564  * Return what the adapter supports
 565  */
 566 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 567 {
 568         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 569                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 570                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 571                I2C_FUNC_I2C;
 572 }
 573
 574
 575 static struct i2c_algorithm bfin_twi_algorithm = {
 576         .master_xfer   = bfin_twi_master_xfer,
 577         .smbus_xfer    = bfin_twi_smbus_xfer,
 578         .functionality = bfin_twi_functionality,
 579 };
 580
 581
 582 static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
 583 {
 584         struct bfin_twi_iface *iface = platform_get_drvdata(dev);
 585
 586         /* Disable TWI */
 587         write_CONTROL(iface, read_CONTROL(iface) & ~TWI_ENA);
 588         SSYNC();
 589
 590         return 0;
 591 }
 592
 593 static int i2c_bfin_twi_resume(struct platform_device *dev)
 594 {
 595         struct bfin_twi_iface *iface = platform_get_drvdata(dev);
 596
 597         /* Enable TWI */
 598         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 599         SSYNC();
 600
 601         return 0;
 602 }
 603
 604 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 605 {
 606         struct bfin_twi_iface *iface;
 607         struct i2c_adapter *p_adap;
 608         struct resource *res;
 609         int rc;
 610
 611         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
 612         if (!iface) {
 613                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 614                 rc = -ENOMEM;
 615                 goto out_error_nomem;
 616         }
 617
 618         spin_lock_init(&(iface->lock));
 619         init_completion(&(iface->complete));
 620
 621         /* Find and map our resources */
 622         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 623         if (res == NULL) {
 624                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
 625                 rc = -ENOENT;
 626                 goto out_error_get_res;
 627         }
 628
 629         iface->regs_base = ioremap(res->start, res->end - res->start + 1);
 630         if (iface->regs_base == NULL) {
 631                 dev_err(&pdev->dev, "Cannot map IO\n");
 632                 rc = -ENXIO;
 633                 goto out_error_ioremap;
 634         }
 635
 636         iface->irq = platform_get_irq(pdev, 0);
 637         if (iface->irq < 0) {
 638                 dev_err(&pdev->dev, "No IRQ specified\n");
 639                 rc = -ENOENT;
 640                 goto out_error_no_irq;
 641         }
 642
 643         init_timer(&(iface->timeout_timer));
 644         iface->timeout_timer.function = bfin_twi_timeout;
 645         iface->timeout_timer.data = (unsigned long)iface;
 646
 647         p_adap = &iface->adap;
 648         p_adap->id = I2C_HW_BLACKFIN;
 649         p_adap->nr = pdev->id;
 650         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 651         p_adap->algo = &bfin_twi_algorithm;
 652         p_adap->algo_data = iface;
 653         p_adap->class = I2C_CLASS_ALL;
 654         p_adap->dev.parent = &pdev->dev;
 655
 656         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 657                 IRQF_DISABLED, pdev->name, iface);
 658         if (rc) {
 659                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 660                 rc = -ENODEV;
 661                 goto out_error_req_irq;
 662         }
 663
 664         /* Set TWI internal clock as 10MHz */
 665         write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
 666
 667         /* Set Twi interface clock as specified */
 668         write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
 669                         << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
 670                         & 0xFF));
 671
 672         /* Enable TWI */
 673         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 674         SSYNC();
 675
 676         rc = i2c_add_numbered_adapter(p_adap);
 677         if (rc < 0) {
 678                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 679                 goto out_error_add_adapter;
 680         }
 681
 682         platform_set_drvdata(pdev, iface);
 683
 684         dev_info(&pdev->dev, "Blackfin I2C TWI controller, regs_base@%p\n",
 685                 iface->regs_base);
 686
 687         return 0;
 688
 689 out_error_add_adapter:
 690         free_irq(iface->irq, iface);
 691 out_error_req_irq:
 692 out_error_no_irq:
 693         iounmap(iface->regs_base);
 694 out_error_ioremap:
 695 out_error_get_res:
 696         kfree(iface);
 697 out_error_nomem:
 698         return rc;
 699 }
 700
 701 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 702 {
 703         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 704
 705         platform_set_drvdata(pdev, NULL);
 706
 707         i2c_del_adapter(&(iface->adap));
 708         free_irq(iface->irq, iface);
 709         iounmap(iface->regs_base);
 710         kfree(iface);
 711
 712         return 0;
 713 }
 714
 715 static struct platform_driver i2c_bfin_twi_driver = {
 716         .probe          = i2c_bfin_twi_probe,
 717         .remove         = i2c_bfin_twi_remove,
 718         .suspend        = i2c_bfin_twi_suspend,
 719         .resume         = i2c_bfin_twi_resume,
 720         .driver         = {
 721                 .name   = "i2c-bfin-twi",
 722                 .owner  = THIS_MODULE,
 723         },
 724 };
 725
 726 static int __init i2c_bfin_twi_init(void)
 727 {
 728         return platform_driver_register(&i2c_bfin_twi_driver);
 729 }
 730
 731 static void __exit i2c_bfin_twi_exit(void)
 732 {
 733         platform_driver_unregister(&i2c_bfin_twi_driver);
 734 }
 735
 736 MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
 737 MODULE_DESCRIPTION("I2C-Bus adapter routines for Blackfin TWI");
 738 MODULE_LICENSE("GPL");
 739
 740 module_init(i2c_bfin_twi_init);
 741 module_exit(i2c_bfin_twi_exit);