2 * TI OMAP I2C master mode driver
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@nokia.com>
13 * Syed Khasim <x0khasim@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
30 #include <linux/module.h>
31 #include <linux/delay.h>
32 #include <linux/i2c.h>
33 #include <linux/err.h>
34 #include <linux/interrupt.h>
35 #include <linux/completion.h>
36 #include <linux/platform_device.h>
37 #include <linux/clk.h>
41 /* Hack to enable zero length transfers and smbus quick until clean fix
45 /* timeout waiting for the controller to respond */
46 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
48 #define OMAP_I2C_REV_REG 0x00
49 #define OMAP_I2C_IE_REG 0x04
50 #define OMAP_I2C_STAT_REG 0x08
51 #define OMAP_I2C_IV_REG 0x0c
52 #define OMAP_I2C_SYSS_REG 0x10
53 #define OMAP_I2C_BUF_REG 0x14
54 #define OMAP_I2C_CNT_REG 0x18
55 #define OMAP_I2C_DATA_REG 0x1c
56 #define OMAP_I2C_SYSC_REG 0x20
57 #define OMAP_I2C_CON_REG 0x24
58 #define OMAP_I2C_OA_REG 0x28
59 #define OMAP_I2C_SA_REG 0x2c
60 #define OMAP_I2C_PSC_REG 0x30
61 #define OMAP_I2C_SCLL_REG 0x34
62 #define OMAP_I2C_SCLH_REG 0x38
63 #define OMAP_I2C_SYSTEST_REG 0x3c
64 #define OMAP_I2C_BUFSTAT_REG 0x40
66 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
67 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer draining int enable */
68 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer draining int enable */
69 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
70 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
71 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
72 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
73 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
75 /* I2C Status Register (OMAP_I2C_STAT): */
76 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
77 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
78 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
79 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
80 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
81 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
82 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
83 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
84 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
85 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
86 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
87 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
89 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
90 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
91 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
92 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
93 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
95 /* I2C Configuration Register (OMAP_I2C_CON): */
96 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
97 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
98 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
99 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
100 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
101 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
102 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
103 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
104 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
105 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
107 /* I2C SCL time value when Master */
108 #define OMAP_I2C_SCLL_HSSCLL 8
109 #define OMAP_I2C_SCLH_HSSCLH 8
111 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
113 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
114 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
115 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
116 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
117 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
118 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
119 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
120 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
123 /* I2C System Status register (OMAP_I2C_SYSS): */
124 #define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
126 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
127 #define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
129 struct omap_i2c_dev {
131 void __iomem *base; /* virtual */
133 struct clk *iclk; /* Interface clock */
134 struct clk *fclk; /* Functional clock */
135 struct completion cmd_complete;
136 struct resource *ioarea;
137 u32 speed; /* Speed of bus in Khz */
141 struct i2c_adapter adapter;
142 u8 fifo_size; /* use as flag and value
143 * fifo_size==0 implies no fifo
144 * if set, should be trsh+1
147 unsigned b_hw:1; /* bad h/w fixes */
149 u16 iestate; /* Saved interrupt register */
152 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
155 __raw_writew(val, i2c_dev->base + reg);
158 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
160 return __raw_readw(i2c_dev->base + reg);
163 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
165 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
166 dev->iclk = clk_get(dev->dev, "i2c_ick");
167 if (IS_ERR(dev->iclk)) {
172 /* For I2C operations on 2430 we need 96Mhz clock */
173 if (cpu_is_omap2430()) {
174 dev->fclk = clk_get(dev->dev, "i2chs_fck");
175 if (IS_ERR(dev->fclk)) {
176 if (dev->iclk != NULL) {
184 dev->fclk = clk_get(dev->dev, "i2c_fck");
185 if (IS_ERR(dev->fclk)) {
186 if (dev->iclk != NULL) {
197 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
201 if (dev->iclk != NULL) {
207 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
209 if (dev->iclk != NULL)
210 clk_enable(dev->iclk);
211 clk_enable(dev->fclk);
214 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
217 static void omap_i2c_idle(struct omap_i2c_dev *dev)
221 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
222 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
224 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
226 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
228 * The wmb() is to ensure that the I2C interrupt mask write
229 * reaches the I2C controller before the dev->idle store
234 clk_disable(dev->fclk);
235 if (dev->iclk != NULL)
236 clk_disable(dev->iclk);
239 static int omap_i2c_init(struct omap_i2c_dev *dev)
241 u16 psc = 0, scll = 0, sclh = 0;
242 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
243 unsigned long fclk_rate = 12000000;
244 unsigned long timeout;
245 unsigned long internal_clk = 0;
248 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
249 /* For some reason we need to set the EN bit before the
250 * reset done bit gets set. */
251 timeout = jiffies + OMAP_I2C_TIMEOUT;
252 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
253 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
254 OMAP_I2C_SYSS_RDONE)) {
255 if (time_after(jiffies, timeout)) {
256 dev_warn(dev->dev, "timeout waiting "
257 "for controller reset\n");
263 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
265 if (cpu_class_is_omap1()) {
266 struct clk *armxor_ck;
268 armxor_ck = clk_get(NULL, "armxor_ck");
269 if (IS_ERR(armxor_ck))
270 dev_warn(dev->dev, "Could not get armxor_ck\n");
272 fclk_rate = clk_get_rate(armxor_ck);
275 /* TRM for 5912 says the I2C clock must be prescaled to be
276 * between 7 - 12 MHz. The XOR input clock is typically
277 * 12, 13 or 19.2 MHz. So we should have code that produces:
279 * XOR MHz Divider Prescaler
284 if (fclk_rate > 12000000)
285 psc = fclk_rate / 12000000;
288 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
290 /* HSI2C controller internal clk rate should be 19.2 Mhz */
291 internal_clk = 19200;
292 fclk_rate = clk_get_rate(dev->fclk) / 1000;
294 /* Compute prescaler divisor */
295 psc = fclk_rate / internal_clk;
298 /* If configured for High Speed */
299 if (dev->speed > 400) {
300 /* For first phase of HS mode */
301 fsscll = internal_clk / (400 * 2) - 6;
302 fssclh = internal_clk / (400 * 2) - 6;
304 /* For second phase of HS mode */
305 hsscll = fclk_rate / (dev->speed * 2) - 6;
306 hssclh = fclk_rate / (dev->speed * 2) - 6;
308 /* To handle F/S modes */
309 fsscll = internal_clk / (dev->speed * 2) - 6;
310 fssclh = internal_clk / (dev->speed * 2) - 6;
312 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
313 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
315 /* Program desired operating rate */
316 fclk_rate /= (psc + 1) * 1000;
319 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
320 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
323 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
324 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
326 /* SCL low and high time values */
327 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
328 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
331 /* Note: setup required fifo size - 1 */
332 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
333 (dev->fifo_size - 1) << 8 | /* RTRSH */
334 OMAP_I2C_BUF_RXFIF_CLR |
335 (dev->fifo_size - 1) | /* XTRSH */
336 OMAP_I2C_BUF_TXFIF_CLR);
338 /* Take the I2C module out of reset: */
339 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
341 /* Enable interrupts */
342 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
343 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
344 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
345 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
346 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
351 * Waiting on Bus Busy
353 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
355 unsigned long timeout;
357 timeout = jiffies + OMAP_I2C_TIMEOUT;
358 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
359 if (time_after(jiffies, timeout)) {
360 dev_warn(dev->dev, "timeout waiting for bus ready\n");
370 * Low level master read/write transaction.
372 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
373 struct i2c_msg *msg, int stop)
375 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
382 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
383 msg->addr, msg->len, msg->flags, stop);
389 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
391 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
393 dev->buf_len = msg->len;
397 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
398 /* REVISIT: Remove this hack when we can get I2C chips from board-*.c
400 * Sigh, seems we can't do zero length transactions. Thus, we
401 * can't probe for devices w/o actually sending/receiving at least
402 * a single byte. So we'll set count to 1 for the zero length
403 * transaction case and hope we don't cause grief for some
404 * arbitrary device due to random byte write/read during
408 dev->buf = &zero_byte;
412 dev->buf_len = msg->len;
416 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
418 /* Clear the FIFO Buffers */
419 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
420 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
421 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
423 init_completion(&dev->cmd_complete);
426 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
428 /* High speed configuration */
429 if (dev->speed > 400)
430 w |= OMAP_I2C_CON_OPMODE_HS;
432 if (msg->flags & I2C_M_TEN)
433 w |= OMAP_I2C_CON_XA;
434 if (!(msg->flags & I2C_M_RD))
435 w |= OMAP_I2C_CON_TRX;
437 if (!dev->b_hw && stop)
438 w |= OMAP_I2C_CON_STP;
440 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
442 if (dev->b_hw && stop) {
443 /* H/w behavior: dont write stt and stp together.. */
444 while (omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & OMAP_I2C_CON_STT) {
445 /* Dont do anything - this will come in a couple of loops at max*/
447 w |= OMAP_I2C_CON_STP;
448 w &= ~OMAP_I2C_CON_STT;
449 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
451 r = wait_for_completion_timeout(&dev->cmd_complete,
457 dev_err(dev->dev, "controller timed out\n");
462 if (likely(!dev->cmd_err))
465 /* We have an error */
466 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
467 OMAP_I2C_STAT_XUDF)) {
472 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
473 if (msg->flags & I2C_M_IGNORE_NAK)
476 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
477 w |= OMAP_I2C_CON_STP;
478 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
487 * Prepare controller for a transaction and call omap_i2c_xfer_msg
488 * to do the work during IRQ processing.
491 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
493 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
497 omap_i2c_unidle(dev);
499 if ((r = omap_i2c_wait_for_bb(dev)) < 0)
502 for (i = 0; i < num; i++) {
503 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
516 omap_i2c_func(struct i2c_adapter *adap)
519 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
521 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
526 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
529 complete(&dev->cmd_complete);
533 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
535 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
538 /* rev1 devices are apparently only on some 15xx */
539 #ifdef CONFIG_ARCH_OMAP15XX
542 omap_i2c_rev1_isr(int this_irq, void *dev_id)
544 struct omap_i2c_dev *dev = dev_id;
550 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
552 case 0x00: /* None */
554 case 0x01: /* Arbitration lost */
555 dev_err(dev->dev, "Arbitration lost\n");
556 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
558 case 0x02: /* No acknowledgement */
559 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
560 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
562 case 0x03: /* Register access ready */
563 omap_i2c_complete_cmd(dev, 0);
565 case 0x04: /* Receive data ready */
567 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
571 *dev->buf++ = w >> 8;
575 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
577 case 0x05: /* Transmit data ready */
582 w |= *dev->buf++ << 8;
585 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
587 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
596 #define omap_i2c_rev1_isr 0
600 omap_i2c_isr(int this_irq, void *dev_id)
602 struct omap_i2c_dev *dev = dev_id;
610 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
611 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
612 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
613 if (count++ == 100) {
614 dev_warn(dev->dev, "Too much work in one IRQ\n");
618 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
621 if (stat & OMAP_I2C_STAT_NACK) {
622 err |= OMAP_I2C_STAT_NACK;
623 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
626 if (stat & OMAP_I2C_STAT_AL) {
627 dev_err(dev->dev, "Arbitration lost\n");
628 err |= OMAP_I2C_STAT_AL;
630 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
632 omap_i2c_complete_cmd(dev, err);
633 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
635 if (dev->fifo_size) {
636 num_bytes = (stat & OMAP_I2C_STAT_RRDY) ? dev->fifo_size :
637 omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG);
641 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
645 /* Data reg from 2430 is 8 bit wide */
646 if (!cpu_is_omap2430() &&
647 !cpu_is_omap34xx()) {
649 *dev->buf++ = w >> 8;
654 if (stat & OMAP_I2C_STAT_RRDY)
655 dev_err(dev->dev, "RRDY IRQ while no data "
657 if (stat & OMAP_I2C_STAT_RDR)
658 dev_err(dev->dev, "RDR IRQ while no data "
663 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
666 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
668 if (dev->fifo_size) {
669 num_bytes = (stat & OMAP_I2C_STAT_XRDY) ? dev->fifo_size :
670 omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG);
678 /* Data reg from 2430 is 8 bit wide */
679 if (!cpu_is_omap2430() &&
680 !cpu_is_omap34xx()) {
682 w |= *dev->buf++ << 8;
687 if (stat & OMAP_I2C_STAT_XRDY)
688 dev_err(dev->dev, "XRDY IRQ while no "
690 if (stat & OMAP_I2C_STAT_XDR)
691 dev_err(dev->dev, "XDR IRQ while no "
695 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
697 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
700 if (stat & OMAP_I2C_STAT_ROVR) {
701 dev_err(dev->dev, "Receive overrun\n");
702 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
704 if (stat & OMAP_I2C_STAT_XUDF) {
705 dev_err(dev->dev, "Transmit underflow\n");
706 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
710 return count ? IRQ_HANDLED : IRQ_NONE;
713 static const struct i2c_algorithm omap_i2c_algo = {
714 .master_xfer = omap_i2c_xfer,
715 .functionality = omap_i2c_func,
719 omap_i2c_probe(struct platform_device *pdev)
721 struct omap_i2c_dev *dev;
722 struct i2c_adapter *adap;
723 struct resource *mem, *irq, *ioarea;
727 /* NOTE: driver uses the static register mapping */
728 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
730 dev_err(&pdev->dev, "no mem resource?\n");
733 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
735 dev_err(&pdev->dev, "no irq resource?\n");
739 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
742 dev_err(&pdev->dev, "I2C region already claimed\n");
746 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
749 goto err_release_region;
752 if (pdev->dev.platform_data != NULL)
753 speed = (u32 *) pdev->dev.platform_data;
755 *speed = 100; /* Defualt speed */
758 dev->dev = &pdev->dev;
759 dev->irq = irq->start;
760 dev->base = (void __iomem *) IO_ADDRESS(mem->start);
761 platform_set_drvdata(pdev, dev);
763 if ((r = omap_i2c_get_clocks(dev)) != 0)
766 omap_i2c_unidle(dev);
768 if (cpu_is_omap15xx())
769 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
771 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
772 /* Set up the fifo size - Get total size */
773 dev->fifo_size = 0x8 <<
774 ((omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3);
776 * Set up notification threshold as half the total available size
777 * This is to ensure that we can handle the status on int call back
780 dev->fifo_size = (dev->fifo_size / 2);
781 dev->b_hw = 1; /* Enable hardware fixes */
784 /* reset ASAP, clearing any IRQs */
787 r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
791 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
792 goto err_unuse_clocks;
794 r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
795 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
796 pdev->id, r >> 4, r & 0xf, dev->speed);
798 adap = &dev->adapter;
799 i2c_set_adapdata(adap, dev);
800 adap->owner = THIS_MODULE;
801 adap->class = I2C_CLASS_HWMON;
802 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
803 adap->algo = &omap_i2c_algo;
804 adap->dev.parent = &pdev->dev;
806 /* i2c device drivers may be active on return from add_adapter() */
808 r = i2c_add_numbered_adapter(adap);
810 dev_err(dev->dev, "failure adding adapter\n");
819 free_irq(dev->irq, dev);
821 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
823 omap_i2c_put_clocks(dev);
825 platform_set_drvdata(pdev, NULL);
828 release_mem_region(mem->start, (mem->end - mem->start) + 1);
834 omap_i2c_remove(struct platform_device *pdev)
836 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
837 struct resource *mem;
839 platform_set_drvdata(pdev, NULL);
841 free_irq(dev->irq, dev);
842 i2c_del_adapter(&dev->adapter);
843 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
844 omap_i2c_put_clocks(dev);
846 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
847 release_mem_region(mem->start, (mem->end - mem->start) + 1);
851 static struct platform_driver omap_i2c_driver = {
852 .probe = omap_i2c_probe,
853 .remove = omap_i2c_remove,
856 .owner = THIS_MODULE,
860 /* I2C may be needed to bring up other drivers */
862 omap_i2c_init_driver(void)
864 return platform_driver_register(&omap_i2c_driver);
866 subsys_initcall(omap_i2c_init_driver);
868 static void __devexit omap_i2c_exit_driver(void)
870 platform_driver_unregister(&omap_i2c_driver);
872 module_exit(omap_i2c_exit_driver);
874 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
875 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
876 MODULE_LICENSE("GPL");
877 MODULE_ALIAS("platform:i2c_omap");