2 * TI OMAP I2C master mode driver
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
41 /* I2C controller revisions */
42 #define OMAP_I2C_REV_2 0x20
44 /* I2C controller revisions present on specific hardware */
45 #define OMAP_I2C_REV_ON_2430 0x36
46 #define OMAP_I2C_REV_ON_3430 0x3C
48 /* timeout waiting for the controller to respond */
49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
51 #define OMAP_I2C_REV_REG 0x00
52 #define OMAP_I2C_IE_REG 0x04
53 #define OMAP_I2C_STAT_REG 0x08
54 #define OMAP_I2C_IV_REG 0x0c
55 #define OMAP_I2C_SYSS_REG 0x10
56 #define OMAP_I2C_BUF_REG 0x14
57 #define OMAP_I2C_CNT_REG 0x18
58 #define OMAP_I2C_DATA_REG 0x1c
59 #define OMAP_I2C_SYSC_REG 0x20
60 #define OMAP_I2C_CON_REG 0x24
61 #define OMAP_I2C_OA_REG 0x28
62 #define OMAP_I2C_SA_REG 0x2c
63 #define OMAP_I2C_PSC_REG 0x30
64 #define OMAP_I2C_SCLL_REG 0x34
65 #define OMAP_I2C_SCLH_REG 0x38
66 #define OMAP_I2C_SYSTEST_REG 0x3c
67 #define OMAP_I2C_BUFSTAT_REG 0x40
69 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
70 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
71 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
72 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
73 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
74 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
75 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
76 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
78 /* I2C Status Register (OMAP_I2C_STAT): */
79 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
80 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
81 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
82 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
83 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
84 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
85 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
86 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
87 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
88 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
89 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
90 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
92 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
93 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
94 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
95 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
96 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
98 /* I2C Configuration Register (OMAP_I2C_CON): */
99 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
100 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
101 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
102 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
103 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
104 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
105 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
106 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
107 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
108 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
110 /* I2C SCL time value when Master */
111 #define OMAP_I2C_SCLL_HSSCLL 8
112 #define OMAP_I2C_SCLH_HSSCLH 8
114 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
116 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
117 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
118 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
119 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
120 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
121 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
122 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
123 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
126 /* I2C System Status register (OMAP_I2C_SYSS): */
127 #define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
129 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
130 #define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
132 struct omap_i2c_dev {
134 void __iomem *base; /* virtual */
136 struct clk *iclk; /* Interface clock */
137 struct clk *fclk; /* Functional clock */
138 struct completion cmd_complete;
139 struct resource *ioarea;
140 u32 speed; /* Speed of bus in Khz */
144 struct i2c_adapter adapter;
145 u8 fifo_size; /* use as flag and value
146 * fifo_size==0 implies no fifo
147 * if set, should be trsh+1
150 unsigned b_hw:1; /* bad h/w fixes */
152 u16 iestate; /* Saved interrupt register */
155 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
158 __raw_writew(val, i2c_dev->base + reg);
161 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
163 return __raw_readw(i2c_dev->base + reg);
166 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
168 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
169 dev->iclk = clk_get(dev->dev, "i2c_ick");
170 if (IS_ERR(dev->iclk)) {
176 dev->fclk = clk_get(dev->dev, "i2c_fck");
177 if (IS_ERR(dev->fclk)) {
178 if (dev->iclk != NULL) {
189 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
193 if (dev->iclk != NULL) {
199 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
203 if (dev->iclk != NULL)
204 clk_enable(dev->iclk);
205 clk_enable(dev->fclk);
208 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
211 static void omap_i2c_idle(struct omap_i2c_dev *dev)
217 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
218 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
219 if (dev->rev < OMAP_I2C_REV_2) {
220 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
222 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
224 /* Flush posted write before the dev->idle store occurs */
225 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
228 clk_disable(dev->fclk);
229 if (dev->iclk != NULL)
230 clk_disable(dev->iclk);
233 static int omap_i2c_init(struct omap_i2c_dev *dev)
235 u16 psc = 0, scll = 0, sclh = 0;
236 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
237 unsigned long fclk_rate = 12000000;
238 unsigned long timeout;
239 unsigned long internal_clk = 0;
241 if (dev->rev >= OMAP_I2C_REV_2) {
242 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
243 /* For some reason we need to set the EN bit before the
244 * reset done bit gets set. */
245 timeout = jiffies + OMAP_I2C_TIMEOUT;
246 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
247 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
248 OMAP_I2C_SYSS_RDONE)) {
249 if (time_after(jiffies, timeout)) {
250 dev_warn(dev->dev, "timeout waiting "
251 "for controller reset\n");
257 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
259 if (cpu_class_is_omap1()) {
260 struct clk *armxor_ck;
262 armxor_ck = clk_get(NULL, "armxor_ck");
263 if (IS_ERR(armxor_ck))
264 dev_warn(dev->dev, "Could not get armxor_ck\n");
266 fclk_rate = clk_get_rate(armxor_ck);
269 /* TRM for 5912 says the I2C clock must be prescaled to be
270 * between 7 - 12 MHz. The XOR input clock is typically
271 * 12, 13 or 19.2 MHz. So we should have code that produces:
273 * XOR MHz Divider Prescaler
278 if (fclk_rate > 12000000)
279 psc = fclk_rate / 12000000;
282 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
284 /* HSI2C controller internal clk rate should be 19.2 Mhz */
285 internal_clk = 19200;
286 fclk_rate = clk_get_rate(dev->fclk) / 1000;
288 /* Compute prescaler divisor */
289 psc = fclk_rate / internal_clk;
292 /* If configured for High Speed */
293 if (dev->speed > 400) {
294 /* For first phase of HS mode */
295 fsscll = internal_clk / (400 * 2) - 6;
296 fssclh = internal_clk / (400 * 2) - 6;
298 /* For second phase of HS mode */
299 hsscll = fclk_rate / (dev->speed * 2) - 6;
300 hssclh = fclk_rate / (dev->speed * 2) - 6;
302 /* To handle F/S modes */
303 fsscll = internal_clk / (dev->speed * 2) - 6;
304 fssclh = internal_clk / (dev->speed * 2) - 6;
306 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
307 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
309 /* Program desired operating rate */
310 fclk_rate /= (psc + 1) * 1000;
313 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
314 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
317 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
318 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
320 /* SCL low and high time values */
321 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
322 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
325 /* Note: setup required fifo size - 1 */
326 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
327 (dev->fifo_size - 1) << 8 | /* RTRSH */
328 OMAP_I2C_BUF_RXFIF_CLR |
329 (dev->fifo_size - 1) | /* XTRSH */
330 OMAP_I2C_BUF_TXFIF_CLR);
332 /* Take the I2C module out of reset: */
333 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
335 /* Enable interrupts */
336 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
337 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
338 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
339 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
340 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
345 * Waiting on Bus Busy
347 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
349 unsigned long timeout;
351 timeout = jiffies + OMAP_I2C_TIMEOUT;
352 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
353 if (time_after(jiffies, timeout)) {
354 dev_warn(dev->dev, "timeout waiting for bus ready\n");
364 * Low level master read/write transaction.
366 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
367 struct i2c_msg *msg, int stop)
369 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
373 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
374 msg->addr, msg->len, msg->flags, stop);
379 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
381 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
383 dev->buf_len = msg->len;
385 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
387 /* Clear the FIFO Buffers */
388 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
389 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
390 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
392 init_completion(&dev->cmd_complete);
395 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
397 /* High speed configuration */
398 if (dev->speed > 400)
399 w |= OMAP_I2C_CON_OPMODE_HS;
401 if (msg->flags & I2C_M_TEN)
402 w |= OMAP_I2C_CON_XA;
403 if (!(msg->flags & I2C_M_RD))
404 w |= OMAP_I2C_CON_TRX;
406 if (!dev->b_hw && stop)
407 w |= OMAP_I2C_CON_STP;
409 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
412 * Don't write stt and stp together on some hardware.
414 if (dev->b_hw && stop) {
415 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
416 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
417 while (con & OMAP_I2C_CON_STT) {
418 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
420 /* Let the user know if i2c is in a bad state */
421 if (time_after(jiffies, delay)) {
422 dev_err(dev->dev, "controller timed out "
423 "waiting for start condition to finish\n");
429 w |= OMAP_I2C_CON_STP;
430 w &= ~OMAP_I2C_CON_STT;
431 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
435 * REVISIT: We should abort the transfer on signals, but the bus goes
436 * into arbitration and we're currently unable to recover from it.
438 r = wait_for_completion_timeout(&dev->cmd_complete,
444 dev_err(dev->dev, "controller timed out\n");
449 if (likely(!dev->cmd_err))
452 /* We have an error */
453 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
454 OMAP_I2C_STAT_XUDF)) {
459 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
460 if (msg->flags & I2C_M_IGNORE_NAK)
463 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
464 w |= OMAP_I2C_CON_STP;
465 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
474 * Prepare controller for a transaction and call omap_i2c_xfer_msg
475 * to do the work during IRQ processing.
478 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
480 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
484 omap_i2c_unidle(dev);
486 r = omap_i2c_wait_for_bb(dev);
490 for (i = 0; i < num; i++) {
491 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
504 omap_i2c_func(struct i2c_adapter *adap)
506 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
510 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
513 complete(&dev->cmd_complete);
517 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
519 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
522 /* rev1 devices are apparently only on some 15xx */
523 #ifdef CONFIG_ARCH_OMAP15XX
526 omap_i2c_rev1_isr(int this_irq, void *dev_id)
528 struct omap_i2c_dev *dev = dev_id;
534 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
536 case 0x00: /* None */
538 case 0x01: /* Arbitration lost */
539 dev_err(dev->dev, "Arbitration lost\n");
540 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
542 case 0x02: /* No acknowledgement */
543 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
544 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
546 case 0x03: /* Register access ready */
547 omap_i2c_complete_cmd(dev, 0);
549 case 0x04: /* Receive data ready */
551 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
555 *dev->buf++ = w >> 8;
559 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
561 case 0x05: /* Transmit data ready */
566 w |= *dev->buf++ << 8;
569 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
571 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
580 #define omap_i2c_rev1_isr NULL
584 omap_i2c_isr(int this_irq, void *dev_id)
586 struct omap_i2c_dev *dev = dev_id;
594 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
595 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
596 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
597 if (count++ == 100) {
598 dev_warn(dev->dev, "Too much work in one IRQ\n");
602 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
605 if (stat & OMAP_I2C_STAT_NACK) {
606 err |= OMAP_I2C_STAT_NACK;
607 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
610 if (stat & OMAP_I2C_STAT_AL) {
611 dev_err(dev->dev, "Arbitration lost\n");
612 err |= OMAP_I2C_STAT_AL;
614 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
616 omap_i2c_complete_cmd(dev, err);
617 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
619 if (dev->fifo_size) {
620 if (stat & OMAP_I2C_STAT_RRDY)
621 num_bytes = dev->fifo_size;
623 num_bytes = omap_i2c_read_reg(dev,
624 OMAP_I2C_BUFSTAT_REG);
628 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
632 /* Data reg from 2430 is 8 bit wide */
633 if (!cpu_is_omap2430() &&
634 !cpu_is_omap34xx()) {
636 *dev->buf++ = w >> 8;
641 if (stat & OMAP_I2C_STAT_RRDY)
643 "RRDY IRQ while no data"
645 if (stat & OMAP_I2C_STAT_RDR)
647 "RDR IRQ while no data"
652 omap_i2c_ack_stat(dev,
653 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
656 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
658 if (dev->fifo_size) {
659 if (stat & OMAP_I2C_STAT_XRDY)
660 num_bytes = dev->fifo_size;
662 num_bytes = omap_i2c_read_reg(dev,
663 OMAP_I2C_BUFSTAT_REG);
671 /* Data reg from 2430 is 8 bit wide */
672 if (!cpu_is_omap2430() &&
673 !cpu_is_omap34xx()) {
675 w |= *dev->buf++ << 8;
680 if (stat & OMAP_I2C_STAT_XRDY)
684 if (stat & OMAP_I2C_STAT_XDR)
690 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
692 omap_i2c_ack_stat(dev,
693 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
696 if (stat & OMAP_I2C_STAT_ROVR) {
697 dev_err(dev->dev, "Receive overrun\n");
698 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
700 if (stat & OMAP_I2C_STAT_XUDF) {
701 dev_err(dev->dev, "Transmit underflow\n");
702 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
706 return count ? IRQ_HANDLED : IRQ_NONE;
709 static const struct i2c_algorithm omap_i2c_algo = {
710 .master_xfer = omap_i2c_xfer,
711 .functionality = omap_i2c_func,
715 omap_i2c_probe(struct platform_device *pdev)
717 struct omap_i2c_dev *dev;
718 struct i2c_adapter *adap;
719 struct resource *mem, *irq, *ioarea;
724 /* NOTE: driver uses the static register mapping */
725 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
727 dev_err(&pdev->dev, "no mem resource?\n");
730 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
732 dev_err(&pdev->dev, "no irq resource?\n");
736 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
739 dev_err(&pdev->dev, "I2C region already claimed\n");
743 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
746 goto err_release_region;
749 if (pdev->dev.platform_data != NULL)
750 speed = *(u32 *)pdev->dev.platform_data;
752 speed = 100; /* Defualt speed */
756 dev->dev = &pdev->dev;
757 dev->irq = irq->start;
758 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
764 platform_set_drvdata(pdev, dev);
766 if ((r = omap_i2c_get_clocks(dev)) != 0)
769 omap_i2c_unidle(dev);
771 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
773 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
776 /* Set up the fifo size - Get total size */
777 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
778 dev->fifo_size = 0x8 << s;
781 * Set up notification threshold as half the total available
782 * size. This is to ensure that we can handle the status on int
783 * call back latencies.
785 dev->fifo_size = (dev->fifo_size / 2);
786 dev->b_hw = 1; /* Enable hardware fixes */
789 /* reset ASAP, clearing any IRQs */
792 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
793 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
796 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
797 goto err_unuse_clocks;
800 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
801 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
805 adap = &dev->adapter;
806 i2c_set_adapdata(adap, dev);
807 adap->owner = THIS_MODULE;
808 adap->class = I2C_CLASS_HWMON;
809 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
810 adap->algo = &omap_i2c_algo;
811 adap->dev.parent = &pdev->dev;
813 /* i2c device drivers may be active on return from add_adapter() */
815 r = i2c_add_numbered_adapter(adap);
817 dev_err(dev->dev, "failure adding adapter\n");
824 free_irq(dev->irq, dev);
826 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
828 omap_i2c_put_clocks(dev);
832 platform_set_drvdata(pdev, NULL);
835 release_mem_region(mem->start, (mem->end - mem->start) + 1);
841 omap_i2c_remove(struct platform_device *pdev)
843 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
844 struct resource *mem;
846 platform_set_drvdata(pdev, NULL);
848 free_irq(dev->irq, dev);
849 i2c_del_adapter(&dev->adapter);
850 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
851 omap_i2c_put_clocks(dev);
854 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
855 release_mem_region(mem->start, (mem->end - mem->start) + 1);
859 static struct platform_driver omap_i2c_driver = {
860 .probe = omap_i2c_probe,
861 .remove = omap_i2c_remove,
864 .owner = THIS_MODULE,
868 /* I2C may be needed to bring up other drivers */
870 omap_i2c_init_driver(void)
872 return platform_driver_register(&omap_i2c_driver);
874 subsys_initcall(omap_i2c_init_driver);
876 static void __exit omap_i2c_exit_driver(void)
878 platform_driver_unregister(&omap_i2c_driver);
880 module_exit(omap_i2c_exit_driver);
882 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
883 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
884 MODULE_LICENSE("GPL");
885 MODULE_ALIAS("platform:i2c_omap");