drivers/ide/arm/icside.c

   1 /*
   2  * linux/drivers/ide/arm/icside.c
   3  *
   4  * Copyright (c) 1996-2004 Russell King.
   5  *
   6  * Please note that this platform does not support 32-bit IDE IO.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/module.h>
  11 #include <linux/ioport.h>
  12 #include <linux/slab.h>
  13 #include <linux/blkdev.h>
  14 #include <linux/errno.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/device.h>
  19 #include <linux/init.h>
  20 #include <linux/scatterlist.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/dma.h>
  24 #include <asm/ecard.h>
  25
  26 #define ICS_IDENT_OFFSET                0x2280
  27
  28 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  29 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  30 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  31 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  32 #define ICS_ARCIN_V5_IDESTEPPING        6
  33
  34 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  35 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  36 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  37 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  38 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  39 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  40 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  41 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  42 #define ICS_ARCIN_V6_IDESTEPPING        6
  43
  44 struct cardinfo {
  45         unsigned int dataoffset;
  46         unsigned int ctrloffset;
  47         unsigned int stepping;
  48 };
  49
  50 static struct cardinfo icside_cardinfo_v5 = {
  51         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  52         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  53         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  54 };
  55
  56 static struct cardinfo icside_cardinfo_v6_1 = {
  57         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  58         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  59         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  60 };
  61
  62 static struct cardinfo icside_cardinfo_v6_2 = {
  63         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  64         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  65         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  66 };
  67
  68 struct icside_state {
  69         unsigned int channel;
  70         unsigned int enabled;
  71         void __iomem *irq_port;
  72         void __iomem *ioc_base;
  73         unsigned int type;
  74         /* parent device... until the IDE core gets one of its own */
  75         struct device *dev;
  76         ide_hwif_t *hwif[2];
  77 };
  78
  79 #define ICS_TYPE_A3IN   0
  80 #define ICS_TYPE_A3USER 1
  81 #define ICS_TYPE_V6     3
  82 #define ICS_TYPE_V5     15
  83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  84
  85 /* ---------------- Version 5 PCB Support Functions --------------------- */
  86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  87  * Purpose  : enable interrupts from card
  88  */
  89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  90 {
  91         struct icside_state *state = ec->irq_data;
  92
  93         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  94 }
  95
  96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  97  * Purpose  : disable interrupts from card
  98  */
  99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 100 {
 101         struct icside_state *state = ec->irq_data;
 102
 103         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 104 }
 105
 106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 107         .irqenable      = icside_irqenable_arcin_v5,
 108         .irqdisable     = icside_irqdisable_arcin_v5,
 109 };
 110
 111
 112 /* ---------------- Version 6 PCB Support Functions --------------------- */
 113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 114  * Purpose  : enable interrupts from card
 115  */
 116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 117 {
 118         struct icside_state *state = ec->irq_data;
 119         void __iomem *base = state->irq_port;
 120
 121         state->enabled = 1;
 122
 123         switch (state->channel) {
 124         case 0:
 125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 126                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 127                 break;
 128         case 1:
 129                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 130                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 131                 break;
 132         }
 133 }
 134
 135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 136  * Purpose  : disable interrupts from card
 137  */
 138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 139 {
 140         struct icside_state *state = ec->irq_data;
 141
 142         state->enabled = 0;
 143
 144         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 146 }
 147
 148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 149  * Purpose  : detect an active interrupt from card
 150  */
 151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 152 {
 153         struct icside_state *state = ec->irq_data;
 154
 155         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 156                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 157 }
 158
 159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 160         .irqenable      = icside_irqenable_arcin_v6,
 161         .irqdisable     = icside_irqdisable_arcin_v6,
 162         .irqpending     = icside_irqpending_arcin_v6,
 163 };
 164
 165 /*
 166  * Handle routing of interrupts.  This is called before
 167  * we write the command to the drive.
 168  */
 169 static void icside_maskproc(ide_drive_t *drive, int mask)
 170 {
 171         ide_hwif_t *hwif = HWIF(drive);
 172         struct icside_state *state = hwif->hwif_data;
 173         unsigned long flags;
 174
 175         local_irq_save(flags);
 176
 177         state->channel = hwif->channel;
 178
 179         if (state->enabled && !mask) {
 180                 switch (hwif->channel) {
 181                 case 0:
 182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 184                         break;
 185                 case 1:
 186                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 187                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 188                         break;
 189                 }
 190         } else {
 191                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 193         }
 194
 195         local_irq_restore(flags);
 196 }
 197
 198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 199 /*
 200  * SG-DMA support.
 201  *
 202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 203  * There is only one DMA controller per card, which means that only
 204  * one drive can be accessed at one time.  NOTE! We do not enforce that
 205  * here, but we rely on the main IDE driver spotting that both
 206  * interfaces use the same IRQ, which should guarantee this.
 207  */
 208
 209 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
 210 {
 211         ide_hwif_t *hwif = drive->hwif;
 212         struct icside_state *state = hwif->hwif_data;
 213         struct scatterlist *sg = hwif->sg_table;
 214
 215         ide_map_sg(drive, rq);
 216
 217         if (rq_data_dir(rq) == READ)
 218                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 219         else
 220                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 221
 222         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
 223                                     hwif->sg_dma_direction);
 224 }
 225
 226 /*
 227  * Configure the IOMD to give the appropriate timings for the transfer
 228  * mode being requested.  We take the advice of the ATA standards, and
 229  * calculate the cycle time based on the transfer mode, and the EIDE
 230  * MW DMA specs that the drive provides in the IDENTIFY command.
 231  *
 232  * We have the following IOMD DMA modes to choose from:
 233  *
 234  *      Type    Active          Recovery        Cycle
 235  *      A       250 (250)       312 (550)       562 (800)
 236  *      B       187             250             437
 237  *      C       125 (125)       125 (375)       250 (500)
 238  *      D       62              125             187
 239  *
 240  * (figures in brackets are actual measured timings)
 241  *
 242  * However, we also need to take care of the read/write active and
 243  * recovery timings:
 244  *
 245  *                      Read    Write
 246  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 247  *      MW0     215     50      215     480     A
 248  *      MW1     80      50      50      150     C
 249  *      MW2     70      25      25      120     C
 250  */
 251 static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
 252 {
 253         int cycle_time, use_dma_info = 0;
 254
 255         switch (xfer_mode) {
 256         case XFER_MW_DMA_2:
 257                 cycle_time = 250;
 258                 use_dma_info = 1;
 259                 break;
 260
 261         case XFER_MW_DMA_1:
 262                 cycle_time = 250;
 263                 use_dma_info = 1;
 264                 break;
 265
 266         case XFER_MW_DMA_0:
 267                 cycle_time = 480;
 268                 break;
 269
 270         case XFER_SW_DMA_2:
 271         case XFER_SW_DMA_1:
 272         case XFER_SW_DMA_0:
 273                 cycle_time = 480;
 274                 break;
 275         }
 276
 277         /*
 278          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 279          * take care to note the values in the ID...
 280          */
 281         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 282                 cycle_time = drive->id->eide_dma_time;
 283
 284         drive->drive_data = cycle_time;
 285
 286         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 287                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 288 }
 289
 290 static void icside_dma_host_set(ide_drive_t *drive, int on)
 291 {
 292 }
 293
 294 static int icside_dma_end(ide_drive_t *drive)
 295 {
 296         ide_hwif_t *hwif = HWIF(drive);
 297         struct icside_state *state = hwif->hwif_data;
 298
 299         drive->waiting_for_dma = 0;
 300
 301         disable_dma(ECARD_DEV(state->dev)->dma);
 302
 303         /* Teardown mappings after DMA has completed. */
 304         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
 305                      hwif->sg_dma_direction);
 306
 307         return get_dma_residue(ECARD_DEV(state->dev)->dma) != 0;
 308 }
 309
 310 static void icside_dma_start(ide_drive_t *drive)
 311 {
 312         ide_hwif_t *hwif = HWIF(drive);
 313         struct icside_state *state = hwif->hwif_data;
 314
 315         /* We can not enable DMA on both channels simultaneously. */
 316         BUG_ON(dma_channel_active(ECARD_DEV(state->dev)->dma));
 317         enable_dma(ECARD_DEV(state->dev)->dma);
 318 }
 319
 320 static int icside_dma_setup(ide_drive_t *drive)
 321 {
 322         ide_hwif_t *hwif = HWIF(drive);
 323         struct icside_state *state = hwif->hwif_data;
 324         struct request *rq = hwif->hwgroup->rq;
 325         unsigned int dma_mode;
 326
 327         if (rq_data_dir(rq))
 328                 dma_mode = DMA_MODE_WRITE;
 329         else
 330                 dma_mode = DMA_MODE_READ;
 331
 332         /*
 333          * We can not enable DMA on both channels.
 334          */
 335         BUG_ON(dma_channel_active(ECARD_DEV(state->dev)->dma));
 336
 337         icside_build_sglist(drive, rq);
 338
 339         /*
 340          * Ensure that we have the right interrupt routed.
 341          */
 342         icside_maskproc(drive, 0);
 343
 344         /*
 345          * Route the DMA signals to the correct interface.
 346          */
 347         writeb(hwif->select_data, hwif->config_data);
 348
 349         /*
 350          * Select the correct timing for this drive.
 351          */
 352         set_dma_speed(ECARD_DEV(state->dev)->dma, drive->drive_data);
 353
 354         /*
 355          * Tell the DMA engine about the SG table and
 356          * data direction.
 357          */
 358         set_dma_sg(ECARD_DEV(state->dev)->dma, hwif->sg_table, hwif->sg_nents);
 359         set_dma_mode(ECARD_DEV(state->dev)->dma, dma_mode);
 360
 361         drive->waiting_for_dma = 1;
 362
 363         return 0;
 364 }
 365
 366 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 367 {
 368         /* issue cmd to drive */
 369         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
 370 }
 371
 372 static int icside_dma_test_irq(ide_drive_t *drive)
 373 {
 374         ide_hwif_t *hwif = HWIF(drive);
 375         struct icside_state *state = hwif->hwif_data;
 376
 377         return readb(state->irq_port +
 378                      (hwif->channel ?
 379                         ICS_ARCIN_V6_INTRSTAT_2 :
 380                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 381 }
 382
 383 static void icside_dma_timeout(ide_drive_t *drive)
 384 {
 385         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 386
 387         if (icside_dma_test_irq(drive))
 388                 return;
 389
 390         ide_dump_status(drive, "DMA timeout", HWIF(drive)->INB(IDE_STATUS_REG));
 391
 392         icside_dma_end(drive);
 393 }
 394
 395 static void icside_dma_lost_irq(ide_drive_t *drive)
 396 {
 397         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 398 }
 399
 400 static void icside_dma_init(ide_hwif_t *hwif)
 401 {
 402         hwif->mwdma_mask        = 7; /* MW0..2 */
 403         hwif->swdma_mask        = 7; /* SW0..2 */
 404
 405         hwif->dmatable_cpu      = NULL;
 406         hwif->dmatable_dma      = 0;
 407         hwif->set_dma_mode      = icside_set_dma_mode;
 408
 409         hwif->dma_host_set      = icside_dma_host_set;
 410         hwif->dma_setup         = icside_dma_setup;
 411         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
 412         hwif->dma_start         = icside_dma_start;
 413         hwif->ide_dma_end       = icside_dma_end;
 414         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 415         hwif->dma_timeout       = icside_dma_timeout;
 416         hwif->dma_lost_irq      = icside_dma_lost_irq;
 417 }
 418 #else
 419 #define icside_dma_init(hwif)   (0)
 420 #endif
 421
 422 static ide_hwif_t *
 423 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 424 {
 425         unsigned long port = (unsigned long)base + info->dataoffset;
 426         ide_hwif_t *hwif;
 427
 428         hwif = ide_find_port(port);
 429         if (hwif) {
 430                 int i;
 431
 432                 /*
 433                  * Ensure we're using MMIO
 434                  */
 435                 default_hwif_mmiops(hwif);
 436                 hwif->mmio = 1;
 437
 438                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 439                         hwif->io_ports[i] = port;
 440                         port += 1 << info->stepping;
 441                 }
 442                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 443                 hwif->irq     = ec->irq;
 444                 hwif->noprobe = 0;
 445                 hwif->chipset = ide_acorn;
 446                 hwif->gendev.parent = &ec->dev;
 447         }
 448
 449         return hwif;
 450 }
 451
 452 static int __init
 453 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 454 {
 455         ide_hwif_t *hwif;
 456         void __iomem *base;
 457         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 458
 459         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 460         if (!base)
 461                 return -ENOMEM;
 462
 463         state->irq_port = base;
 464
 465         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 466         ec->irqmask  = 1;
 467
 468         ecard_setirq(ec, &icside_ops_arcin_v5, state);
 469
 470         /*
 471          * Be on the safe side - disable interrupts
 472          */
 473         icside_irqdisable_arcin_v5(ec, 0);
 474
 475         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 476         if (!hwif)
 477                 return -ENODEV;
 478
 479         state->hwif[0] = hwif;
 480
 481         idx[0] = hwif->index;
 482
 483         ide_device_add(idx);
 484
 485         return 0;
 486 }
 487
 488 static int __init
 489 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 490 {
 491         ide_hwif_t *hwif, *mate;
 492         void __iomem *ioc_base, *easi_base;
 493         unsigned int sel = 0;
 494         int ret;
 495         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 496
 497         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 498         if (!ioc_base) {
 499                 ret = -ENOMEM;
 500                 goto out;
 501         }
 502
 503         easi_base = ioc_base;
 504
 505         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 506                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
 507                 if (!easi_base) {
 508                         ret = -ENOMEM;
 509                         goto out;
 510                 }
 511
 512                 /*
 513                  * Enable access to the EASI region.
 514                  */
 515                 sel = 1 << 5;
 516         }
 517
 518         writeb(sel, ioc_base);
 519
 520         ecard_setirq(ec, &icside_ops_arcin_v6, state);
 521
 522         state->irq_port   = easi_base;
 523         state->ioc_base   = ioc_base;
 524
 525         /*
 526          * Be on the safe side - disable interrupts
 527          */
 528         icside_irqdisable_arcin_v6(ec, 0);
 529
 530         /*
 531          * Find and register the interfaces.
 532          */
 533         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 534         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 535
 536         if (!hwif || !mate) {
 537                 ret = -ENODEV;
 538                 goto out;
 539         }
 540
 541         state->hwif[0]    = hwif;
 542         state->hwif[1]    = mate;
 543
 544         hwif->maskproc    = icside_maskproc;
 545         hwif->channel     = 0;
 546         hwif->hwif_data   = state;
 547         hwif->mate        = mate;
 548         hwif->serialized  = 1;
 549         hwif->config_data = (unsigned long)ioc_base;
 550         hwif->select_data = sel;
 551
 552         mate->maskproc    = icside_maskproc;
 553         mate->channel     = 1;
 554         mate->hwif_data   = state;
 555         mate->mate        = hwif;
 556         mate->serialized  = 1;
 557         mate->config_data = (unsigned long)ioc_base;
 558         mate->select_data = sel | 1;
 559
 560         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 561                 icside_dma_init(hwif);
 562                 icside_dma_init(mate);
 563         }
 564
 565         idx[0] = hwif->index;
 566         idx[1] = mate->index;
 567
 568         ide_device_add(idx);
 569
 570         return 0;
 571
 572  out:
 573         return ret;
 574 }
 575
 576 static int __devinit
 577 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 578 {
 579         struct icside_state *state;
 580         void __iomem *idmem;
 581         int ret;
 582
 583         ret = ecard_request_resources(ec);
 584         if (ret)
 585                 goto out;
 586
 587         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
 588         if (!state) {
 589                 ret = -ENOMEM;
 590                 goto release;
 591         }
 592
 593         state->type     = ICS_TYPE_NOTYPE;
 594         state->dev      = &ec->dev;
 595
 596         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 597         if (idmem) {
 598                 unsigned int type;
 599
 600                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 601                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 602                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 603                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 604                 ecardm_iounmap(ec, idmem);
 605
 606                 state->type = type;
 607         }
 608
 609         switch (state->type) {
 610         case ICS_TYPE_A3IN:
 611                 dev_warn(&ec->dev, "A3IN unsupported\n");
 612                 ret = -ENODEV;
 613                 break;
 614
 615         case ICS_TYPE_A3USER:
 616                 dev_warn(&ec->dev, "A3USER unsupported\n");
 617                 ret = -ENODEV;
 618                 break;
 619
 620         case ICS_TYPE_V5:
 621                 ret = icside_register_v5(state, ec);
 622                 break;
 623
 624         case ICS_TYPE_V6:
 625                 ret = icside_register_v6(state, ec);
 626                 break;
 627
 628         default:
 629                 dev_warn(&ec->dev, "unknown interface type\n");
 630                 ret = -ENODEV;
 631                 break;
 632         }
 633
 634         if (ret == 0) {
 635                 ecard_set_drvdata(ec, state);
 636                 goto out;
 637         }
 638
 639         kfree(state);
 640  release:
 641         ecard_release_resources(ec);
 642  out:
 643         return ret;
 644 }
 645
 646 static void __devexit icside_remove(struct expansion_card *ec)
 647 {
 648         struct icside_state *state = ecard_get_drvdata(ec);
 649
 650         switch (state->type) {
 651         case ICS_TYPE_V5:
 652                 /* FIXME: tell IDE to stop using the interface */
 653
 654                 /* Disable interrupts */
 655                 icside_irqdisable_arcin_v5(ec, 0);
 656                 break;
 657
 658         case ICS_TYPE_V6:
 659                 /* FIXME: tell IDE to stop using the interface */
 660                 if (ec->dma != NO_DMA)
 661                         free_dma(ec->dma);
 662
 663                 /* Disable interrupts */
 664                 icside_irqdisable_arcin_v6(ec, 0);
 665
 666                 /* Reset the ROM pointer/EASI selection */
 667                 writeb(0, state->ioc_base);
 668                 break;
 669         }
 670
 671         ecard_set_drvdata(ec, NULL);
 672
 673         kfree(state);
 674         ecard_release_resources(ec);
 675 }
 676
 677 static void icside_shutdown(struct expansion_card *ec)
 678 {
 679         struct icside_state *state = ecard_get_drvdata(ec);
 680         unsigned long flags;
 681
 682         /*
 683          * Disable interrupts from this card.  We need to do
 684          * this before disabling EASI since we may be accessing
 685          * this register via that region.
 686          */
 687         local_irq_save(flags);
 688         ec->ops->irqdisable(ec, 0);
 689         local_irq_restore(flags);
 690
 691         /*
 692          * Reset the ROM pointer so that we can read the ROM
 693          * after a soft reboot.  This also disables access to
 694          * the IDE taskfile via the EASI region.
 695          */
 696         if (state->ioc_base)
 697                 writeb(0, state->ioc_base);
 698 }
 699
 700 static const struct ecard_id icside_ids[] = {
 701         { MANU_ICS,  PROD_ICS_IDE  },
 702         { MANU_ICS2, PROD_ICS2_IDE },
 703         { 0xffff, 0xffff }
 704 };
 705
 706 static struct ecard_driver icside_driver = {
 707         .probe          = icside_probe,
 708         .remove         = __devexit_p(icside_remove),
 709         .shutdown       = icside_shutdown,
 710         .id_table       = icside_ids,
 711         .drv = {
 712                 .name   = "icside",
 713         },
 714 };
 715
 716 static int __init icside_init(void)
 717 {
 718         return ecard_register_driver(&icside_driver);
 719 }
 720
 721 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 722 MODULE_LICENSE("GPL");
 723 MODULE_DESCRIPTION("ICS IDE driver");
 724
 725 module_init(icside_init);