drivers/ide/arm/icside.c

   1 /*
   2  * linux/drivers/ide/arm/icside.c
   3  *
   4  * Copyright (c) 1996-2004 Russell King.
   5  *
   6  * Please note that this platform does not support 32-bit IDE IO.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/module.h>
  11 #include <linux/ioport.h>
  12 #include <linux/slab.h>
  13 #include <linux/blkdev.h>
  14 #include <linux/errno.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/device.h>
  19 #include <linux/init.h>
  20 #include <linux/scatterlist.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/dma.h>
  24 #include <asm/ecard.h>
  25
  26 #define ICS_IDENT_OFFSET                0x2280
  27
  28 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  29 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  30 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  31 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  32 #define ICS_ARCIN_V5_IDESTEPPING        6
  33
  34 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  35 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  36 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  37 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  38 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  39 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  40 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  41 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  42 #define ICS_ARCIN_V6_IDESTEPPING        6
  43
  44 struct cardinfo {
  45         unsigned int dataoffset;
  46         unsigned int ctrloffset;
  47         unsigned int stepping;
  48 };
  49
  50 static struct cardinfo icside_cardinfo_v5 = {
  51         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  52         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  53         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  54 };
  55
  56 static struct cardinfo icside_cardinfo_v6_1 = {
  57         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  58         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  59         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  60 };
  61
  62 static struct cardinfo icside_cardinfo_v6_2 = {
  63         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  64         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  65         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  66 };
  67
  68 struct icside_state {
  69         unsigned int channel;
  70         unsigned int enabled;
  71         void __iomem *irq_port;
  72         void __iomem *ioc_base;
  73         unsigned int type;
  74         /* parent device... until the IDE core gets one of its own */
  75         struct device *dev;
  76         ide_hwif_t *hwif[2];
  77 };
  78
  79 #define ICS_TYPE_A3IN   0
  80 #define ICS_TYPE_A3USER 1
  81 #define ICS_TYPE_V6     3
  82 #define ICS_TYPE_V5     15
  83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  84
  85 /* ---------------- Version 5 PCB Support Functions --------------------- */
  86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  87  * Purpose  : enable interrupts from card
  88  */
  89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  90 {
  91         struct icside_state *state = ec->irq_data;
  92
  93         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  94 }
  95
  96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  97  * Purpose  : disable interrupts from card
  98  */
  99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 100 {
 101         struct icside_state *state = ec->irq_data;
 102
 103         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 104 }
 105
 106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 107         .irqenable      = icside_irqenable_arcin_v5,
 108         .irqdisable     = icside_irqdisable_arcin_v5,
 109 };
 110
 111
 112 /* ---------------- Version 6 PCB Support Functions --------------------- */
 113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 114  * Purpose  : enable interrupts from card
 115  */
 116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 117 {
 118         struct icside_state *state = ec->irq_data;
 119         void __iomem *base = state->irq_port;
 120
 121         state->enabled = 1;
 122
 123         switch (state->channel) {
 124         case 0:
 125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 126                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 127                 break;
 128         case 1:
 129                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 130                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 131                 break;
 132         }
 133 }
 134
 135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 136  * Purpose  : disable interrupts from card
 137  */
 138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 139 {
 140         struct icside_state *state = ec->irq_data;
 141
 142         state->enabled = 0;
 143
 144         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 146 }
 147
 148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 149  * Purpose  : detect an active interrupt from card
 150  */
 151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 152 {
 153         struct icside_state *state = ec->irq_data;
 154
 155         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 156                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 157 }
 158
 159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 160         .irqenable      = icside_irqenable_arcin_v6,
 161         .irqdisable     = icside_irqdisable_arcin_v6,
 162         .irqpending     = icside_irqpending_arcin_v6,
 163 };
 164
 165 /*
 166  * Handle routing of interrupts.  This is called before
 167  * we write the command to the drive.
 168  */
 169 static void icside_maskproc(ide_drive_t *drive, int mask)
 170 {
 171         ide_hwif_t *hwif = HWIF(drive);
 172         struct icside_state *state = hwif->hwif_data;
 173         unsigned long flags;
 174
 175         local_irq_save(flags);
 176
 177         state->channel = hwif->channel;
 178
 179         if (state->enabled && !mask) {
 180                 switch (hwif->channel) {
 181                 case 0:
 182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 184                         break;
 185                 case 1:
 186                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 187                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 188                         break;
 189                 }
 190         } else {
 191                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 193         }
 194
 195         local_irq_restore(flags);
 196 }
 197
 198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 199 /*
 200  * SG-DMA support.
 201  *
 202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 203  * There is only one DMA controller per card, which means that only
 204  * one drive can be accessed at one time.  NOTE! We do not enforce that
 205  * here, but we rely on the main IDE driver spotting that both
 206  * interfaces use the same IRQ, which should guarantee this.
 207  */
 208
 209 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
 210 {
 211         ide_hwif_t *hwif = drive->hwif;
 212         struct icside_state *state = hwif->hwif_data;
 213         struct scatterlist *sg = hwif->sg_table;
 214
 215         ide_map_sg(drive, rq);
 216
 217         if (rq_data_dir(rq) == READ)
 218                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 219         else
 220                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 221
 222         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
 223                                     hwif->sg_dma_direction);
 224 }
 225
 226 /*
 227  * Configure the IOMD to give the appropriate timings for the transfer
 228  * mode being requested.  We take the advice of the ATA standards, and
 229  * calculate the cycle time based on the transfer mode, and the EIDE
 230  * MW DMA specs that the drive provides in the IDENTIFY command.
 231  *
 232  * We have the following IOMD DMA modes to choose from:
 233  *
 234  *      Type    Active          Recovery        Cycle
 235  *      A       250 (250)       312 (550)       562 (800)
 236  *      B       187             250             437
 237  *      C       125 (125)       125 (375)       250 (500)
 238  *      D       62              125             187
 239  *
 240  * (figures in brackets are actual measured timings)
 241  *
 242  * However, we also need to take care of the read/write active and
 243  * recovery timings:
 244  *
 245  *                      Read    Write
 246  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 247  *      MW0     215     50      215     480     A
 248  *      MW1     80      50      50      150     C
 249  *      MW2     70      25      25      120     C
 250  */
 251 static int icside_set_speed(ide_drive_t *drive, const u8 xfer_mode)
 252 {
 253         int cycle_time, use_dma_info = 0;
 254
 255         switch (xfer_mode) {
 256         case XFER_MW_DMA_2:
 257                 cycle_time = 250;
 258                 use_dma_info = 1;
 259                 break;
 260
 261         case XFER_MW_DMA_1:
 262                 cycle_time = 250;
 263                 use_dma_info = 1;
 264                 break;
 265
 266         case XFER_MW_DMA_0:
 267                 cycle_time = 480;
 268                 break;
 269
 270         case XFER_SW_DMA_2:
 271         case XFER_SW_DMA_1:
 272         case XFER_SW_DMA_0:
 273                 cycle_time = 480;
 274                 break;
 275         default:
 276                 return 1;
 277         }
 278
 279         /*
 280          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 281          * take care to note the values in the ID...
 282          */
 283         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 284                 cycle_time = drive->id->eide_dma_time;
 285
 286         drive->drive_data = cycle_time;
 287
 288         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 289                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 290
 291         return ide_config_drive_speed(drive, xfer_mode);
 292 }
 293
 294 static void icside_dma_host_off(ide_drive_t *drive)
 295 {
 296 }
 297
 298 static void icside_dma_off_quietly(ide_drive_t *drive)
 299 {
 300         drive->using_dma = 0;
 301 }
 302
 303 static void icside_dma_host_on(ide_drive_t *drive)
 304 {
 305 }
 306
 307 static int icside_dma_on(ide_drive_t *drive)
 308 {
 309         drive->using_dma = 1;
 310
 311         return 0;
 312 }
 313
 314 static int icside_dma_check(ide_drive_t *drive)
 315 {
 316         struct hd_driveid *id = drive->id;
 317         ide_hwif_t *hwif = HWIF(drive);
 318         int xfer_mode = 0;
 319
 320         if (!(id->capability & 1) || !hwif->autodma)
 321                 goto out;
 322
 323         /*
 324          * Consult the list of known "bad" drives
 325          */
 326         if (__ide_dma_bad_drive(drive))
 327                 goto out;
 328
 329         /*
 330          * Enable DMA on any drive that has multiword DMA
 331          */
 332         if (id->field_valid & 2) {
 333                 xfer_mode = ide_max_dma_mode(drive);
 334                 goto out;
 335         }
 336
 337         /*
 338          * Consult the list of known "good" drives
 339          */
 340         if (__ide_dma_good_drive(drive)) {
 341                 if (id->eide_dma_time > 150)
 342                         goto out;
 343                 xfer_mode = XFER_MW_DMA_1;
 344         }
 345
 346 out:
 347         if (xfer_mode == 0)
 348                 return -1;
 349
 350         return icside_set_speed(drive, xfer_mode) ? -1 : 0;
 351 }
 352
 353 static int icside_dma_end(ide_drive_t *drive)
 354 {
 355         ide_hwif_t *hwif = HWIF(drive);
 356         struct icside_state *state = hwif->hwif_data;
 357
 358         drive->waiting_for_dma = 0;
 359
 360         disable_dma(hwif->hw.dma);
 361
 362         /* Teardown mappings after DMA has completed. */
 363         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
 364                      hwif->sg_dma_direction);
 365
 366         return get_dma_residue(hwif->hw.dma) != 0;
 367 }
 368
 369 static void icside_dma_start(ide_drive_t *drive)
 370 {
 371         ide_hwif_t *hwif = HWIF(drive);
 372
 373         /* We can not enable DMA on both channels simultaneously. */
 374         BUG_ON(dma_channel_active(hwif->hw.dma));
 375         enable_dma(hwif->hw.dma);
 376 }
 377
 378 static int icside_dma_setup(ide_drive_t *drive)
 379 {
 380         ide_hwif_t *hwif = HWIF(drive);
 381         struct request *rq = hwif->hwgroup->rq;
 382         unsigned int dma_mode;
 383
 384         if (rq_data_dir(rq))
 385                 dma_mode = DMA_MODE_WRITE;
 386         else
 387                 dma_mode = DMA_MODE_READ;
 388
 389         /*
 390          * We can not enable DMA on both channels.
 391          */
 392         BUG_ON(dma_channel_active(hwif->hw.dma));
 393
 394         icside_build_sglist(drive, rq);
 395
 396         /*
 397          * Ensure that we have the right interrupt routed.
 398          */
 399         icside_maskproc(drive, 0);
 400
 401         /*
 402          * Route the DMA signals to the correct interface.
 403          */
 404         writeb(hwif->select_data, hwif->config_data);
 405
 406         /*
 407          * Select the correct timing for this drive.
 408          */
 409         set_dma_speed(hwif->hw.dma, drive->drive_data);
 410
 411         /*
 412          * Tell the DMA engine about the SG table and
 413          * data direction.
 414          */
 415         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
 416         set_dma_mode(hwif->hw.dma, dma_mode);
 417
 418         drive->waiting_for_dma = 1;
 419
 420         return 0;
 421 }
 422
 423 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 424 {
 425         /* issue cmd to drive */
 426         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
 427 }
 428
 429 static int icside_dma_test_irq(ide_drive_t *drive)
 430 {
 431         ide_hwif_t *hwif = HWIF(drive);
 432         struct icside_state *state = hwif->hwif_data;
 433
 434         return readb(state->irq_port +
 435                      (hwif->channel ?
 436                         ICS_ARCIN_V6_INTRSTAT_2 :
 437                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 438 }
 439
 440 static void icside_dma_timeout(ide_drive_t *drive)
 441 {
 442         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 443
 444         if (icside_dma_test_irq(drive))
 445                 return;
 446
 447         ide_dump_status(drive, "DMA timeout", HWIF(drive)->INB(IDE_STATUS_REG));
 448
 449         icside_dma_end(drive);
 450 }
 451
 452 static void icside_dma_lost_irq(ide_drive_t *drive)
 453 {
 454         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 455 }
 456
 457 static void icside_dma_init(ide_hwif_t *hwif)
 458 {
 459         printk("    %s: SG-DMA", hwif->name);
 460
 461         hwif->atapi_dma         = 1;
 462         hwif->mwdma_mask        = 7; /* MW0..2 */
 463         hwif->swdma_mask        = 7; /* SW0..2 */
 464
 465         hwif->dmatable_cpu      = NULL;
 466         hwif->dmatable_dma      = 0;
 467         hwif->speedproc         = icside_set_speed;
 468         hwif->autodma           = 1;
 469
 470         hwif->ide_dma_check     = icside_dma_check;
 471         hwif->dma_host_off      = icside_dma_host_off;
 472         hwif->dma_off_quietly   = icside_dma_off_quietly;
 473         hwif->dma_host_on       = icside_dma_host_on;
 474         hwif->ide_dma_on        = icside_dma_on;
 475         hwif->dma_setup         = icside_dma_setup;
 476         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
 477         hwif->dma_start         = icside_dma_start;
 478         hwif->ide_dma_end       = icside_dma_end;
 479         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 480         hwif->dma_timeout       = icside_dma_timeout;
 481         hwif->dma_lost_irq      = icside_dma_lost_irq;
 482
 483         hwif->drives[0].autodma = hwif->autodma;
 484         hwif->drives[1].autodma = hwif->autodma;
 485
 486         printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
 487 }
 488 #else
 489 #define icside_dma_init(hwif)   (0)
 490 #endif
 491
 492 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
 493 {
 494         ide_hwif_t *hwif;
 495         int index;
 496
 497         for (index = 0; index < MAX_HWIFS; ++index) {
 498                 hwif = &ide_hwifs[index];
 499                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
 500                         goto found;
 501         }
 502
 503         for (index = 0; index < MAX_HWIFS; ++index) {
 504                 hwif = &ide_hwifs[index];
 505                 if (!hwif->io_ports[IDE_DATA_OFFSET])
 506                         goto found;
 507         }
 508
 509         hwif = NULL;
 510 found:
 511         return hwif;
 512 }
 513
 514 static ide_hwif_t *
 515 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 516 {
 517         unsigned long port = (unsigned long)base + info->dataoffset;
 518         ide_hwif_t *hwif;
 519
 520         hwif = icside_find_hwif(port);
 521         if (hwif) {
 522                 int i;
 523
 524                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
 525
 526                 /*
 527                  * Ensure we're using MMIO
 528                  */
 529                 default_hwif_mmiops(hwif);
 530                 hwif->mmio = 1;
 531
 532                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 533                         hwif->hw.io_ports[i] = port;
 534                         hwif->io_ports[i] = port;
 535                         port += 1 << info->stepping;
 536                 }
 537                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 538                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 539                 hwif->hw.irq  = ec->irq;
 540                 hwif->irq     = ec->irq;
 541                 hwif->noprobe = 0;
 542                 hwif->chipset = ide_acorn;
 543                 hwif->gendev.parent = &ec->dev;
 544         }
 545
 546         return hwif;
 547 }
 548
 549 static int __init
 550 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 551 {
 552         ide_hwif_t *hwif;
 553         void __iomem *base;
 554
 555         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 556         if (!base)
 557                 return -ENOMEM;
 558
 559         state->irq_port = base;
 560
 561         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 562         ec->irqmask  = 1;
 563
 564         ecard_setirq(ec, &icside_ops_arcin_v5, state);
 565
 566         /*
 567          * Be on the safe side - disable interrupts
 568          */
 569         icside_irqdisable_arcin_v5(ec, 0);
 570
 571         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 572         if (!hwif)
 573                 return -ENODEV;
 574
 575         state->hwif[0] = hwif;
 576
 577         probe_hwif_init(hwif);
 578
 579         ide_proc_register_port(hwif);
 580
 581         return 0;
 582 }
 583
 584 static int __init
 585 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 586 {
 587         ide_hwif_t *hwif, *mate;
 588         void __iomem *ioc_base, *easi_base;
 589         unsigned int sel = 0;
 590         int ret;
 591
 592         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 593         if (!ioc_base) {
 594                 ret = -ENOMEM;
 595                 goto out;
 596         }
 597
 598         easi_base = ioc_base;
 599
 600         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 601                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
 602                 if (!easi_base) {
 603                         ret = -ENOMEM;
 604                         goto out;
 605                 }
 606
 607                 /*
 608                  * Enable access to the EASI region.
 609                  */
 610                 sel = 1 << 5;
 611         }
 612
 613         writeb(sel, ioc_base);
 614
 615         ecard_setirq(ec, &icside_ops_arcin_v6, state);
 616
 617         state->irq_port   = easi_base;
 618         state->ioc_base   = ioc_base;
 619
 620         /*
 621          * Be on the safe side - disable interrupts
 622          */
 623         icside_irqdisable_arcin_v6(ec, 0);
 624
 625         /*
 626          * Find and register the interfaces.
 627          */
 628         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 629         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 630
 631         if (!hwif || !mate) {
 632                 ret = -ENODEV;
 633                 goto out;
 634         }
 635
 636         state->hwif[0]    = hwif;
 637         state->hwif[1]    = mate;
 638
 639         hwif->maskproc    = icside_maskproc;
 640         hwif->channel     = 0;
 641         hwif->hwif_data   = state;
 642         hwif->mate        = mate;
 643         hwif->serialized  = 1;
 644         hwif->config_data = (unsigned long)ioc_base;
 645         hwif->select_data = sel;
 646         hwif->hw.dma      = ec->dma;
 647
 648         mate->maskproc    = icside_maskproc;
 649         mate->channel     = 1;
 650         mate->hwif_data   = state;
 651         mate->mate        = hwif;
 652         mate->serialized  = 1;
 653         mate->config_data = (unsigned long)ioc_base;
 654         mate->select_data = sel | 1;
 655         mate->hw.dma      = ec->dma;
 656
 657         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 658                 icside_dma_init(hwif);
 659                 icside_dma_init(mate);
 660         }
 661
 662         probe_hwif_init(hwif);
 663         probe_hwif_init(mate);
 664
 665         ide_proc_register_port(hwif);
 666         ide_proc_register_port(mate);
 667
 668         return 0;
 669
 670  out:
 671         return ret;
 672 }
 673
 674 static int __devinit
 675 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 676 {
 677         struct icside_state *state;
 678         void __iomem *idmem;
 679         int ret;
 680
 681         ret = ecard_request_resources(ec);
 682         if (ret)
 683                 goto out;
 684
 685         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
 686         if (!state) {
 687                 ret = -ENOMEM;
 688                 goto release;
 689         }
 690
 691         state->type     = ICS_TYPE_NOTYPE;
 692         state->dev      = &ec->dev;
 693
 694         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 695         if (idmem) {
 696                 unsigned int type;
 697
 698                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 699                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 700                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 701                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 702                 ecardm_iounmap(ec, idmem);
 703
 704                 state->type = type;
 705         }
 706
 707         switch (state->type) {
 708         case ICS_TYPE_A3IN:
 709                 dev_warn(&ec->dev, "A3IN unsupported\n");
 710                 ret = -ENODEV;
 711                 break;
 712
 713         case ICS_TYPE_A3USER:
 714                 dev_warn(&ec->dev, "A3USER unsupported\n");
 715                 ret = -ENODEV;
 716                 break;
 717
 718         case ICS_TYPE_V5:
 719                 ret = icside_register_v5(state, ec);
 720                 break;
 721
 722         case ICS_TYPE_V6:
 723                 ret = icside_register_v6(state, ec);
 724                 break;
 725
 726         default:
 727                 dev_warn(&ec->dev, "unknown interface type\n");
 728                 ret = -ENODEV;
 729                 break;
 730         }
 731
 732         if (ret == 0) {
 733                 ecard_set_drvdata(ec, state);
 734                 goto out;
 735         }
 736
 737         kfree(state);
 738  release:
 739         ecard_release_resources(ec);
 740  out:
 741         return ret;
 742 }
 743
 744 static void __devexit icside_remove(struct expansion_card *ec)
 745 {
 746         struct icside_state *state = ecard_get_drvdata(ec);
 747
 748         switch (state->type) {
 749         case ICS_TYPE_V5:
 750                 /* FIXME: tell IDE to stop using the interface */
 751
 752                 /* Disable interrupts */
 753                 icside_irqdisable_arcin_v5(ec, 0);
 754                 break;
 755
 756         case ICS_TYPE_V6:
 757                 /* FIXME: tell IDE to stop using the interface */
 758                 if (ec->dma != NO_DMA)
 759                         free_dma(ec->dma);
 760
 761                 /* Disable interrupts */
 762                 icside_irqdisable_arcin_v6(ec, 0);
 763
 764                 /* Reset the ROM pointer/EASI selection */
 765                 writeb(0, state->ioc_base);
 766                 break;
 767         }
 768
 769         ecard_set_drvdata(ec, NULL);
 770
 771         kfree(state);
 772         ecard_release_resources(ec);
 773 }
 774
 775 static void icside_shutdown(struct expansion_card *ec)
 776 {
 777         struct icside_state *state = ecard_get_drvdata(ec);
 778         unsigned long flags;
 779
 780         /*
 781          * Disable interrupts from this card.  We need to do
 782          * this before disabling EASI since we may be accessing
 783          * this register via that region.
 784          */
 785         local_irq_save(flags);
 786         ec->ops->irqdisable(ec, 0);
 787         local_irq_restore(flags);
 788
 789         /*
 790          * Reset the ROM pointer so that we can read the ROM
 791          * after a soft reboot.  This also disables access to
 792          * the IDE taskfile via the EASI region.
 793          */
 794         if (state->ioc_base)
 795                 writeb(0, state->ioc_base);
 796 }
 797
 798 static const struct ecard_id icside_ids[] = {
 799         { MANU_ICS,  PROD_ICS_IDE  },
 800         { MANU_ICS2, PROD_ICS2_IDE },
 801         { 0xffff, 0xffff }
 802 };
 803
 804 static struct ecard_driver icside_driver = {
 805         .probe          = icside_probe,
 806         .remove         = __devexit_p(icside_remove),
 807         .shutdown       = icside_shutdown,
 808         .id_table       = icside_ids,
 809         .drv = {
 810                 .name   = "icside",
 811         },
 812 };
 813
 814 static int __init icside_init(void)
 815 {
 816         return ecard_register_driver(&icside_driver);
 817 }
 818
 819 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 820 MODULE_LICENSE("GPL");
 821 MODULE_DESCRIPTION("ICS IDE driver");
 822
 823 module_init(icside_init);