2 * linux/drivers/ide/pci/hpt366.c Version 0.45 May 27, 2006
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc.
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
21 * Note that final HPT370 support was done by force extraction of GPL.
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * Alan Cox <alan@redhat.com>
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - avoid calibrating PLL twice as the second time results in a wrong PCI
64 * frequency and thus in the wrong timings for the secondary channel
65 * - disable UltraATA/133 for HPT372 and UltraATA/100 for HPT370 by default
66 * as the ATA clock being used does not allow for this speed anyway
67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
68 * - HPT371/N are single channel chips, so avoid touching the primary channel
69 * which exists only virtually (there's no pins for it)
70 * - fix/remove bad/unused timing tables and use one set of tables for the whole
71 * HPT37x chip family; save space by introducing the separate transfer mode
72 * table in which the mode lookup is done
73 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
74 * the wrong PCI frequency since DPLL has already been calibrated by BIOS
75 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
76 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
77 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
78 * they tamper with its fields
79 * - prefix the driver startup messages with the real chip name
80 * - claim the extra 240 bytes of I/O space for all chips
81 * - optimize the rate masking/filtering and the drive list lookup code
82 * - use pci_get_slot() to get to the function 1 of HPT36x/374
88 #include <linux/types.h>
89 #include <linux/module.h>
90 #include <linux/kernel.h>
91 #include <linux/delay.h>
92 #include <linux/timer.h>
94 #include <linux/ioport.h>
95 #include <linux/blkdev.h>
96 #include <linux/hdreg.h>
98 #include <linux/interrupt.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ide.h>
103 #include <asm/uaccess.h>
107 /* various tuning parameters */
108 #define HPT_RESET_STATE_ENGINE
109 #undef HPT_DELAY_INTERRUPT
110 #define HPT_SERIALIZE_IO 0
112 static const char *quirk_drives[] = {
113 "QUANTUM FIREBALLlct08 08",
114 "QUANTUM FIREBALLP KA6.4",
115 "QUANTUM FIREBALLP LM20.4",
116 "QUANTUM FIREBALLP LM20.5",
120 static const char *bad_ata100_5[] = {
139 static const char *bad_ata66_4[] = {
158 static const char *bad_ata66_3[] = {
163 static const char *bad_ata33[] = {
164 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
165 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
166 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
168 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
169 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
170 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
174 static u8 xfer_speeds[] = {
194 /* Key for bus clock timings
197 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
199 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
201 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
203 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
205 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
206 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
207 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
209 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
210 * task file register access.
213 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
218 static u32 forty_base_hpt36x[] = {
219 /* XFER_UDMA_6 */ 0x900fd943,
220 /* XFER_UDMA_5 */ 0x900fd943,
221 /* XFER_UDMA_4 */ 0x900fd943,
222 /* XFER_UDMA_3 */ 0x900ad943,
223 /* XFER_UDMA_2 */ 0x900bd943,
224 /* XFER_UDMA_1 */ 0x9008d943,
225 /* XFER_UDMA_0 */ 0x9008d943,
227 /* XFER_MW_DMA_2 */ 0xa008d943,
228 /* XFER_MW_DMA_1 */ 0xa010d955,
229 /* XFER_MW_DMA_0 */ 0xa010d9fc,
231 /* XFER_PIO_4 */ 0xc008d963,
232 /* XFER_PIO_3 */ 0xc010d974,
233 /* XFER_PIO_2 */ 0xc010d997,
234 /* XFER_PIO_1 */ 0xc010d9c7,
235 /* XFER_PIO_0 */ 0xc018d9d9
238 static u32 thirty_three_base_hpt36x[] = {
239 /* XFER_UDMA_6 */ 0x90c9a731,
240 /* XFER_UDMA_5 */ 0x90c9a731,
241 /* XFER_UDMA_4 */ 0x90c9a731,
242 /* XFER_UDMA_3 */ 0x90cfa731,
243 /* XFER_UDMA_2 */ 0x90caa731,
244 /* XFER_UDMA_1 */ 0x90cba731,
245 /* XFER_UDMA_0 */ 0x90c8a731,
247 /* XFER_MW_DMA_2 */ 0xa0c8a731,
248 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
249 /* XFER_MW_DMA_0 */ 0xa0c8a797,
251 /* XFER_PIO_4 */ 0xc0c8a731,
252 /* XFER_PIO_3 */ 0xc0c8a742,
253 /* XFER_PIO_2 */ 0xc0d0a753,
254 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
255 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
258 static u32 twenty_five_base_hpt36x[] = {
259 /* XFER_UDMA_6 */ 0x90c98521,
260 /* XFER_UDMA_5 */ 0x90c98521,
261 /* XFER_UDMA_4 */ 0x90c98521,
262 /* XFER_UDMA_3 */ 0x90cf8521,
263 /* XFER_UDMA_2 */ 0x90cf8521,
264 /* XFER_UDMA_1 */ 0x90cb8521,
265 /* XFER_UDMA_0 */ 0x90cb8521,
267 /* XFER_MW_DMA_2 */ 0xa0ca8521,
268 /* XFER_MW_DMA_1 */ 0xa0ca8532,
269 /* XFER_MW_DMA_0 */ 0xa0ca8575,
271 /* XFER_PIO_4 */ 0xc0ca8521,
272 /* XFER_PIO_3 */ 0xc0ca8532,
273 /* XFER_PIO_2 */ 0xc0ca8542,
274 /* XFER_PIO_1 */ 0xc0d08572,
275 /* XFER_PIO_0 */ 0xc0d08585
278 static u32 thirty_three_base_hpt37x[] = {
279 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
280 /* XFER_UDMA_5 */ 0x12446231,
281 /* XFER_UDMA_4 */ 0x12446231,
282 /* XFER_UDMA_3 */ 0x126c6231,
283 /* XFER_UDMA_2 */ 0x12486231,
284 /* XFER_UDMA_1 */ 0x124c6233,
285 /* XFER_UDMA_0 */ 0x12506297,
287 /* XFER_MW_DMA_2 */ 0x22406c31,
288 /* XFER_MW_DMA_1 */ 0x22406c33,
289 /* XFER_MW_DMA_0 */ 0x22406c97,
291 /* XFER_PIO_4 */ 0x06414e31,
292 /* XFER_PIO_3 */ 0x06414e42,
293 /* XFER_PIO_2 */ 0x06414e53,
294 /* XFER_PIO_1 */ 0x06814e93,
295 /* XFER_PIO_0 */ 0x06814ea7
298 static u32 fifty_base_hpt37x[] = {
299 /* XFER_UDMA_6 */ 0x12848242,
300 /* XFER_UDMA_5 */ 0x12848242,
301 /* XFER_UDMA_4 */ 0x12ac8242,
302 /* XFER_UDMA_3 */ 0x128c8242,
303 /* XFER_UDMA_2 */ 0x120c8242,
304 /* XFER_UDMA_1 */ 0x12148254,
305 /* XFER_UDMA_0 */ 0x121882ea,
307 /* XFER_MW_DMA_2 */ 0x22808242,
308 /* XFER_MW_DMA_1 */ 0x22808254,
309 /* XFER_MW_DMA_0 */ 0x228082ea,
311 /* XFER_PIO_4 */ 0x0a81f442,
312 /* XFER_PIO_3 */ 0x0a81f443,
313 /* XFER_PIO_2 */ 0x0a81f454,
314 /* XFER_PIO_1 */ 0x0ac1f465,
315 /* XFER_PIO_0 */ 0x0ac1f48a
318 static u32 sixty_six_base_hpt37x[] = {
319 /* XFER_UDMA_6 */ 0x1c869c62,
320 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
321 /* XFER_UDMA_4 */ 0x1c8a9c62,
322 /* XFER_UDMA_3 */ 0x1c8e9c62,
323 /* XFER_UDMA_2 */ 0x1c929c62,
324 /* XFER_UDMA_1 */ 0x1c9a9c62,
325 /* XFER_UDMA_0 */ 0x1c829c62,
327 /* XFER_MW_DMA_2 */ 0x2c829c62,
328 /* XFER_MW_DMA_1 */ 0x2c829c66,
329 /* XFER_MW_DMA_0 */ 0x2c829d2e,
331 /* XFER_PIO_4 */ 0x0c829c62,
332 /* XFER_PIO_3 */ 0x0c829c84,
333 /* XFER_PIO_2 */ 0x0c829ca6,
334 /* XFER_PIO_1 */ 0x0d029d26,
335 /* XFER_PIO_0 */ 0x0d029d5e
338 #define HPT366_DEBUG_DRIVE_INFO 0
339 #define HPT374_ALLOW_ATA133_6 0
340 #define HPT371_ALLOW_ATA133_6 0
341 #define HPT302_ALLOW_ATA133_6 0
342 #define HPT372_ALLOW_ATA133_6 0
343 #define HPT370_ALLOW_ATA100_5 0
344 #define HPT366_ALLOW_ATA66_4 1
345 #define HPT366_ALLOW_ATA66_3 1
346 #define HPT366_MAX_DEVS 8
348 #define F_LOW_PCI_33 0x23
349 #define F_LOW_PCI_40 0x29
350 #define F_LOW_PCI_50 0x2d
351 #define F_LOW_PCI_66 0x42
354 * Hold all the highpoint quirks and revision information in one
360 u8 max_mode; /* Speeds allowed */
361 u8 revision; /* Chipset revision */
362 u8 flags; /* Chipset properties */
371 * This wants fixing so that we do everything not by revision
372 * (which breaks on the newest chips) but by creating an
373 * enumeration of chip variants and using that
376 static __devinit u8 hpt_revision(struct pci_dev *dev)
380 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
382 switch(dev->device) {
383 /* Remap new 372N onto 372 */
384 case PCI_DEVICE_ID_TTI_HPT372N:
385 rev = PCI_DEVICE_ID_TTI_HPT372;
387 case PCI_DEVICE_ID_TTI_HPT374:
388 rev = PCI_DEVICE_ID_TTI_HPT374;
390 case PCI_DEVICE_ID_TTI_HPT371:
391 rev = PCI_DEVICE_ID_TTI_HPT371;
393 case PCI_DEVICE_ID_TTI_HPT302:
394 rev = PCI_DEVICE_ID_TTI_HPT302;
396 case PCI_DEVICE_ID_TTI_HPT372:
397 rev = PCI_DEVICE_ID_TTI_HPT372;
405 static int check_in_drive_list(ide_drive_t *drive, const char **list)
407 struct hd_driveid *id = drive->id;
410 if (!strcmp(*list++,id->model))
415 static u8 hpt3xx_ratemask(ide_drive_t *drive)
417 struct hpt_info *info = ide_get_hwifdata(HWIF(drive));
418 u8 mode = info->max_mode;
420 if (!eighty_ninty_three(drive) && mode)
421 mode = min(mode, (u8)1);
426 * Note for the future; the SATA hpt37x we must set
427 * either PIO or UDMA modes 0,4,5
430 static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
432 struct hpt_info *info = ide_get_hwifdata(HWIF(drive));
433 u8 mode = hpt3xx_ratemask(drive);
435 if (drive->media != ide_disk)
436 return min(speed, (u8)XFER_PIO_4);
440 speed = min(speed, (u8)XFER_UDMA_6);
443 speed = min(speed, (u8)XFER_UDMA_5);
444 if (info->revision >= 5)
446 if (!check_in_drive_list(drive, bad_ata100_5))
447 goto check_bad_ata33;
450 speed = min_t(u8, speed, XFER_UDMA_4);
452 * CHECK ME, Does this need to be set to 5 ??
454 if (info->revision >= 3)
455 goto check_bad_ata33;
456 if (HPT366_ALLOW_ATA66_4 &&
457 !check_in_drive_list(drive, bad_ata66_4))
458 goto check_bad_ata33;
460 speed = min_t(u8, speed, XFER_UDMA_3);
461 if (HPT366_ALLOW_ATA66_3 &&
462 !check_in_drive_list(drive, bad_ata66_3))
463 goto check_bad_ata33;
466 speed = min_t(u8, speed, XFER_UDMA_2);
469 if (info->revision >= 4)
471 if (!check_in_drive_list(drive, bad_ata33))
476 speed = min_t(u8, speed, XFER_MW_DMA_2);
482 static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
487 * Lookup the transfer mode table to get the index into
490 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
492 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
493 if (xfer_speeds[i] == speed)
495 return chipset_table[i];
498 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
500 ide_hwif_t *hwif = drive->hwif;
501 struct pci_dev *dev = hwif->pci_dev;
502 struct hpt_info *info = ide_get_hwifdata(hwif);
503 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
504 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
505 u8 regfast = (hwif->channel) ? 0x55 : 0x51;
507 u32 reg1 = 0, reg2 = 0;
510 * Disable the "fast interrupt" prediction.
512 pci_read_config_byte(dev, regfast, &drive_fast);
513 if (drive_fast & 0x80)
514 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
516 reg2 = pci_bus_clock_list(speed, info->speed);
519 * Disable on-chip PIO FIFO/buffer
520 * (to avoid problems handling I/O errors later)
522 pci_read_config_dword(dev, regtime, ®1);
523 if (speed >= XFER_MW_DMA_0) {
524 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
526 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
530 pci_write_config_dword(dev, regtime, reg2);
532 return ide_config_drive_speed(drive, speed);
535 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
537 ide_hwif_t *hwif = drive->hwif;
538 struct pci_dev *dev = hwif->pci_dev;
539 struct hpt_info *info = ide_get_hwifdata(hwif);
540 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
541 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
542 u8 drive_pci = 0x40 + (drive->dn * 4);
543 u8 new_fast = 0, drive_fast = 0;
544 u32 list_conf = 0, drive_conf = 0;
545 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
548 * Disable the "fast interrupt" prediction.
549 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
551 pci_read_config_byte(dev, regfast, &drive_fast);
552 new_fast = drive_fast;
556 #ifdef HPT_DELAY_INTERRUPT
560 if ((new_fast & 0x01) == 0)
563 if (new_fast != drive_fast)
564 pci_write_config_byte(dev, regfast, new_fast);
566 list_conf = pci_bus_clock_list(speed, info->speed);
568 pci_read_config_dword(dev, drive_pci, &drive_conf);
569 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
571 if (speed < XFER_MW_DMA_0)
572 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
573 pci_write_config_dword(dev, drive_pci, list_conf);
575 return ide_config_drive_speed(drive, speed);
578 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
580 ide_hwif_t *hwif = drive->hwif;
581 struct pci_dev *dev = hwif->pci_dev;
582 struct hpt_info *info = ide_get_hwifdata(hwif);
583 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
584 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
585 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
586 u32 list_conf = 0, drive_conf = 0;
587 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
590 * Disable the "fast interrupt" prediction.
591 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
593 pci_read_config_byte(dev, regfast, &drive_fast);
595 pci_write_config_byte(dev, regfast, drive_fast);
597 list_conf = pci_bus_clock_list(speed, info->speed);
598 pci_read_config_dword(dev, drive_pci, &drive_conf);
599 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
600 if (speed < XFER_MW_DMA_0)
601 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
602 pci_write_config_dword(dev, drive_pci, list_conf);
604 return ide_config_drive_speed(drive, speed);
607 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
609 ide_hwif_t *hwif = drive->hwif;
610 struct hpt_info *info = ide_get_hwifdata(hwif);
612 if (info->revision >= 8)
613 return hpt372_tune_chipset(drive, speed); /* not a typo */
614 else if (info->revision >= 5)
615 return hpt372_tune_chipset(drive, speed);
616 else if (info->revision >= 3)
617 return hpt370_tune_chipset(drive, speed);
618 else /* hpt368: hpt_minimum_revision(dev, 2) */
619 return hpt36x_tune_chipset(drive, speed);
622 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
624 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
625 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
629 * This allows the configuration of ide_pci chipset registers
630 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
631 * after the drive is reported by the OS. Initially for designed for
632 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
634 * check_in_drive_lists(drive, bad_ata66_4)
635 * check_in_drive_lists(drive, bad_ata66_3)
636 * check_in_drive_lists(drive, bad_ata33)
639 static int config_chipset_for_dma (ide_drive_t *drive)
641 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
642 ide_hwif_t *hwif = drive->hwif;
643 struct hpt_info *info = ide_get_hwifdata(hwif);
648 /* If we don't have any timings we can't do a lot */
649 if (info->speed == NULL)
652 (void) hpt3xx_tune_chipset(drive, speed);
653 return ide_dma_enable(drive);
656 static int hpt3xx_quirkproc(ide_drive_t *drive)
658 struct hd_driveid *id = drive->id;
659 const char **list = quirk_drives;
662 if (strstr(id->model, *list++))
667 static void hpt3xx_intrproc (ide_drive_t *drive)
669 ide_hwif_t *hwif = drive->hwif;
671 if (drive->quirk_list)
673 /* drives in the quirk_list may not like intr setups/cleanups */
674 hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
677 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
679 ide_hwif_t *hwif = drive->hwif;
680 struct hpt_info *info = ide_get_hwifdata(hwif);
681 struct pci_dev *dev = hwif->pci_dev;
683 if (drive->quirk_list) {
684 if (info->revision >= 3) {
686 pci_read_config_byte(dev, 0x5a, ®5a);
687 if (((reg5a & 0x10) >> 4) != mask)
688 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
691 disable_irq(hwif->irq);
693 enable_irq(hwif->irq);
698 hwif->OUTB(mask ? (drive->ctl | 2) :
704 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
706 ide_hwif_t *hwif = drive->hwif;
707 struct hd_driveid *id = drive->id;
709 drive->init_speed = 0;
711 if ((id->capability & 1) && drive->autodma) {
713 if (ide_use_dma(drive)) {
714 if (config_chipset_for_dma(drive))
715 return hwif->ide_dma_on(drive);
720 } else if ((id->capability & 8) || (id->field_valid & 2)) {
722 hpt3xx_tune_drive(drive, 5);
723 return hwif->ide_dma_off_quietly(drive);
725 /* IORDY not supported */
730 * This is specific to the HPT366 UDMA bios chipset
731 * by HighPoint|Triones Technologies, Inc.
733 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
735 struct pci_dev *dev = HWIF(drive)->pci_dev;
736 u8 reg50h = 0, reg52h = 0, reg5ah = 0;
738 pci_read_config_byte(dev, 0x50, ®50h);
739 pci_read_config_byte(dev, 0x52, ®52h);
740 pci_read_config_byte(dev, 0x5a, ®5ah);
741 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
742 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
744 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
745 return __ide_dma_lostirq(drive);
748 static void hpt370_clear_engine (ide_drive_t *drive)
750 u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
751 pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
755 static void hpt370_ide_dma_start(ide_drive_t *drive)
757 #ifdef HPT_RESET_STATE_ENGINE
758 hpt370_clear_engine(drive);
760 ide_dma_start(drive);
763 static int hpt370_ide_dma_end (ide_drive_t *drive)
765 ide_hwif_t *hwif = HWIF(drive);
766 u8 dma_stat = hwif->INB(hwif->dma_status);
768 if (dma_stat & 0x01) {
771 dma_stat = hwif->INB(hwif->dma_status);
773 if ((dma_stat & 0x01) != 0)
775 (void) HWIF(drive)->ide_dma_timeout(drive);
777 return __ide_dma_end(drive);
780 static void hpt370_lostirq_timeout (ide_drive_t *drive)
782 ide_hwif_t *hwif = HWIF(drive);
783 u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52;
784 u8 dma_stat = 0, dma_cmd = 0;
786 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
787 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
788 hpt370_clear_engine(drive);
789 /* get dma command mode */
790 dma_cmd = hwif->INB(hwif->dma_command);
792 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
793 dma_stat = hwif->INB(hwif->dma_status);
795 hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
798 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
800 hpt370_lostirq_timeout(drive);
801 hpt370_clear_engine(drive);
802 return __ide_dma_timeout(drive);
805 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
807 hpt370_lostirq_timeout(drive);
808 hpt370_clear_engine(drive);
809 return __ide_dma_lostirq(drive);
812 /* returns 1 if DMA IRQ issued, 0 otherwise */
813 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
815 ide_hwif_t *hwif = HWIF(drive);
817 u8 reginfo = hwif->channel ? 0x56 : 0x52;
820 pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
822 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
826 dma_stat = hwif->INB(hwif->dma_status);
827 /* return 1 if INTR asserted */
828 if ((dma_stat & 4) == 4)
831 if (!drive->waiting_for_dma)
832 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
833 drive->name, __FUNCTION__);
837 static int hpt374_ide_dma_end (ide_drive_t *drive)
839 struct pci_dev *dev = HWIF(drive)->pci_dev;
840 ide_hwif_t *hwif = HWIF(drive);
841 u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
842 u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
844 pci_read_config_byte(dev, 0x6a, &bwsr_stat);
845 pci_read_config_byte(dev, mscreg, &msc_stat);
846 if ((bwsr_stat & bwsr_mask) == bwsr_mask)
847 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
848 return __ide_dma_end(drive);
852 * hpt3xxn_set_clock - perform clock switching dance
853 * @hwif: hwif to switch
854 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
856 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
857 * NOTE: avoid touching the disabled primary channel on HPT371N -- it
858 * doesn't physically exist anyway...
861 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
863 u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
865 if ((scr2 & 0x7f) == mode)
868 /* MISC. control register 1 has the channel enable bit... */
869 mcr1 = hwif->INB(hwif->dma_master + 0x70);
871 /* Tristate the bus */
873 hwif->OUTB(0x80, hwif->dma_master + 0x73);
874 hwif->OUTB(0x80, hwif->dma_master + 0x77);
876 /* Switch clock and reset channels */
877 hwif->OUTB(mode, hwif->dma_master + 0x7b);
878 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
880 /* Reset state machines */
882 hwif->OUTB(0x37, hwif->dma_master + 0x70);
883 hwif->OUTB(0x37, hwif->dma_master + 0x74);
886 hwif->OUTB(0x00, hwif->dma_master + 0x79);
888 /* Reconnect channels to bus */
890 hwif->OUTB(0x00, hwif->dma_master + 0x73);
891 hwif->OUTB(0x00, hwif->dma_master + 0x77);
895 * hpt3xxn_rw_disk - prepare for I/O
896 * @drive: drive for command
897 * @rq: block request structure
899 * This is called when a disk I/O is issued to HPT3xxN.
900 * We need it because of the clock switching.
903 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
905 ide_hwif_t *hwif = HWIF(drive);
906 u8 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
908 hpt3xxn_set_clock(hwif, wantclock);
912 * Set/get power state for a drive.
914 * When we turn the power back on, we need to re-initialize things.
916 #define TRISTATE_BIT 0x8000
918 static int hpt3xx_busproc(ide_drive_t *drive, int state)
920 ide_hwif_t *hwif = drive->hwif;
921 struct pci_dev *dev = hwif->pci_dev;
922 u8 tristate, resetmask, bus_reg = 0;
925 hwif->bus_state = state;
928 /* secondary channel */
932 /* primary channel */
937 /* Grab the status. */
938 pci_read_config_word(dev, tristate, &tri_reg);
939 pci_read_config_byte(dev, 0x59, &bus_reg);
942 * Set the state. We don't set it if we don't need to do so.
943 * Make sure that the drive knows that it has failed if it's off.
947 if (!(bus_reg & resetmask))
949 hwif->drives[0].failures = hwif->drives[1].failures = 0;
951 pci_write_config_byte(dev, 0x59, bus_reg & ~resetmask);
952 pci_write_config_word(dev, tristate, tri_reg & ~TRISTATE_BIT);
955 if ((bus_reg & resetmask) && !(tri_reg & TRISTATE_BIT))
957 tri_reg &= ~TRISTATE_BIT;
959 case BUSSTATE_TRISTATE:
960 if ((bus_reg & resetmask) && (tri_reg & TRISTATE_BIT))
962 tri_reg |= TRISTATE_BIT;
968 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
969 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
971 pci_write_config_word(dev, tristate, tri_reg);
972 pci_write_config_byte(dev, 0x59, bus_reg | resetmask);
976 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
979 struct hpt_info *info = ide_get_hwifdata(hwif);
981 pci_read_config_dword(hwif->pci_dev, 0x40, ®1);
983 /* detect bus speed by looking at control reg timing: */
984 switch((reg1 >> 8) & 7) {
986 info->speed = forty_base_hpt36x;
989 info->speed = twenty_five_base_hpt36x;
993 info->speed = thirty_three_base_hpt36x;
998 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1000 struct hpt_info *info = ide_get_hwifdata(hwif);
1001 struct pci_dev *dev = hwif->pci_dev;
1002 char *name = hwif->cds->name;
1006 u8 reg5bh = 0, mcr1 = 0;
1009 * default to pci clock. make sure MA15/16 are set to output
1010 * to prevent drives having problems with 40-pin cables. Needed
1011 * for some drives such as IBM-DTLA which will not enter ready
1012 * state on reset when PDIAG is a input.
1014 * ToDo: should we set 0x21 when using PLL mode ?
1016 pci_write_config_byte(dev, 0x5b, 0x23);
1019 * We'll have to read f_CNT value in order to determine
1020 * the PCI clock frequency according to the following ratio:
1022 * f_CNT = Fpci * 192 / Fdpll
1024 * First try reading the register in which the HighPoint BIOS
1025 * saves f_CNT value before reprogramming the DPLL from its
1026 * default setting (which differs for the various chips).
1027 * NOTE: This register is only accessible via I/O space.
1029 * In case the signature check fails, we'll have to resort to
1030 * reading the f_CNT register itself in hopes that nobody has
1031 * touched the DPLL yet...
1033 temp = inl(pci_resource_start(dev, 4) + 0x90);
1034 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1035 printk(KERN_WARNING "%s: no clock data saved by BIOS\n", name);
1037 /* Calculate the average value of f_CNT */
1038 for (temp = i = 0; i < 128; i++) {
1039 pci_read_config_word(dev, 0x78, &freq);
1040 temp += freq & 0x1ff;
1045 freq = temp & 0x1ff;
1048 * HPT3xxN chips use different PCI clock information.
1049 * Currently we always set up the PLL for them.
1052 if (info->flags & IS_3xxN) {
1055 else if(freq < 0x70)
1057 else if(freq < 0x7F)
1065 else if(freq < 0xb0)
1072 printk(KERN_INFO "%s: FREQ: %d, PLL: %d\n", name, freq, pll);
1074 if (!(info->flags & IS_3xxN)) {
1075 if (pll == F_LOW_PCI_33) {
1076 info->speed = thirty_three_base_hpt37x;
1077 printk(KERN_DEBUG "%s: using 33MHz PCI clock\n", name);
1078 } else if (pll == F_LOW_PCI_40) {
1080 } else if (pll == F_LOW_PCI_50) {
1081 info->speed = fifty_base_hpt37x;
1082 printk(KERN_DEBUG "%s: using 50MHz PCI clock\n", name);
1084 info->speed = sixty_six_base_hpt37x;
1085 printk(KERN_DEBUG "%s: using 66MHz PCI clock\n", name);
1089 if (pll == F_LOW_PCI_66)
1090 info->flags |= PCI_66MHZ;
1093 * only try the pll if we don't have a table for the clock
1094 * speed that we're running at. NOTE: the internal PLL will
1095 * result in slow reads when using a 33MHz PCI clock. we also
1096 * don't like to use the PLL because it will cause glitches
1097 * on PRST/SRST when the HPT state engine gets reset.
1099 * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1100 * 372 device so we can get ATA133 support
1103 goto init_hpt37X_done;
1105 info->flags |= PLL_MODE;
1108 * Adjust the PLL based upon the PCI clock, enable it, and
1109 * wait for stabilization...
1112 freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1113 while (adjust++ < 6) {
1114 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1117 /* wait for clock stabilization */
1118 for (i = 0; i < 0x50000; i++) {
1119 pci_read_config_byte(dev, 0x5b, ®5bh);
1120 if (reg5bh & 0x80) {
1121 /* spin looking for the clock to destabilize */
1122 for (i = 0; i < 0x1000; ++i) {
1123 pci_read_config_byte(dev, 0x5b,
1125 if ((reg5bh & 0x80) == 0)
1128 pci_read_config_dword(dev, 0x5c, &pll);
1129 pci_write_config_dword(dev, 0x5c,
1131 pci_write_config_byte(dev, 0x5b, 0x21);
1133 info->speed = fifty_base_hpt37x;
1134 printk("%s: using 50MHz internal PLL\n", name);
1135 goto init_hpt37X_done;
1140 pll -= (adjust >> 1);
1142 pll += (adjust >> 1);
1147 printk(KERN_ERR "%s: unknown bus timing [%d %d].\n",
1150 * Reset the state engines.
1151 * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1153 pci_read_config_byte(dev, 0x50, &mcr1);
1155 pci_write_config_byte(dev, 0x50, 0x37);
1156 pci_write_config_byte(dev, 0x54, 0x37);
1160 static int __devinit init_hpt37x(struct pci_dev *dev)
1164 pci_read_config_byte(dev, 0x5a, ®5ah);
1165 /* interrupt force enable */
1166 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1170 static int __devinit init_hpt366(struct pci_dev *dev)
1176 * Disable the "fast interrupt" prediction.
1178 pci_read_config_byte(dev, 0x51, &drive_fast);
1179 if (drive_fast & 0x80)
1180 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1181 pci_read_config_dword(dev, 0x40, ®1);
1186 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1191 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1192 * We don't seem to be using it.
1194 if (dev->resource[PCI_ROM_RESOURCE].start)
1195 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1196 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1198 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1199 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1200 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1201 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1203 if (hpt_revision(dev) >= 3)
1204 ret = init_hpt37x(dev);
1206 ret = init_hpt366(dev);
1214 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1216 struct pci_dev *dev = hwif->pci_dev;
1217 struct hpt_info *info = ide_get_hwifdata(hwif);
1218 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1219 int serialize = HPT_SERIALIZE_IO;
1221 hwif->tuneproc = &hpt3xx_tune_drive;
1222 hwif->speedproc = &hpt3xx_tune_chipset;
1223 hwif->quirkproc = &hpt3xx_quirkproc;
1224 hwif->intrproc = &hpt3xx_intrproc;
1225 hwif->maskproc = &hpt3xx_maskproc;
1228 * HPT3xxN chips have some complications:
1230 * - on 33 MHz PCI we must clock switch
1231 * - on 66 MHz PCI we must NOT use the PCI clock
1233 if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1235 * Clock is shared between the channels,
1236 * so we'll have to serialize them... :-(
1239 hwif->rw_disk = &hpt3xxn_rw_disk;
1243 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1244 * address lines to access an external eeprom. To read valid
1245 * cable detect state the pins must be enabled as inputs.
1247 if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1249 * HPT374 PCI function 1
1250 * - set bit 15 of reg 0x52 to enable TCBLID as input
1251 * - set bit 15 of reg 0x56 to enable FCBLID as input
1254 pci_read_config_word(dev, 0x52, &mcr3);
1255 pci_read_config_word(dev, 0x56, &mcr6);
1256 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1257 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1258 /* now read cable id register */
1259 pci_read_config_byte(dev, 0x5a, &ata66);
1260 pci_write_config_word(dev, 0x52, mcr3);
1261 pci_write_config_word(dev, 0x56, mcr6);
1262 } else if (info->revision >= 3) {
1264 * HPT370/372 and 374 pcifn 0
1265 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1268 pci_read_config_byte(dev, 0x5b, &scr2);
1269 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1270 /* now read cable id register */
1271 pci_read_config_byte(dev, 0x5a, &ata66);
1272 pci_write_config_byte(dev, 0x5b, scr2);
1274 pci_read_config_byte(dev, 0x5a, &ata66);
1278 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1279 ata66, (ata66 & regmask) ? "33" : "66",
1280 PCI_FUNC(hwif->pci_dev->devfn));
1283 /* Serialize access to this device */
1284 if (serialize && hwif->mate)
1285 hwif->serialized = hwif->mate->serialized = 1;
1288 * Set up ioctl for power status.
1289 * NOTE: power affects both drives on each channel.
1291 hwif->busproc = &hpt3xx_busproc;
1293 if (!hwif->dma_base) {
1294 hwif->drives[0].autotune = 1;
1295 hwif->drives[1].autotune = 1;
1299 hwif->ultra_mask = 0x7f;
1300 hwif->mwdma_mask = 0x07;
1302 if (!(hwif->udma_four))
1303 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1304 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1306 if (info->revision >= 8) {
1307 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1308 hwif->ide_dma_end = &hpt374_ide_dma_end;
1309 } else if (info->revision >= 5) {
1310 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1311 hwif->ide_dma_end = &hpt374_ide_dma_end;
1312 } else if (info->revision >= 3) {
1313 hwif->dma_start = &hpt370_ide_dma_start;
1314 hwif->ide_dma_end = &hpt370_ide_dma_end;
1315 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1316 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1317 } else if (info->revision >= 2)
1318 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1320 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1324 hwif->drives[0].autodma = hwif->autodma;
1325 hwif->drives[1].autodma = hwif->autodma;
1328 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1330 struct hpt_info *info = ide_get_hwifdata(hwif);
1331 u8 masterdma = 0, slavedma = 0;
1332 u8 dma_new = 0, dma_old = 0;
1333 u8 primary = hwif->channel ? 0x4b : 0x43;
1334 u8 secondary = hwif->channel ? 0x4f : 0x47;
1335 unsigned long flags;
1340 if(info->speed == NULL) {
1341 printk(KERN_WARNING "%s: no known IDE timings, disabling DMA.\n",
1346 dma_old = hwif->INB(dmabase+2);
1348 local_irq_save(flags);
1351 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1352 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1354 if (masterdma & 0x30) dma_new |= 0x20;
1355 if (slavedma & 0x30) dma_new |= 0x40;
1356 if (dma_new != dma_old)
1357 hwif->OUTB(dma_new, dmabase+2);
1359 local_irq_restore(flags);
1361 ide_setup_dma(hwif, dmabase, 8);
1365 * We "borrow" this hook in order to set the data structures
1366 * up early enough before dma or init_hwif calls are made.
1369 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1371 struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1372 struct pci_dev *dev = hwif->pci_dev;
1373 u16 did = dev->device;
1377 printk(KERN_WARNING "%s: out of memory.\n", hwif->cds->name);
1380 ide_set_hwifdata(hwif, info);
1382 /* Avoid doing the same thing twice. */
1383 if (hwif->channel && hwif->mate) {
1384 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1388 pci_read_config_byte(dev, PCI_REVISION_ID, &rid);
1390 if (( did == PCI_DEVICE_ID_TTI_HPT366 && rid == 6) ||
1391 ((did == PCI_DEVICE_ID_TTI_HPT372 ||
1392 did == PCI_DEVICE_ID_TTI_HPT302 ||
1393 did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1394 did == PCI_DEVICE_ID_TTI_HPT372N)
1395 info->flags |= IS_3xxN;
1397 rid = info->revision = hpt_revision(dev);
1398 if (rid >= 8) /* HPT374 */
1399 mode = HPT374_ALLOW_ATA133_6 ? 4 : 3;
1400 else if (rid >= 7) /* HPT371 and HPT371N */
1401 mode = HPT371_ALLOW_ATA133_6 ? 4 : 3;
1402 else if (rid >= 6) /* HPT302 and HPT302N */
1403 mode = HPT302_ALLOW_ATA133_6 ? 4 : 3;
1404 else if (rid >= 5) /* HPT372, HPT372A, and HPT372N */
1405 mode = HPT372_ALLOW_ATA133_6 ? 4 : 3;
1406 else if (rid >= 3) /* HPT370 and HPT370A */
1407 mode = HPT370_ALLOW_ATA100_5 ? 3 : 2;
1408 else /* HPT366 and HPT368 */
1409 mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1;
1410 info->max_mode = mode;
1413 hpt37x_clocking(hwif);
1415 hpt366_clocking(hwif);
1418 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1420 struct pci_dev *dev2;
1422 if (PCI_FUNC(dev->devfn) & 1)
1425 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1428 if (dev2->irq != dev->irq) {
1429 /* FIXME: we need a core pci_set_interrupt() */
1430 dev2->irq = dev->irq;
1431 printk(KERN_WARNING "%s: PCI config space interrupt "
1432 "fixed.\n", d->name);
1434 ret = ide_setup_pci_devices(dev, dev2, d);
1439 return ide_setup_pci_device(dev, d);
1442 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1444 return ide_setup_pci_device(dev, d);
1447 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1449 u8 rev = 0, mcr1 = 0;
1451 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1454 d->name = "HPT371N";
1457 * HPT371 chips physically have only one channel, the secondary one,
1458 * but the primary channel registers do exist! Go figure...
1459 * So, we manually disable the non-existing channel here
1460 * (if the BIOS hasn't done this already).
1462 pci_read_config_byte(dev, 0x50, &mcr1);
1464 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1466 return ide_setup_pci_device(dev, d);
1469 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1473 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1476 d->name = "HPT372N";
1478 return ide_setup_pci_device(dev, d);
1481 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1485 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1488 d->name = "HPT302N";
1490 return ide_setup_pci_device(dev, d);
1493 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1495 struct pci_dev *dev2;
1497 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1498 "HPT370", "HPT370A", "HPT372",
1501 if (PCI_FUNC(dev->devfn) & 1)
1504 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1509 d->name = chipset_names[rev];
1516 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1517 u8 pin1 = 0, pin2 = 0;
1520 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1521 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1522 if (pin1 != pin2 && dev->irq == dev2->irq) {
1523 d->bootable = ON_BOARD;
1524 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1525 d->name, pin1, pin2);
1527 ret = ide_setup_pci_devices(dev, dev2, d);
1533 return ide_setup_pci_device(dev, d);
1536 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1539 .init_setup = init_setup_hpt366,
1540 .init_chipset = init_chipset_hpt366,
1541 .init_iops = init_iops_hpt366,
1542 .init_hwif = init_hwif_hpt366,
1543 .init_dma = init_dma_hpt366,
1546 .bootable = OFF_BOARD,
1550 .init_setup = init_setup_hpt372a,
1551 .init_chipset = init_chipset_hpt366,
1552 .init_iops = init_iops_hpt366,
1553 .init_hwif = init_hwif_hpt366,
1554 .init_dma = init_dma_hpt366,
1557 .bootable = OFF_BOARD,
1561 .init_setup = init_setup_hpt302,
1562 .init_chipset = init_chipset_hpt366,
1563 .init_iops = init_iops_hpt366,
1564 .init_hwif = init_hwif_hpt366,
1565 .init_dma = init_dma_hpt366,
1568 .bootable = OFF_BOARD,
1572 .init_setup = init_setup_hpt371,
1573 .init_chipset = init_chipset_hpt366,
1574 .init_iops = init_iops_hpt366,
1575 .init_hwif = init_hwif_hpt366,
1576 .init_dma = init_dma_hpt366,
1579 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1580 .bootable = OFF_BOARD,
1584 .init_setup = init_setup_hpt374,
1585 .init_chipset = init_chipset_hpt366,
1586 .init_iops = init_iops_hpt366,
1587 .init_hwif = init_hwif_hpt366,
1588 .init_dma = init_dma_hpt366,
1589 .channels = 2, /* 4 */
1591 .bootable = OFF_BOARD,
1595 .init_setup = init_setup_hpt372n,
1596 .init_chipset = init_chipset_hpt366,
1597 .init_iops = init_iops_hpt366,
1598 .init_hwif = init_hwif_hpt366,
1599 .init_dma = init_dma_hpt366,
1600 .channels = 2, /* 4 */
1602 .bootable = OFF_BOARD,
1608 * hpt366_init_one - called when an HPT366 is found
1609 * @dev: the hpt366 device
1610 * @id: the matching pci id
1612 * Called when the PCI registration layer (or the IDE initialization)
1613 * finds a device matching our IDE device tables.
1615 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1616 * structure depending on the chip's revision, we'd better pass a local
1617 * copy down the call chain...
1619 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1621 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1623 return d.init_setup(dev, &d);
1626 static struct pci_device_id hpt366_pci_tbl[] = {
1627 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1628 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1629 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1630 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1631 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1632 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1635 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1637 static struct pci_driver driver = {
1638 .name = "HPT366_IDE",
1639 .id_table = hpt366_pci_tbl,
1640 .probe = hpt366_init_one,
1643 static int __init hpt366_ide_init(void)
1645 return ide_pci_register_driver(&driver);
1648 module_init(hpt366_ide_init);
1650 MODULE_AUTHOR("Andre Hedrick");
1651 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1652 MODULE_LICENSE("GPL");