2 * Promise TX2/TX4/TX2000/133 IDE driver
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2006 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
35 #ifdef CONFIG_PPC_PMAC
37 #include <asm/pci-bridge.h>
43 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
45 #define DBG(fmt, args...)
48 static const char *pdc_quirk_drives[] = {
49 "QUANTUM FIREBALLlct08 08",
50 "QUANTUM FIREBALLP KA6.4",
51 "QUANTUM FIREBALLP KA9.1",
52 "QUANTUM FIREBALLP LM20.4",
53 "QUANTUM FIREBALLP KX13.6",
54 "QUANTUM FIREBALLP KX20.5",
55 "QUANTUM FIREBALLP KX27.3",
56 "QUANTUM FIREBALLP LM20.5",
60 static u8 max_dma_rate(struct pci_dev *pdev)
64 switch(pdev->device) {
65 case PCI_DEVICE_ID_PROMISE_20277:
66 case PCI_DEVICE_ID_PROMISE_20276:
67 case PCI_DEVICE_ID_PROMISE_20275:
68 case PCI_DEVICE_ID_PROMISE_20271:
69 case PCI_DEVICE_ID_PROMISE_20269:
72 case PCI_DEVICE_ID_PROMISE_20270:
73 case PCI_DEVICE_ID_PROMISE_20268:
84 * get_indexed_reg - Get indexed register
85 * @hwif: for the port address
86 * @index: index of the indexed register
88 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
92 outb(index, hwif->dma_vendor1);
93 value = inb(hwif->dma_vendor3);
95 DBG("index[%02X] value[%02X]\n", index, value);
100 * set_indexed_reg - Set indexed register
101 * @hwif: for the port address
102 * @index: index of the indexed register
104 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
106 outb(index, hwif->dma_vendor1);
107 outb(value, hwif->dma_vendor3);
108 DBG("index[%02X] value[%02X]\n", index, value);
112 * ATA Timing Tables based on 133 MHz PLL output clock.
114 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
115 * the timing registers automatically when "set features" command is
116 * issued to the device. However, if the PLL output clock is 133 MHz,
117 * the following tables must be used.
119 static struct pio_timing {
120 u8 reg0c, reg0d, reg13;
122 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
123 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
124 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
125 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
126 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
129 static struct mwdma_timing {
131 } mwdma_timings [] = {
132 { 0xdf, 0x5f }, /* MWDMA mode 0 */
133 { 0x6b, 0x27 }, /* MWDMA mode 1 */
134 { 0x69, 0x25 }, /* MWDMA mode 2 */
137 static struct udma_timing {
138 u8 reg10, reg11, reg12;
139 } udma_timings [] = {
140 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
141 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
142 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
143 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
144 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
145 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
146 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
149 static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
151 ide_hwif_t *hwif = HWIF(drive);
152 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
155 speed = ide_rate_filter(drive, speed);
158 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
159 * automatically set the timing registers based on 100 MHz PLL output.
161 err = ide_config_drive_speed(drive, speed);
164 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
165 * chips, we must override the default register settings...
167 if (max_dma_rate(hwif->pci_dev) == 4) {
168 u8 mode = speed & 0x07;
178 set_indexed_reg(hwif, 0x10 + adj,
179 udma_timings[mode].reg10);
180 set_indexed_reg(hwif, 0x11 + adj,
181 udma_timings[mode].reg11);
182 set_indexed_reg(hwif, 0x12 + adj,
183 udma_timings[mode].reg12);
189 set_indexed_reg(hwif, 0x0e + adj,
190 mwdma_timings[mode].reg0e);
191 set_indexed_reg(hwif, 0x0f + adj,
192 mwdma_timings[mode].reg0f);
199 set_indexed_reg(hwif, 0x0c + adj,
200 pio_timings[mode].reg0c);
201 set_indexed_reg(hwif, 0x0d + adj,
202 pio_timings[mode].reg0d);
203 set_indexed_reg(hwif, 0x13 + adj,
204 pio_timings[mode].reg13);
207 printk(KERN_ERR "pdc202xx_new: "
208 "Unknown speed %d ignored\n", speed);
210 } else if (speed == XFER_UDMA_2) {
211 /* Set tHOLD bit to 0 if using UDMA mode 2 */
212 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
214 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
220 static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
222 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
223 (void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
226 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
228 return get_indexed_reg(hwif, 0x0b) & 0x04;
231 static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
233 drive->init_speed = 0;
235 if (ide_tune_dma(drive))
238 if (ide_use_fast_pio(drive))
239 pdcnew_tune_drive(drive, 255);
244 static int pdcnew_quirkproc(ide_drive_t *drive)
246 const char **list, *model = drive->id->model;
248 for (list = pdc_quirk_drives; *list != NULL; list++)
249 if (strstr(model, *list) != NULL)
254 static void pdcnew_reset(ide_drive_t *drive)
257 * Deleted this because it is redundant from the caller.
259 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
260 HWIF(drive)->channel ? "Secondary" : "Primary");
264 * read_counter - Read the byte count registers
265 * @dma_base: for the port address
267 static long __devinit read_counter(u32 dma_base)
269 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
270 u8 cnt0, cnt1, cnt2, cnt3;
271 long count = 0, last;
277 /* Read the current count */
278 outb(0x20, pri_dma_base + 0x01);
279 cnt0 = inb(pri_dma_base + 0x03);
280 outb(0x21, pri_dma_base + 0x01);
281 cnt1 = inb(pri_dma_base + 0x03);
282 outb(0x20, sec_dma_base + 0x01);
283 cnt2 = inb(sec_dma_base + 0x03);
284 outb(0x21, sec_dma_base + 0x01);
285 cnt3 = inb(sec_dma_base + 0x03);
287 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
290 * The 30-bit decrementing counter is read in 4 pieces.
291 * Incorrect value may be read when the most significant bytes
294 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
296 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
297 cnt0, cnt1, cnt2, cnt3);
303 * detect_pll_input_clock - Detect the PLL input clock in Hz.
304 * @dma_base: for the port address
305 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
307 static long __devinit detect_pll_input_clock(unsigned long dma_base)
309 long start_count, end_count;
313 start_count = read_counter(dma_base);
315 /* Start the test mode */
316 outb(0x01, dma_base + 0x01);
317 scr1 = inb(dma_base + 0x03);
318 DBG("scr1[%02X]\n", scr1);
319 outb(scr1 | 0x40, dma_base + 0x03);
321 /* Let the counter run for 10 ms. */
324 end_count = read_counter(dma_base);
326 /* Stop the test mode */
327 outb(0x01, dma_base + 0x01);
328 scr1 = inb(dma_base + 0x03);
329 DBG("scr1[%02X]\n", scr1);
330 outb(scr1 & ~0x40, dma_base + 0x03);
333 * Calculate the input clock in Hz
334 * (the clock counter is 30 bit wide and counts down)
336 pll_input = ((start_count - end_count) & 0x3ffffff) * 100;
338 DBG("start[%ld] end[%ld]\n", start_count, end_count);
343 #ifdef CONFIG_PPC_PMAC
344 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
346 struct device_node *np = pci_device_to_OF_node(pdev);
347 unsigned int class_rev = 0;
350 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
353 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
356 if (class_rev >= 0x03) {
357 /* Setup chip magic config stuff (from darwin) */
358 pci_read_config_byte (pdev, 0x40, &conf);
359 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
362 #endif /* CONFIG_PPC_PMAC */
364 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
366 unsigned long dma_base = pci_resource_start(dev, 4);
367 unsigned long sec_dma_base = dma_base + 0x08;
368 long pll_input, pll_output, ratio;
370 u8 pll_ctl0, pll_ctl1;
372 if (dev->resource[PCI_ROM_RESOURCE].start) {
373 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
374 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
375 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
376 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
379 #ifdef CONFIG_PPC_PMAC
380 apple_kiwi_init(dev);
383 /* Calculate the required PLL output frequency */
384 switch(max_dma_rate(dev)) {
385 case 4: /* it's 133 MHz for Ultra133 chips */
386 pll_output = 133333333;
388 case 3: /* and 100 MHz for Ultra100 chips */
390 pll_output = 100000000;
395 * Detect PLL input clock.
396 * On some systems, where PCI bus is running at non-standard clock rate
397 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
398 * PDC20268 and newer chips employ PLL circuit to help correct timing
401 pll_input = detect_pll_input_clock(dma_base);
402 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
405 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
406 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
412 DBG("pll_output is %ld Hz\n", pll_output);
414 /* Show the current clock value of PLL control register
415 * (maybe already configured by the BIOS)
417 outb(0x02, sec_dma_base + 0x01);
418 pll_ctl0 = inb(sec_dma_base + 0x03);
419 outb(0x03, sec_dma_base + 0x01);
420 pll_ctl1 = inb(sec_dma_base + 0x03);
422 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
426 * Calculate the ratio of F, R and NO
427 * POUT = (F + 2) / (( R + 2) * NO)
429 ratio = pll_output / (pll_input / 1000);
430 if (ratio < 8600L) { /* 8.6x */
431 /* Using NO = 0x01, R = 0x0d */
433 } else if (ratio < 12900L) { /* 12.9x */
434 /* Using NO = 0x01, R = 0x08 */
436 } else if (ratio < 16100L) { /* 16.1x */
437 /* Using NO = 0x01, R = 0x06 */
439 } else if (ratio < 64000L) { /* 64x */
443 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
447 f = (ratio * (r + 2)) / 1000 - 2;
449 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
451 if (unlikely(f < 0 || f > 127)) {
453 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
460 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
462 outb(0x02, sec_dma_base + 0x01);
463 outb(pll_ctl0, sec_dma_base + 0x03);
464 outb(0x03, sec_dma_base + 0x01);
465 outb(pll_ctl1, sec_dma_base + 0x03);
467 /* Wait the PLL circuit to be stable */
472 * Show the current clock value of PLL control register
474 outb(0x02, sec_dma_base + 0x01);
475 pll_ctl0 = inb(sec_dma_base + 0x03);
476 outb(0x03, sec_dma_base + 0x01);
477 pll_ctl1 = inb(sec_dma_base + 0x03);
479 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
486 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
490 hwif->tuneproc = &pdcnew_tune_drive;
491 hwif->quirkproc = &pdcnew_quirkproc;
492 hwif->speedproc = &pdcnew_tune_chipset;
493 hwif->resetproc = &pdcnew_reset;
495 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
499 hwif->ultra_mask = hwif->cds->udma_mask;
500 hwif->mwdma_mask = 0x07;
502 hwif->err_stops_fifo = 1;
504 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
506 if (!hwif->udma_four)
507 hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1;
511 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
514 static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
516 return ide_setup_pci_device(dev, d);
519 static int __devinit init_setup_pdc20270(struct pci_dev *dev,
522 struct pci_dev *findev = NULL;
525 if ((dev->bus->self &&
526 dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
527 (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
528 if (PCI_SLOT(dev->devfn) & 2)
531 while ((findev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
532 if ((findev->vendor == dev->vendor) &&
533 (findev->device == dev->device) &&
534 (PCI_SLOT(findev->devfn) & 2)) {
535 if (findev->irq != dev->irq) {
536 findev->irq = dev->irq;
538 ret = ide_setup_pci_devices(dev, findev, d);
544 return ide_setup_pci_device(dev, d);
547 static int __devinit init_setup_pdc20276(struct pci_dev *dev,
550 if ((dev->bus->self) &&
551 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
552 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
553 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
554 printk(KERN_INFO "ide: Skipping Promise PDC20276 "
555 "attached to I2O RAID controller.\n");
558 return ide_setup_pci_device(dev, d);
561 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
564 .init_setup = init_setup_pdcnew,
565 .init_chipset = init_chipset_pdcnew,
566 .init_hwif = init_hwif_pdc202new,
569 .bootable = OFF_BOARD,
570 .udma_mask = 0x3f, /* udma0-5 */
573 .init_setup = init_setup_pdcnew,
574 .init_chipset = init_chipset_pdcnew,
575 .init_hwif = init_hwif_pdc202new,
578 .bootable = OFF_BOARD,
579 .udma_mask = 0x7f, /* udma0-6*/
582 .init_setup = init_setup_pdc20270,
583 .init_chipset = init_chipset_pdcnew,
584 .init_hwif = init_hwif_pdc202new,
587 .bootable = OFF_BOARD,
588 .udma_mask = 0x3f, /* udma0-5 */
591 .init_setup = init_setup_pdcnew,
592 .init_chipset = init_chipset_pdcnew,
593 .init_hwif = init_hwif_pdc202new,
596 .bootable = OFF_BOARD,
597 .udma_mask = 0x7f, /* udma0-6*/
600 .init_setup = init_setup_pdcnew,
601 .init_chipset = init_chipset_pdcnew,
602 .init_hwif = init_hwif_pdc202new,
605 .bootable = OFF_BOARD,
606 .udma_mask = 0x7f, /* udma0-6*/
609 .init_setup = init_setup_pdc20276,
610 .init_chipset = init_chipset_pdcnew,
611 .init_hwif = init_hwif_pdc202new,
614 .bootable = OFF_BOARD,
615 .udma_mask = 0x7f, /* udma0-6*/
618 .init_setup = init_setup_pdcnew,
619 .init_chipset = init_chipset_pdcnew,
620 .init_hwif = init_hwif_pdc202new,
623 .bootable = OFF_BOARD,
624 .udma_mask = 0x7f, /* udma0-6*/
629 * pdc202new_init_one - called when a pdc202xx is found
630 * @dev: the pdc202new device
631 * @id: the matching pci id
633 * Called when the PCI registration layer (or the IDE initialization)
634 * finds a device matching our IDE device tables.
637 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
639 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
641 return d->init_setup(dev, d);
644 static struct pci_device_id pdc202new_pci_tbl[] = {
645 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
646 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
647 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
648 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
649 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
650 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
651 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
654 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
656 static struct pci_driver driver = {
657 .name = "Promise_IDE",
658 .id_table = pdc202new_pci_tbl,
659 .probe = pdc202new_init_one,
662 static int __init pdc202new_ide_init(void)
664 return ide_pci_register_driver(&driver);
667 module_init(pdc202new_ide_init);
669 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
670 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
671 MODULE_LICENSE("GPL");