2 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
3 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
4 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
7 * May be copied or modified under the terms of the GNU General Public License
11 * Publically available from Intel web site. Errata documentation
12 * is also publically available. As an aide to anyone hacking on this
13 * driver the list of errata that are relevant is below.going back to
14 * PIIX4. Older device documentation is now a bit tricky to find.
19 * PIIX4 errata #9 - Only on ultra obscure hw
20 * ICH3 errata #13 - Not observed to affect real hw
23 * Things we must deal with
24 * PIIX4 errata #10 - BM IDE hang with non UDMA
25 * (must stop/start dma to recover)
26 * 440MX errata #15 - As PIIX4 errata #10
27 * PIIX4 errata #15 - Must not read control registers
28 * during a PIO transfer
29 * 440MX errata #13 - As PIIX4 errata #15
30 * ICH2 errata #21 - DMA mode 0 doesn't work right
31 * ICH0/1 errata #55 - As ICH2 errata #21
32 * ICH2 spec c #9 - Extra operations needed to handle
33 * drive hotswap [NOT YET SUPPORTED]
34 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
35 * and must be dword aligned
36 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
38 * Should have been BIOS fixed:
39 * 450NX: errata #19 - DMA hangs on old 450NX
40 * 450NX: errata #20 - DMA hangs on old 450NX
41 * 450NX: errata #25 - Corruption with DMA on old 450NX
42 * ICH3 errata #15 - IDE deadlock under high load
43 * (BIOS must set dev 31 fn 0 bit 23)
44 * ICH3 errata #18 - Don't use native mode
47 #include <linux/types.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/pci.h>
51 #include <linux/hdreg.h>
52 #include <linux/ide.h>
53 #include <linux/init.h>
57 #define DRV_NAME "piix"
59 static int no_piix_dma;
62 * piix_set_pio_mode - set host controller for PIO mode
64 * @pio: PIO mode number
66 * Set the interface PIO mode based upon the settings done by AMI BIOS.
69 static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
71 ide_hwif_t *hwif = HWIF(drive);
72 struct pci_dev *dev = to_pci_dev(hwif->dev);
73 int is_slave = drive->dn & 1;
74 int master_port = hwif->channel ? 0x42 : 0x40;
75 int slave_port = 0x44;
79 static DEFINE_SPINLOCK(tune_lock);
83 static const u8 timings[][2]= {
91 * Master vs slave is synchronized above us but the slave register is
92 * shared by the two hwifs so the corner case of two slave timeouts in
93 * parallel must be locked.
95 spin_lock_irqsave(&tune_lock, flags);
96 pci_read_config_word(dev, master_port, &master_data);
99 control |= 1; /* Programmable timing on */
100 if (drive->media == ide_disk)
101 control |= 4; /* Prefetch, post write */
103 control |= 2; /* IORDY */
105 master_data |= 0x4000;
106 master_data &= ~0x0070;
108 /* Set PPE, IE and TIME */
109 master_data |= control << 4;
111 pci_read_config_byte(dev, slave_port, &slave_data);
112 slave_data &= hwif->channel ? 0x0f : 0xf0;
113 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
114 (hwif->channel ? 4 : 0);
116 master_data &= ~0x3307;
118 /* enable PPE, IE and TIME */
119 master_data |= control;
121 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
123 pci_write_config_word(dev, master_port, master_data);
125 pci_write_config_byte(dev, slave_port, slave_data);
126 spin_unlock_irqrestore(&tune_lock, flags);
130 * piix_set_dma_mode - set host controller for DMA mode
134 * Set a PIIX host controller to the desired DMA mode. This involves
135 * programming the right timing data into the PCI configuration space.
138 static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
140 ide_hwif_t *hwif = HWIF(drive);
141 struct pci_dev *dev = to_pci_dev(hwif->dev);
142 u8 maslave = hwif->channel ? 0x42 : 0x40;
143 int a_speed = 3 << (drive->dn * 4);
144 int u_flag = 1 << drive->dn;
145 int v_flag = 0x01 << drive->dn;
146 int w_flag = 0x10 << drive->dn;
150 u8 reg48, reg54, reg55;
152 pci_read_config_word(dev, maslave, ®4042);
153 sitre = (reg4042 & 0x4000) ? 1 : 0;
154 pci_read_config_byte(dev, 0x48, ®48);
155 pci_read_config_word(dev, 0x4a, ®4a);
156 pci_read_config_byte(dev, 0x54, ®54);
157 pci_read_config_byte(dev, 0x55, ®55);
159 if (speed >= XFER_UDMA_0) {
160 u8 udma = speed - XFER_UDMA_0;
162 u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
164 if (!(reg48 & u_flag))
165 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
166 if (speed == XFER_UDMA_5) {
167 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
169 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
171 if ((reg4a & a_speed) != u_speed)
172 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
173 if (speed > XFER_UDMA_2) {
174 if (!(reg54 & v_flag))
175 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
177 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
179 const u8 mwdma_to_pio[] = { 0, 3, 4 };
183 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
185 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
187 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
189 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
191 if (speed >= XFER_MW_DMA_0)
192 pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
194 pio = 2; /* only SWDMA2 is allowed */
196 piix_set_pio_mode(drive, pio);
201 * init_chipset_ich - set up the ICH chipset
202 * @dev: PCI device to set up
203 * @name: Name of the device
205 * Initialize the PCI device as required. For the ICH this turns
206 * out to be nice and simple.
209 static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name)
213 pci_read_config_dword(dev, 0x54, &extra);
214 pci_write_config_dword(dev, 0x54, extra | 0x400);
220 * piix_dma_clear_irq - clear BMDMA status
221 * @drive: IDE drive to clear
223 * Called from ide_intr() for PIO interrupts
224 * to clear BMDMA status as needed by ICHx
226 static void piix_dma_clear_irq(ide_drive_t *drive)
228 ide_hwif_t *hwif = HWIF(drive);
231 /* clear the INTR & ERROR bits */
232 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
233 /* Should we force the bit as well ? */
234 outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
244 * List of laptops that use short cables rather than 80 wire
247 static const struct ich_laptop ich_laptop[] = {
248 /* devid, subvendor, subdev */
249 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
250 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
251 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
252 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
253 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
254 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
255 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
260 static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
262 struct pci_dev *pdev = to_pci_dev(hwif->dev);
263 const struct ich_laptop *lap = &ich_laptop[0];
264 u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
266 /* check for specials */
267 while (lap->device) {
268 if (lap->device == pdev->device &&
269 lap->subvendor == pdev->subsystem_vendor &&
270 lap->subdevice == pdev->subsystem_device) {
271 return ATA_CBL_PATA40_SHORT;
276 pci_read_config_byte(pdev, 0x54, ®54h);
278 return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
282 * init_hwif_piix - fill in the hwif for the PIIX
283 * @hwif: IDE interface
285 * Set up the ide_hwif_t for the PIIX interface according to the
286 * capabilities of the hardware.
289 static void __devinit init_hwif_piix(ide_hwif_t *hwif)
295 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
298 static void __devinit init_hwif_ich(ide_hwif_t *hwif)
300 init_hwif_piix(hwif);
302 /* ICHx need to clear the BMDMA status for all interrupts */
304 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
307 static const struct ide_port_ops piix_port_ops = {
308 .set_pio_mode = piix_set_pio_mode,
309 .set_dma_mode = piix_set_dma_mode,
310 .cable_detect = piix_cable_detect,
314 #define IDE_HFLAGS_PIIX IDE_HFLAG_LEGACY_IRQS
316 #define IDE_HFLAGS_PIIX 0
319 #define DECLARE_PIIX_DEV(udma) \
322 .init_hwif = init_hwif_piix, \
323 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
324 .port_ops = &piix_port_ops, \
325 .host_flags = IDE_HFLAGS_PIIX, \
326 .pio_mask = ATA_PIO4, \
327 .swdma_mask = ATA_SWDMA2_ONLY, \
328 .mwdma_mask = ATA_MWDMA12_ONLY, \
332 #define DECLARE_ICH_DEV(udma) \
335 .init_chipset = init_chipset_ich, \
336 .init_hwif = init_hwif_ich, \
337 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
338 .port_ops = &piix_port_ops, \
339 .host_flags = IDE_HFLAGS_PIIX, \
340 .pio_mask = ATA_PIO4, \
341 .swdma_mask = ATA_SWDMA2_ONLY, \
342 .mwdma_mask = ATA_MWDMA12_ONLY, \
346 static const struct ide_port_info piix_pci_info[] __devinitdata = {
349 * MPIIX actually has only a single IDE channel mapped to
350 * the primary or secondary ports depending on the value
351 * of the bit 14 of the IDETIM register at offset 0x6c
354 .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
355 .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
357 .pio_mask = ATA_PIO4,
358 /* This is a painful system best to let it self tune for now */
360 /* 1: PIIXa/PIIXb/PIIX3 */
361 DECLARE_PIIX_DEV(0x00), /* no udma */
363 DECLARE_PIIX_DEV(ATA_UDMA2),
365 DECLARE_ICH_DEV(ATA_UDMA2),
367 DECLARE_ICH_DEV(ATA_UDMA4),
369 DECLARE_PIIX_DEV(ATA_UDMA4),
370 /* 6: ICH[2-7]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */
371 DECLARE_ICH_DEV(ATA_UDMA5),
375 * piix_init_one - called when a PIIX is found
376 * @dev: the piix device
377 * @id: the matching pci id
379 * Called when the PCI registration layer (or the IDE initialization)
380 * finds a device matching our IDE device tables.
383 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
385 return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
389 * piix_check_450nx - Check for problem 450NX setup
391 * Check for the present of 450NX errata #19 and errata #25. If
392 * they are found, disable use of DMA IDE
395 static void __devinit piix_check_450nx(void)
397 struct pci_dev *pdev = NULL;
399 while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
401 /* Look for 450NX PXB. Check for problem configurations
402 A PCI quirk checks bit 6 already */
403 pci_read_config_word(pdev, 0x41, &cfg);
404 /* Only on the original revision: IDE DMA can hang */
405 if (pdev->revision == 0x00)
407 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
408 else if (cfg & (1<<14) && pdev->revision < 5)
412 printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n");
414 printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n");
417 static const struct pci_device_id piix_pci_tbl[] = {
418 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 1 },
419 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
420 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 0 },
421 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 1 },
422 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 2 },
423 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 3 },
424 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 2 },
425 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 4 },
426 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 5 },
427 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 2 },
428 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 6 },
429 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 6 },
430 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 },
431 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 },
432 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 },
433 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 },
434 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 6 },
435 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 },
436 #ifdef CONFIG_BLK_DEV_IDE_SATA
437 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 6 },
439 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 6 },
440 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 6 },
441 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 6 },
442 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 6 },
443 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 6 },
444 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 6 },
447 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
449 static struct pci_driver driver = {
451 .id_table = piix_pci_tbl,
452 .probe = piix_init_one,
453 .remove = ide_pci_remove,
456 static int __init piix_ide_init(void)
459 return ide_pci_register_driver(&driver);
462 static void __exit piix_ide_exit(void)
464 pci_unregister_driver(&driver);
467 module_init(piix_ide_init);
468 module_exit(piix_ide_exit);
470 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
471 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
472 MODULE_LICENSE("GPL");