2 * linux/drivers/ide/pci/serverworks.c Version 0.9 Mar 4 2007
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * Portions copyright (c) 2001 Sun Microsystems
11 * RCC/ServerWorks IDE driver for Linux
13 * OSB4: `Open South Bridge' IDE Interface (fn 1)
14 * supports UDMA mode 2 (33 MB/s)
16 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
17 * all revisions support UDMA mode 4 (66 MB/s)
18 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
20 * *** The CSB5 does not provide ANY register ***
21 * *** to detect 80-conductor cable presence. ***
23 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
25 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
26 * controller same as the CSB6. Single channel ATA100 only.
29 * Available under NDA only. Errata info very hard to get.
33 #include <linux/types.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/ioport.h>
37 #include <linux/pci.h>
38 #include <linux/hdreg.h>
39 #include <linux/ide.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
46 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
49 * can overrun their FIFOs when used with the CSB5 */
50 static const char *svwks_bad_ata100[] = {
58 static u8 svwks_revision = 0;
59 static struct pci_dev *isa_dev;
61 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
64 if (!strcmp(*list++, drive->id->model))
69 static u8 svwks_udma_filter(ide_drive_t *drive)
71 struct pci_dev *dev = HWIF(drive)->pci_dev;
75 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
77 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
79 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
82 pci_read_config_dword(isa_dev, 0x64, ®);
85 * Don't enable UDMA on disk devices for the moment
87 if(drive->media == ide_disk)
89 /* Check the OSB4 DMA33 enable bit */
90 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
91 } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
93 } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
95 pci_read_config_byte(dev, 0x5A, &btr);
98 /* If someone decides to do UDMA133 on CSB5 the same
99 issue will bite so be inclusive */
100 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
104 case 2: mask = 0x1f; break;
105 case 1: mask = 0x07; break;
106 default: mask = 0x00; break;
109 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
110 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
111 (!(PCI_FUNC(dev->devfn) & 1)))
117 static u8 svwks_csb_check (struct pci_dev *dev)
119 switch (dev->device) {
120 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
121 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
122 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
123 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
130 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
132 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
133 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
134 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
135 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
136 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
138 ide_hwif_t *hwif = HWIF(drive);
139 struct pci_dev *dev = hwif->pci_dev;
140 u8 speed = ide_rate_filter(drive, xferspeed);
141 u8 pio = ide_get_best_pio_mode(drive, 255, 4, NULL);
142 u8 unit = (drive->select.b.unit & 0x01);
143 u8 csb5 = svwks_csb_check(dev);
144 u8 ultra_enable = 0, ultra_timing = 0;
145 u8 dma_timing = 0, pio_timing = 0;
148 /* If we are about to put a disk into UDMA mode we screwed up.
149 Our code assumes we never _ever_ do this on an OSB4 */
151 if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
152 drive->media == ide_disk && speed >= XFER_UDMA_0)
155 pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
156 pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
157 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
158 pci_read_config_word(dev, 0x4A, &csb5_pio);
159 pci_read_config_byte(dev, 0x54, &ultra_enable);
161 /* Per Specified Design by OEM, and ASIC Architect */
162 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
163 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
164 if (!drive->init_speed) {
165 u8 dma_stat = inb(hwif->dma_status);
168 if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
169 ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
170 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
172 } else if ((dma_timing) &&
173 ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
174 u8 dmaspeed = dma_timing;
177 if ((dmaspeed & 0x20) == 0x20)
178 dmaspeed = XFER_MW_DMA_2;
179 else if ((dmaspeed & 0x21) == 0x21)
180 dmaspeed = XFER_MW_DMA_1;
181 else if ((dmaspeed & 0x77) == 0x77)
182 dmaspeed = XFER_MW_DMA_0;
185 drive->current_speed = drive->init_speed = dmaspeed;
187 } else if (pio_timing) {
188 u8 piospeed = pio_timing;
191 if ((piospeed & 0x20) == 0x20)
192 piospeed = XFER_PIO_4;
193 else if ((piospeed & 0x22) == 0x22)
194 piospeed = XFER_PIO_3;
195 else if ((piospeed & 0x34) == 0x34)
196 piospeed = XFER_PIO_2;
197 else if ((piospeed & 0x47) == 0x47)
198 piospeed = XFER_PIO_1;
199 else if ((piospeed & 0x5d) == 0x5d)
200 piospeed = XFER_PIO_0;
202 goto oem_setup_failed;
203 drive->current_speed = drive->init_speed = piospeed;
213 ultra_timing &= ~(0x0F << (4*unit));
214 ultra_enable &= ~(0x01 << drive->dn);
215 csb5_pio &= ~(0x0F << (4*drive->dn));
223 pio_timing |= pio_modes[speed - XFER_PIO_0];
224 csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn));
231 * TODO: always setup PIO mode so this won't be needed
233 pio_timing |= pio_modes[pio];
234 csb5_pio |= (pio << (4*drive->dn));
235 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
245 * TODO: always setup PIO mode so this won't be needed
247 pio_timing |= pio_modes[pio];
248 csb5_pio |= (pio << (4*drive->dn));
249 dma_timing |= dma_modes[2];
250 ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
251 ultra_enable |= (0x01 << drive->dn);
256 pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
258 pci_write_config_word(dev, 0x4A, csb5_pio);
260 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
261 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
262 pci_write_config_byte(dev, 0x54, ultra_enable);
264 return (ide_config_drive_speed(drive, speed));
267 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
269 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
270 (void)svwks_tune_chipset(drive, XFER_PIO_0 + pio);
273 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
275 drive->init_speed = 0;
277 if (ide_tune_dma(drive))
280 if (ide_use_fast_pio(drive))
281 svwks_tune_drive(drive, 255);
286 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
291 /* save revision id to determine DMA capability */
292 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
294 /* force Master Latency Timer value to 64 PCICLKs */
295 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
297 /* OSB4 : South Bridge and IDE */
298 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
299 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
300 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
302 pci_read_config_dword(isa_dev, 0x64, ®);
303 reg &= ~0x00002000; /* disable 600ns interrupt mask */
304 if(!(reg & 0x00004000))
305 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
306 reg |= 0x00004000; /* enable UDMA/33 support */
307 pci_write_config_dword(isa_dev, 0x64, reg);
311 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
312 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
313 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
314 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
316 /* Third Channel Test */
317 if (!(PCI_FUNC(dev->devfn) & 1)) {
318 struct pci_dev * findev = NULL;
320 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
321 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
323 pci_read_config_dword(findev, 0x4C, ®4c);
324 reg4c &= ~0x000007FF;
327 pci_write_config_dword(findev, 0x4C, reg4c);
330 outb_p(0x06, 0x0c00);
331 dev->irq = inb_p(0x0c01);
333 struct pci_dev * findev = NULL;
336 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
337 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
339 pci_read_config_byte(findev, 0x41, ®41);
341 pci_write_config_byte(findev, 0x41, reg41);
345 * This is a device pin issue on CSB6.
346 * Since there will be a future raid mode,
347 * early versions of the chipset require the
348 * interrupt pin to be set, and it is a compatibility
351 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
354 // pci_read_config_dword(dev, 0x40, &pioreg)
355 // pci_write_config_dword(dev, 0x40, 0x99999999);
356 // pci_read_config_dword(dev, 0x44, &dmareg);
357 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
358 /* setup the UDMA Control register
360 * 1. clear bit 6 to enable DMA
361 * 2. enable DMA modes with bits 0-1
365 * 11 : udma2/udma4/udma5
367 pci_read_config_byte(dev, 0x5A, &btr);
369 if (!(PCI_FUNC(dev->devfn) & 1))
372 btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
373 pci_write_config_byte(dev, 0x5A, btr);
375 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
376 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
377 pci_read_config_byte(dev, 0x5A, &btr);
380 pci_write_config_byte(dev, 0x5A, btr);
386 static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
391 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
392 * of the subsystem device ID indicate presence of an 80-pin cable.
393 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
394 * Bit 15 set = secondary IDE channel has 80-pin cable.
395 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
396 * Bit 14 set = primary IDE channel has 80-pin cable.
398 static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
400 struct pci_dev *dev = hwif->pci_dev;
401 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
402 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
403 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
404 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
405 return ((1 << (hwif->channel + 14)) &
406 dev->subsystem_device) ? 1 : 0;
410 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
411 * detect issue by attaching the drives directly to the board.
412 * This check follows the Dell precedent (how scary is that?!)
414 * WARNING: this only works on Alpine hardware!
416 static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
418 struct pci_dev *dev = hwif->pci_dev;
419 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
420 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
421 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
422 return ((1 << (hwif->channel + 14)) &
423 dev->subsystem_device) ? 1 : 0;
427 static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
429 struct pci_dev *dev = hwif->pci_dev;
432 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
433 return ata66_svwks_svwks (hwif);
436 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
437 return ata66_svwks_dell (hwif);
440 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
441 return ata66_svwks_cobalt (hwif);
443 /* Per Specified Design by OEM, and ASIC Architect */
444 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
445 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
451 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
456 hwif->irq = hwif->channel ? 15 : 14;
458 hwif->tuneproc = &svwks_tune_drive;
459 hwif->speedproc = &svwks_tune_chipset;
460 hwif->udma_filter = &svwks_udma_filter;
464 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
465 hwif->ultra_mask = 0x3f;
467 hwif->mwdma_mask = 0x07;
471 if (!hwif->dma_base) {
472 hwif->drives[0].autotune = 1;
473 hwif->drives[1].autotune = 1;
477 hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
478 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
479 if (!hwif->udma_four)
480 hwif->udma_four = ata66_svwks(hwif);
485 dma_stat = inb(hwif->dma_status);
486 hwif->drives[0].autodma = (dma_stat & 0x20);
487 hwif->drives[1].autodma = (dma_stat & 0x40);
488 hwif->drives[0].autotune = (!(dma_stat & 0x20));
489 hwif->drives[1].autotune = (!(dma_stat & 0x40));
492 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
494 return ide_setup_pci_device(dev, d);
497 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
499 if (!(PCI_FUNC(dev->devfn) & 1)) {
500 d->bootable = NEVER_BOARD;
501 if (dev->resource[0].start == 0x01f1)
502 d->bootable = ON_BOARD;
505 d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
506 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
507 (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
509 return ide_setup_pci_device(dev, d);
512 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
514 .name = "SvrWks OSB4",
515 .init_setup = init_setup_svwks,
516 .init_chipset = init_chipset_svwks,
517 .init_hwif = init_hwif_svwks,
520 .bootable = ON_BOARD,
522 .name = "SvrWks CSB5",
523 .init_setup = init_setup_svwks,
524 .init_chipset = init_chipset_svwks,
525 .init_hwif = init_hwif_svwks,
528 .bootable = ON_BOARD,
530 .name = "SvrWks CSB6",
531 .init_setup = init_setup_csb6,
532 .init_chipset = init_chipset_svwks,
533 .init_hwif = init_hwif_svwks,
536 .bootable = ON_BOARD,
538 .name = "SvrWks CSB6",
539 .init_setup = init_setup_csb6,
540 .init_chipset = init_chipset_svwks,
541 .init_hwif = init_hwif_svwks,
542 .channels = 1, /* 2 */
544 .bootable = ON_BOARD,
546 .name = "SvrWks HT1000",
547 .init_setup = init_setup_svwks,
548 .init_chipset = init_chipset_svwks,
549 .init_hwif = init_hwif_svwks,
550 .channels = 1, /* 2 */
552 .bootable = ON_BOARD,
557 * svwks_init_one - called when a OSB/CSB is found
558 * @dev: the svwks device
559 * @id: the matching pci id
561 * Called when the PCI registration layer (or the IDE initialization)
562 * finds a device matching our IDE device tables.
565 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
567 ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
569 return d->init_setup(dev, d);
572 static struct pci_device_id svwks_pci_tbl[] = {
573 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
574 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
575 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
576 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
577 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
580 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
582 static struct pci_driver driver = {
583 .name = "Serverworks_IDE",
584 .id_table = svwks_pci_tbl,
585 .probe = svwks_init_one,
588 static int __init svwks_ide_init(void)
590 return ide_pci_register_driver(&driver);
593 module_init(svwks_ide_init);
595 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
596 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
597 MODULE_LICENSE("GPL");