2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat <alan@redhat.com>
4 * Copyright (C) 2007-2008 MontaVista Software, Inc.
5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15 * Errata and other documentation only available under NDA.
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5, not UDMA6.
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang.
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
29 * The Dell DRAC4 has some interesting features including effectively hot
30 * unplugging/replugging the virtual CD interface when the DRAC is reset.
31 * This often causes drivers/ide/siimage to panic but is ok with the rather
32 * smarter code in libata.
39 #include <linux/types.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/ide.h>
43 #include <linux/init.h>
46 #define DRV_NAME "siimage"
49 * pdev_is_sata - check if device is SATA
50 * @pdev: PCI device to check
52 * Returns true if this is a SATA controller
55 static int pdev_is_sata(struct pci_dev *pdev)
57 #ifdef CONFIG_BLK_DEV_IDE_SATA
58 switch (pdev->device) {
59 case PCI_DEVICE_ID_SII_3112:
60 case PCI_DEVICE_ID_SII_1210SA:
62 case PCI_DEVICE_ID_SII_680:
71 * is_sata - check if hwif is SATA
72 * @hwif: interface to check
74 * Returns true if this is a SATA controller
77 static inline int is_sata(ide_hwif_t *hwif)
79 return pdev_is_sata(to_pci_dev(hwif->dev));
83 * siimage_selreg - return register base
87 * Turn a config register offset into the right address in either
88 * PCI space or MMIO space to access the control register in question
89 * Thankfully this is a configuration operation, so isn't performance
93 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
95 unsigned long base = (unsigned long)hwif->hwif_data;
98 if (hwif->host_flags & IDE_HFLAG_MMIO)
99 base += hwif->channel << 6;
101 base += hwif->channel << 4;
106 * siimage_seldev - return register base
110 * Turn a config register offset into the right address in either
111 * PCI space or MMIO space to access the control register in question
112 * including accounting for the unit shift.
115 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
117 ide_hwif_t *hwif = HWIF(drive);
118 unsigned long base = (unsigned long)hwif->hwif_data;
121 if (hwif->host_flags & IDE_HFLAG_MMIO)
122 base += hwif->channel << 6;
124 base += hwif->channel << 4;
125 base |= drive->select.b.unit << drive->select.b.unit;
129 static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
131 struct ide_host *host = pci_get_drvdata(dev);
135 tmp = readb((void __iomem *)addr);
137 pci_read_config_byte(dev, addr, &tmp);
142 static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
144 struct ide_host *host = pci_get_drvdata(dev);
148 tmp = readw((void __iomem *)addr);
150 pci_read_config_word(dev, addr, &tmp);
155 static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
157 struct ide_host *host = pci_get_drvdata(dev);
160 writeb(val, (void __iomem *)addr);
162 pci_write_config_byte(dev, addr, val);
165 static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
167 struct ide_host *host = pci_get_drvdata(dev);
170 writew(val, (void __iomem *)addr);
172 pci_write_config_word(dev, addr, val);
175 static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
177 struct ide_host *host = pci_get_drvdata(dev);
180 writel(val, (void __iomem *)addr);
182 pci_write_config_dword(dev, addr, val);
186 * sil_udma_filter - compute UDMA mask
189 * Compute the available UDMA speeds for the device on the interface.
191 * For the CMD680 this depends on the clocking mode (scsc), for the
192 * SI3112 SATA controller life is a bit simpler.
195 static u8 sil_pata_udma_filter(ide_drive_t *drive)
197 ide_hwif_t *hwif = drive->hwif;
198 struct pci_dev *dev = to_pci_dev(hwif->dev);
199 unsigned long base = (unsigned long)hwif->hwif_data;
202 base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;
204 scsc = sil_ioread8(dev, base);
206 switch (scsc & 0x30) {
210 case 0x20: /* 2xPCI */
216 default: /* Disabled ? */
223 static u8 sil_sata_udma_filter(ide_drive_t *drive)
225 char *m = (char *)&drive->id[ATA_ID_PROD];
227 return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
231 * sil_set_pio_mode - set host controller for PIO mode
233 * @pio: PIO mode number
235 * Load the timing settings for this device mode into the
236 * controller. If we are in PIO mode 3 or 4 turn on IORDY
237 * monitoring (bit 9). The TF timing is bits 31:16
240 static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
242 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
243 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
245 ide_hwif_t *hwif = HWIF(drive);
246 struct pci_dev *dev = to_pci_dev(hwif->dev);
247 ide_drive_t *pair = ide_get_pair_dev(drive);
250 unsigned long addr = siimage_seldev(drive, 0x04);
251 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
252 unsigned long base = (unsigned long)hwif->hwif_data;
254 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
255 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
256 : (mmio ? 0xB4 : 0x80);
258 u8 unit = drive->select.b.unit;
260 /* trim *taskfile* PIO to the slowest of the master/slave */
262 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
264 if (pair_pio < tf_pio)
268 /* cheat for now and use the docs */
269 speedp = data_speed[pio];
270 speedt = tf_speed[tf_pio];
272 sil_iowrite16(dev, speedp, addr);
273 sil_iowrite16(dev, speedt, tfaddr);
275 /* now set up IORDY */
276 speedp = sil_ioread16(dev, tfaddr - 2);
280 sil_iowrite16(dev, speedp, tfaddr - 2);
282 mode = sil_ioread8(dev, base + addr_mask);
283 mode &= ~(unit ? 0x30 : 0x03);
284 mode |= unit ? 0x10 : 0x01;
285 sil_iowrite8(dev, mode, base + addr_mask);
289 * sil_set_dma_mode - set host controller for DMA mode
293 * Tune the SiI chipset for the desired DMA mode.
296 static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
298 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
299 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
300 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
302 ide_hwif_t *hwif = HWIF(drive);
303 struct pci_dev *dev = to_pci_dev(hwif->dev);
304 u16 ultra = 0, multi = 0;
305 u8 mode = 0, unit = drive->select.b.unit;
306 unsigned long base = (unsigned long)hwif->hwif_data;
307 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
308 u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
309 : (mmio ? 0xB4 : 0x80);
310 unsigned long ma = siimage_seldev(drive, 0x08);
311 unsigned long ua = siimage_seldev(drive, 0x0C);
313 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
314 mode = sil_ioread8 (dev, base + addr_mask);
315 multi = sil_ioread16(dev, ma);
316 ultra = sil_ioread16(dev, ua);
318 mode &= ~(unit ? 0x30 : 0x03);
320 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
322 scsc = is_sata(hwif) ? 1 : scsc;
324 if (speed >= XFER_UDMA_0) {
326 ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
327 ultra5[speed - XFER_UDMA_0];
328 mode |= unit ? 0x30 : 0x03;
330 multi = dma[speed - XFER_MW_DMA_0];
331 mode |= unit ? 0x20 : 0x02;
334 sil_iowrite8 (dev, mode, base + addr_mask);
335 sil_iowrite16(dev, multi, ma);
336 sil_iowrite16(dev, ultra, ua);
339 /* returns 1 if dma irq issued, 0 otherwise */
340 static int siimage_io_dma_test_irq(ide_drive_t *drive)
342 ide_hwif_t *hwif = HWIF(drive);
343 struct pci_dev *dev = to_pci_dev(hwif->dev);
345 unsigned long addr = siimage_selreg(hwif, 1);
347 /* return 1 if INTR asserted */
348 if (inb(hwif->dma_base + ATA_DMA_STATUS) & 4)
351 /* return 1 if Device INTR asserted */
352 pci_read_config_byte(dev, addr, &dma_altstat);
354 return 0; /* return 1; */
360 * siimage_mmio_dma_test_irq - check we caused an IRQ
361 * @drive: drive we are testing
363 * Check if we caused an IDE DMA interrupt. We may also have caused
364 * SATA status interrupts, if so we clean them up and continue.
367 static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
369 ide_hwif_t *hwif = HWIF(drive);
370 unsigned long addr = siimage_selreg(hwif, 0x1);
371 void __iomem *sata_error_addr
372 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
374 if (sata_error_addr) {
375 unsigned long base = (unsigned long)hwif->hwif_data;
376 u32 ext_stat = readl((void __iomem *)(base + 0x10));
379 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
380 u32 sata_error = readl(sata_error_addr);
382 writel(sata_error, sata_error_addr);
383 watchdog = (sata_error & 0x00680000) ? 1 : 0;
384 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
385 "watchdog = %d, %s\n",
386 drive->name, sata_error, watchdog, __func__);
388 watchdog = (ext_stat & 0x8000) ? 1 : 0;
391 if (!(ext_stat & 0x0404) && !watchdog)
395 /* return 1 if INTR asserted */
396 if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
399 /* return 1 if Device INTR asserted */
400 if (readb((void __iomem *)addr) & 8)
401 return 0; /* return 1; */
406 static int siimage_dma_test_irq(ide_drive_t *drive)
408 if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
409 return siimage_mmio_dma_test_irq(drive);
411 return siimage_io_dma_test_irq(drive);
415 * sil_sata_reset_poll - wait for SATA reset
416 * @drive: drive we are resetting
418 * Poll the SATA phy and see whether it has come back from the dead
422 static int sil_sata_reset_poll(ide_drive_t *drive)
424 ide_hwif_t *hwif = drive->hwif;
425 void __iomem *sata_status_addr
426 = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
428 if (sata_status_addr) {
429 /* SATA Status is available only when in MMIO mode */
430 u32 sata_stat = readl(sata_status_addr);
432 if ((sata_stat & 0x03) != 0x03) {
433 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
434 hwif->name, sata_stat);
443 * sil_sata_pre_reset - reset hook
444 * @drive: IDE device being reset
446 * For the SATA devices we need to handle recalibration/geometry
450 static void sil_sata_pre_reset(ide_drive_t *drive)
452 if (drive->media == ide_disk) {
453 drive->special.b.set_geometry = 0;
454 drive->special.b.recalibrate = 0;
459 * init_chipset_siimage - set up an SI device
462 * Perform the initial PCI set up for this device. Attempt to switch
463 * to 133 MHz clocking if the system isn't already set up to do it.
466 static unsigned int init_chipset_siimage(struct pci_dev *dev)
468 struct ide_host *host = pci_get_drvdata(dev);
469 void __iomem *ioaddr = host->host_priv;
470 unsigned long base, scsc_addr;
471 u8 rev = dev->revision, tmp;
473 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
478 base = (unsigned long)ioaddr;
480 if (ioaddr && pdev_is_sata(dev)) {
483 /* make sure IDE0/1 interrupts are not masked */
484 irq_mask = (1 << 22) | (1 << 23);
485 tmp32 = readl(ioaddr + 0x48);
486 if (tmp32 & irq_mask) {
488 writel(tmp32, ioaddr + 0x48);
489 readl(ioaddr + 0x48); /* flush */
491 writel(0, ioaddr + 0x148);
492 writel(0, ioaddr + 0x1C8);
495 sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
496 sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
498 scsc_addr = base ? (base + 0x4A) : 0x8A;
499 tmp = sil_ioread8(dev, scsc_addr);
501 switch (tmp & 0x30) {
503 /* On 100 MHz clocking, try and switch to 133 MHz */
504 sil_iowrite8(dev, tmp | 0x10, scsc_addr);
507 /* Clocking is disabled, attempt to force 133MHz clocking. */
508 sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
510 /* On 133Mhz clocking. */
513 /* On PCIx2 clocking. */
517 tmp = sil_ioread8(dev, scsc_addr);
519 sil_iowrite8 (dev, 0x72, base + 0xA1);
520 sil_iowrite16(dev, 0x328A, base + 0xA2);
521 sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
522 sil_iowrite32(dev, 0x43924392, base + 0xA8);
523 sil_iowrite32(dev, 0x40094009, base + 0xAC);
524 sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
525 sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
526 sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
527 sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
528 sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
530 if (base && pdev_is_sata(dev)) {
531 writel(0xFFFF0000, ioaddr + 0x108);
532 writel(0xFFFF0000, ioaddr + 0x188);
533 writel(0x00680000, ioaddr + 0x148);
534 writel(0x00680000, ioaddr + 0x1C8);
537 /* report the clocking mode of the controller */
538 if (!pdev_is_sata(dev)) {
539 static const char *clk_str[] =
540 { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
543 printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
544 pci_name(dev), clk_str[tmp & 3]);
551 * init_mmio_iops_siimage - set up the iops for MMIO
552 * @hwif: interface to set up
554 * The basic setup here is fairly simple, we can use standard MMIO
555 * operations. However we do have to set the taskfile register offsets
556 * by hand as there isn't a standard defined layout for them this time.
558 * The hardware supports buffered taskfiles and also some rather nice
559 * extended PRD tables. For better SI3112 support use the libata driver
562 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
564 struct pci_dev *dev = to_pci_dev(hwif->dev);
565 struct ide_host *host = pci_get_drvdata(dev);
566 void *addr = host->host_priv;
567 u8 ch = hwif->channel;
568 struct ide_io_ports *io_ports = &hwif->io_ports;
572 * Fill in the basic hwif bits
574 hwif->host_flags |= IDE_HFLAG_MMIO;
576 hwif->hwif_data = addr;
579 * Now set up the hw. We have to do this ourselves as the
580 * MMIO layout isn't the same as the standard port based I/O.
582 memset(io_ports, 0, sizeof(*io_ports));
584 base = (unsigned long)addr;
591 * The buffered task file doesn't have status/control, so we
592 * can't currently use it sanely since we want to use LBA48 mode.
594 io_ports->data_addr = base;
595 io_ports->error_addr = base + 1;
596 io_ports->nsect_addr = base + 2;
597 io_ports->lbal_addr = base + 3;
598 io_ports->lbam_addr = base + 4;
599 io_ports->lbah_addr = base + 5;
600 io_ports->device_addr = base + 6;
601 io_ports->status_addr = base + 7;
602 io_ports->ctl_addr = base + 10;
604 if (pdev_is_sata(dev)) {
605 base = (unsigned long)addr;
608 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
609 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
610 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
613 hwif->irq = dev->irq;
615 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
618 static int is_dev_seagate_sata(ide_drive_t *drive)
620 const char *s = (const char *)&drive->id[ATA_ID_PROD];
621 unsigned len = strnlen(s, ATA_ID_PROD_LEN);
623 if ((len > 4) && (!memcmp(s, "ST", 2)))
624 if ((!memcmp(s + len - 2, "AS", 2)) ||
625 (!memcmp(s + len - 3, "ASL", 3))) {
626 printk(KERN_INFO "%s: applying pessimistic Seagate "
627 "errata fix\n", drive->name);
635 * sil_quirkproc - post probe fixups
638 * Called after drive probe we use this to decide whether the
639 * Seagate fixup must be applied. This used to be in init_iops but
640 * that can occur before we know what drives are present.
643 static void sil_quirkproc(ide_drive_t *drive)
645 ide_hwif_t *hwif = drive->hwif;
647 /* Try and rise the rqsize */
648 if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
653 * init_iops_siimage - set up iops
654 * @hwif: interface to set up
656 * Do the basic setup for the SIIMAGE hardware interface
657 * and then do the MMIO setup if we can. This is the first
658 * look in we get for setting up the hwif so that we
659 * can get the iops right before using them.
662 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
664 struct pci_dev *dev = to_pci_dev(hwif->dev);
665 struct ide_host *host = pci_get_drvdata(dev);
667 hwif->hwif_data = NULL;
669 /* Pessimal until we finish probing */
673 init_mmio_iops_siimage(hwif);
677 * sil_cable_detect - cable detection
678 * @hwif: interface to check
680 * Check for the presence of an ATA66 capable cable on the interface.
683 static u8 sil_cable_detect(ide_hwif_t *hwif)
685 struct pci_dev *dev = to_pci_dev(hwif->dev);
686 unsigned long addr = siimage_selreg(hwif, 0);
687 u8 ata66 = sil_ioread8(dev, addr);
689 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
692 static const struct ide_port_ops sil_pata_port_ops = {
693 .set_pio_mode = sil_set_pio_mode,
694 .set_dma_mode = sil_set_dma_mode,
695 .quirkproc = sil_quirkproc,
696 .udma_filter = sil_pata_udma_filter,
697 .cable_detect = sil_cable_detect,
700 static const struct ide_port_ops sil_sata_port_ops = {
701 .set_pio_mode = sil_set_pio_mode,
702 .set_dma_mode = sil_set_dma_mode,
703 .reset_poll = sil_sata_reset_poll,
704 .pre_reset = sil_sata_pre_reset,
705 .quirkproc = sil_quirkproc,
706 .udma_filter = sil_sata_udma_filter,
707 .cable_detect = sil_cable_detect,
710 static const struct ide_dma_ops sil_dma_ops = {
711 .dma_host_set = ide_dma_host_set,
712 .dma_setup = ide_dma_setup,
713 .dma_exec_cmd = ide_dma_exec_cmd,
714 .dma_start = ide_dma_start,
715 .dma_end = __ide_dma_end,
716 .dma_test_irq = siimage_dma_test_irq,
717 .dma_timeout = ide_dma_timeout,
718 .dma_lost_irq = ide_dma_lost_irq,
721 #define DECLARE_SII_DEV(p_ops) \
724 .init_chipset = init_chipset_siimage, \
725 .init_iops = init_iops_siimage, \
727 .dma_ops = &sil_dma_ops, \
728 .pio_mask = ATA_PIO4, \
729 .mwdma_mask = ATA_MWDMA2, \
730 .udma_mask = ATA_UDMA6, \
733 static const struct ide_port_info siimage_chipsets[] __devinitdata = {
734 /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops),
735 /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops)
739 * siimage_init_one - PCI layer discovery entry
741 * @id: ident table entry
743 * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
744 * We then use the IDE PCI generic helper to do most of the work.
747 static int __devinit siimage_init_one(struct pci_dev *dev,
748 const struct pci_device_id *id)
750 void __iomem *ioaddr = NULL;
751 resource_size_t bar5 = pci_resource_start(dev, 5);
752 unsigned long barsize = pci_resource_len(dev, 5);
754 struct ide_port_info d;
755 u8 idx = id->driver_data;
758 d = siimage_chipsets[idx];
761 static int first = 1;
764 printk(KERN_INFO DRV_NAME ": For full SATA support you "
765 "should use the libata sata_sil module.\n");
769 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
772 rc = pci_enable_device(dev);
776 pci_read_config_byte(dev, 0x8A, &BA5_EN);
777 if ((BA5_EN & 0x01) || bar5) {
779 * Drop back to PIO if we can't map the MMIO. Some systems
780 * seem to get terminally confused in the PCI spaces.
782 if (!request_mem_region(bar5, barsize, d.name)) {
783 printk(KERN_WARNING DRV_NAME " %s: MMIO ports not "
784 "available\n", pci_name(dev));
786 ioaddr = ioremap(bar5, barsize);
788 release_mem_region(bar5, barsize);
792 rc = ide_pci_init_one(dev, &d, ioaddr);
796 release_mem_region(bar5, barsize);
798 pci_disable_device(dev);
804 static void __devexit siimage_remove(struct pci_dev *dev)
806 struct ide_host *host = pci_get_drvdata(dev);
807 void __iomem *ioaddr = host->host_priv;
812 resource_size_t bar5 = pci_resource_start(dev, 5);
813 unsigned long barsize = pci_resource_len(dev, 5);
816 release_mem_region(bar5, barsize);
819 pci_disable_device(dev);
822 static const struct pci_device_id siimage_pci_tbl[] = {
823 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
824 #ifdef CONFIG_BLK_DEV_IDE_SATA
825 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
826 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 },
830 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
832 static struct pci_driver driver = {
834 .id_table = siimage_pci_tbl,
835 .probe = siimage_init_one,
836 .remove = __devexit_p(siimage_remove),
837 .suspend = ide_pci_suspend,
838 .resume = ide_pci_resume,
841 static int __init siimage_ide_init(void)
843 return ide_pci_register_driver(&driver);
846 static void __exit siimage_ide_exit(void)
848 pci_unregister_driver(&driver);
851 module_init(siimage_ide_init);
852 module_exit(siimage_ide_exit);
854 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
855 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
856 MODULE_LICENSE("GPL");