2 * linux/drivers/ide/pci/sl82c105.c
4 * SL82C105/Winbond 553 IDE driver
8 * Drive tuning added from Rebel.com's kernel sources
9 * -- Russell King (15/11/98) linux@arm.linux.org.uk
11 * Merge in Russell's HW workarounds, fix various problems
12 * with the timing registers setup.
13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
15 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
18 #include <linux/types.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/timer.h>
23 #include <linux/ioport.h>
24 #include <linux/interrupt.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/pci.h>
28 #include <linux/ide.h>
36 #define DBG(arg) printk arg
41 * SL82C105 PCI config register 0x40 bits.
43 #define CTRL_IDE_IRQB (1 << 30)
44 #define CTRL_IDE_IRQA (1 << 28)
45 #define CTRL_LEGIRQ (1 << 11)
46 #define CTRL_P1F16 (1 << 5)
47 #define CTRL_P1EN (1 << 4)
48 #define CTRL_P0F16 (1 << 1)
49 #define CTRL_P0EN (1 << 0)
52 * Convert a PIO mode and cycle time to the required on/off times
53 * for the interface. This has protection against runaway timings.
55 static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
57 unsigned int cmd_on, cmd_off;
60 cmd_on = (ide_pio_timings[pio].active_time + 29) / 30;
61 cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
69 if (pio > 2 || ide_dev_has_iordy(drive->id))
72 return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
76 * Configure the chipset for PIO mode.
78 static void sl82c105_tune_pio(ide_drive_t *drive, const u8 pio)
80 struct pci_dev *dev = HWIF(drive)->pci_dev;
81 int reg = 0x44 + drive->dn * 4;
84 drv_ctrl = get_pio_timings(drive, pio);
87 * Store the PIO timings so that we can restore them
88 * in case DMA will be turned off...
90 drive->drive_data &= 0xffff0000;
91 drive->drive_data |= drv_ctrl;
93 if (!drive->using_dma) {
95 * If we are actually using MW DMA, then we can not
96 * reprogram the interface drive control register.
98 pci_write_config_word(dev, reg, drv_ctrl);
99 pci_read_config_word (dev, reg, &drv_ctrl);
102 printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
103 ide_xfer_verbose(pio + XFER_PIO_0),
104 ide_pio_cycle_time(drive, pio), drv_ctrl);
108 * Configure the drive and chipset for a new transfer speed.
110 static int sl82c105_tune_chipset(ide_drive_t *drive, const u8 speed)
112 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
115 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
116 drive->name, ide_xfer_verbose(speed)));
122 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
125 * Store the DMA timings so that we can actually program
126 * them when DMA will be turned on...
128 drive->drive_data &= 0x0000ffff;
129 drive->drive_data |= (unsigned long)drv_ctrl << 16;
132 * If we are already using DMA, we just reprogram
133 * the drive control register.
135 if (drive->using_dma) {
136 struct pci_dev *dev = HWIF(drive)->pci_dev;
137 int reg = 0x44 + drive->dn * 4;
139 pci_write_config_word(dev, reg, drv_ctrl);
146 return ide_config_drive_speed(drive, speed);
150 * Check to see if the drive and chipset are capable of DMA mode.
152 static int sl82c105_ide_dma_check(ide_drive_t *drive)
154 DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));
156 if (ide_tune_dma(drive))
163 * The SL82C105 holds off all IDE interrupts while in DMA mode until
164 * all DMA activity is completed. Sometimes this causes problems (eg,
165 * when the drive wants to report an error condition).
167 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
168 * state machine. We need to kick this to work around various bugs.
170 static inline void sl82c105_reset_host(struct pci_dev *dev)
174 pci_read_config_word(dev, 0x7e, &val);
175 pci_write_config_word(dev, 0x7e, val | (1 << 2));
176 pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
180 * If we get an IRQ timeout, it might be that the DMA state machine
181 * got confused. Fix from Todd Inglett. Details from Winbond.
183 * This function is called when the IDE timer expires, the drive
184 * indicates that it is READY, and we were waiting for DMA to complete.
186 static void sl82c105_dma_lost_irq(ide_drive_t *drive)
188 ide_hwif_t *hwif = HWIF(drive);
189 struct pci_dev *dev = hwif->pci_dev;
190 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
193 printk("sl82c105: lost IRQ, resetting host\n");
196 * Check the raw interrupt from the drive.
198 pci_read_config_dword(dev, 0x40, &val);
200 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
203 * Was DMA enabled? If so, disable it - we're resetting the
204 * host. The IDE layer will be handling the drive for us.
206 dma_cmd = inb(hwif->dma_command);
208 outb(dma_cmd & ~1, hwif->dma_command);
209 printk("sl82c105: DMA was enabled\n");
212 sl82c105_reset_host(dev);
216 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
217 * Winbond recommend that the DMA state machine is reset prior to
218 * setting the bus master DMA enable bit.
220 * The generic IDE core will have disabled the BMEN bit before this
221 * function is called.
223 static void sl82c105_dma_start(ide_drive_t *drive)
225 ide_hwif_t *hwif = HWIF(drive);
226 struct pci_dev *dev = hwif->pci_dev;
228 sl82c105_reset_host(dev);
229 ide_dma_start(drive);
232 static void sl82c105_dma_timeout(ide_drive_t *drive)
234 DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));
236 sl82c105_reset_host(HWIF(drive)->pci_dev);
237 ide_dma_timeout(drive);
240 static int sl82c105_ide_dma_on(ide_drive_t *drive)
242 struct pci_dev *dev = HWIF(drive)->pci_dev;
243 int rc, reg = 0x44 + drive->dn * 4;
245 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
247 rc = __ide_dma_on(drive);
249 pci_write_config_word(dev, reg, drive->drive_data >> 16);
251 printk(KERN_INFO "%s: DMA enabled\n", drive->name);
256 static void sl82c105_dma_off_quietly(ide_drive_t *drive)
258 struct pci_dev *dev = HWIF(drive)->pci_dev;
259 int reg = 0x44 + drive->dn * 4;
261 DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
263 pci_write_config_word(dev, reg, drive->drive_data);
265 ide_dma_off_quietly(drive);
269 * Ok, that is nasty, but we must make sure the DMA timings
270 * won't be used for a PIO access. The solution here is
271 * to make sure the 16 bits mode is diabled on the channel
272 * when DMA is enabled, thus causing the chip to use PIO0
273 * timings for those operations.
275 static void sl82c105_selectproc(ide_drive_t *drive)
277 ide_hwif_t *hwif = HWIF(drive);
278 struct pci_dev *dev = hwif->pci_dev;
281 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
283 mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
284 old = val = (u32)pci_get_drvdata(dev);
285 if (drive->using_dma)
290 pci_write_config_dword(dev, 0x40, val);
291 pci_set_drvdata(dev, (void *)val);
296 * ATA reset will clear the 16 bits mode in the control
297 * register, we need to update our cache
299 static void sl82c105_resetproc(ide_drive_t *drive)
301 struct pci_dev *dev = HWIF(drive)->pci_dev;
304 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
306 pci_read_config_dword(dev, 0x40, &val);
307 pci_set_drvdata(dev, (void *)val);
311 * We only deal with PIO mode here - DMA mode 'using_dma' is not
312 * initialised at the point that this function is called.
314 static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
316 sl82c105_tune_pio(drive, pio);
318 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
322 * Return the revision of the Winbond bridge
323 * which this function is part of.
325 static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
327 struct pci_dev *bridge;
330 * The bridge should be part of the same device, but function 0.
332 bridge = pci_get_bus_and_slot(dev->bus->number,
333 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
338 * Make sure it is a Winbond 553 and is an ISA bridge.
340 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
341 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
342 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
347 * We need to find function 0's revision, not function 1
351 return bridge->revision;
355 * Enable the PCI device
357 * --BenH: It's arch fixup code that should enable channels that
358 * have not been enabled by firmware. I decided we can still enable
359 * channel 0 here at least, but channel 1 has to be enabled by
360 * firmware or arch code. We still set both to 16 bits mode.
362 static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
366 DBG(("init_chipset_sl82c105()\n"));
368 pci_read_config_dword(dev, 0x40, &val);
369 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
370 pci_write_config_dword(dev, 0x40, val);
371 pci_set_drvdata(dev, (void *)val);
377 * Initialise IDE channel
379 static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
383 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
385 hwif->set_pio_mode = &sl82c105_set_pio_mode;
386 hwif->speedproc = &sl82c105_tune_chipset;
387 hwif->selectproc = &sl82c105_selectproc;
388 hwif->resetproc = &sl82c105_resetproc;
391 * We support 32-bit I/O on this interface, and
392 * it doesn't have problems with interrupts.
394 hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
395 hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
398 * We always autotune PIO, this is done before DMA is checked,
399 * so there's no risk of accidentally disabling DMA
401 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
406 rev = sl82c105_bridge_revision(hwif->pci_dev);
409 * Never ever EVER under any circumstances enable
410 * DMA when the bridge is this old.
412 printk(" %s: Winbond W83C553 bridge revision %d, "
413 "BM-DMA disabled\n", hwif->name, rev);
418 hwif->mwdma_mask = 0x07;
420 hwif->ide_dma_check = &sl82c105_ide_dma_check;
421 hwif->ide_dma_on = &sl82c105_ide_dma_on;
422 hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
423 hwif->dma_lost_irq = &sl82c105_dma_lost_irq;
424 hwif->dma_start = &sl82c105_dma_start;
425 hwif->dma_timeout = &sl82c105_dma_timeout;
429 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
432 hwif->serialized = hwif->mate->serialized = 1;
435 static ide_pci_device_t sl82c105_chipset __devinitdata = {
437 .init_chipset = init_chipset_sl82c105,
438 .init_hwif = init_hwif_sl82c105,
439 .autodma = NOAUTODMA,
440 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
441 .bootable = ON_BOARD,
442 .pio_mask = ATA_PIO5,
445 static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
447 return ide_setup_pci_device(dev, &sl82c105_chipset);
450 static struct pci_device_id sl82c105_pci_tbl[] = {
451 { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
454 MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
456 static struct pci_driver driver = {
457 .name = "W82C105_IDE",
458 .id_table = sl82c105_pci_tbl,
459 .probe = sl82c105_init_one,
462 static int __init sl82c105_ide_init(void)
464 return ide_pci_register_driver(&driver);
467 module_init(sl82c105_ide_init);
469 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
470 MODULE_LICENSE("GPL");