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1 /*
2  *  linux/drivers/ide/pci/slc90e66.c    Version 0.14    February 8, 2007
3  *
4  *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5  *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
6  *
7  * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
8  * but this keeps the ISA-Bridge and slots alive.
9  *
10  */
11
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/hdreg.h>
18 #include <linux/ide.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21
22 #include <asm/io.h>
23
24 static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
25         switch(xfer_rate) {
26                 case XFER_UDMA_4:
27                 case XFER_UDMA_3:
28                 case XFER_UDMA_2:
29                 case XFER_UDMA_1:
30                 case XFER_UDMA_0:
31                 case XFER_MW_DMA_2:
32                 case XFER_PIO_4:
33                         return 4;
34                 case XFER_MW_DMA_1:
35                 case XFER_PIO_3:
36                         return 3;
37                 case XFER_SW_DMA_2:
38                 case XFER_PIO_2:
39                         return 2;
40                 case XFER_MW_DMA_0:
41                 case XFER_SW_DMA_1:
42                 case XFER_SW_DMA_0:
43                 case XFER_PIO_1:
44                 case XFER_PIO_0:
45                 case XFER_PIO_SLOW:
46                 default:
47                         return 0;
48         }
49 }
50
51 static void slc90e66_tune_pio (ide_drive_t *drive, u8 pio)
52 {
53         ide_hwif_t *hwif        = HWIF(drive);
54         struct pci_dev *dev     = hwif->pci_dev;
55         int is_slave            = drive->dn & 1;
56         int master_port         = hwif->channel ? 0x42 : 0x40;
57         int slave_port          = 0x44;
58         unsigned long flags;
59         u16 master_data;
60         u8 slave_data;
61         int control = 0;
62                                      /* ISP  RTC */
63         static const u8 timings[][2]= {
64                                         { 0, 0 },
65                                         { 0, 0 },
66                                         { 1, 0 },
67                                         { 2, 1 },
68                                         { 2, 3 }, };
69
70         spin_lock_irqsave(&ide_lock, flags);
71         pci_read_config_word(dev, master_port, &master_data);
72
73         if (pio > 1)
74                 control |= 1;   /* Programmable timing on */
75         if (drive->media == ide_disk)
76                 control |= 4;   /* Prefetch, post write */
77         if (pio > 2)
78                 control |= 2;   /* IORDY */
79         if (is_slave) {
80                 master_data |=  0x4000;
81                 master_data &= ~0x0070;
82                 if (pio > 1) {
83                         /* Set PPE, IE and TIME */
84                         master_data |= control << 4;
85                 }
86                 pci_read_config_byte(dev, slave_port, &slave_data);
87                 slave_data &= hwif->channel ? 0x0f : 0xf0;
88                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
89                                (hwif->channel ? 4 : 0);
90         } else {
91                 master_data &= ~0x3307;
92                 if (pio > 1) {
93                         /* enable PPE, IE and TIME */
94                         master_data |= control;
95                 }
96                 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
97         }
98         pci_write_config_word(dev, master_port, master_data);
99         if (is_slave)
100                 pci_write_config_byte(dev, slave_port, slave_data);
101         spin_unlock_irqrestore(&ide_lock, flags);
102 }
103
104 static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
105 {
106         pio = ide_get_best_pio_mode(drive, pio, 4);
107         slc90e66_tune_pio(drive, pio);
108         (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
109 }
110
111 static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
112 {
113         ide_hwif_t *hwif        = HWIF(drive);
114         struct pci_dev *dev     = hwif->pci_dev;
115         u8 maslave              = hwif->channel ? 0x42 : 0x40;
116         u8 speed                = ide_rate_filter(drive, xferspeed);
117         int sitre = 0, a_speed  = 7 << (drive->dn * 4);
118         int u_speed = 0, u_flag = 1 << drive->dn;
119         u16                     reg4042, reg44, reg48, reg4a;
120
121         pci_read_config_word(dev, maslave, &reg4042);
122         sitre = (reg4042 & 0x4000) ? 1 : 0;
123         pci_read_config_word(dev, 0x44, &reg44);
124         pci_read_config_word(dev, 0x48, &reg48);
125         pci_read_config_word(dev, 0x4a, &reg4a);
126
127         switch(speed) {
128                 case XFER_UDMA_4:       u_speed = 4 << (drive->dn * 4); break;
129                 case XFER_UDMA_3:       u_speed = 3 << (drive->dn * 4); break;
130                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
131                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
132                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
133                 case XFER_MW_DMA_2:
134                 case XFER_MW_DMA_1:
135                 case XFER_SW_DMA_2:     break;
136                 case XFER_PIO_4:
137                 case XFER_PIO_3:
138                 case XFER_PIO_2:
139                 case XFER_PIO_0:        break;
140                 default:                return -1;
141         }
142
143         if (speed >= XFER_UDMA_0) {
144                 if (!(reg48 & u_flag))
145                         pci_write_config_word(dev, 0x48, reg48|u_flag);
146                 /* FIXME: (reg4a & a_speed) ? */
147                 if ((reg4a & u_speed) != u_speed) {
148                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
149                         pci_read_config_word(dev, 0x4a, &reg4a);
150                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
151                 }
152         } else {
153                 if (reg48 & u_flag)
154                         pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
155                 if (reg4a & a_speed)
156                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
157         }
158
159         slc90e66_tune_pio(drive, slc90e66_dma_2_pio(speed));
160         return ide_config_drive_speed(drive, speed);
161 }
162
163 static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
164 {
165         drive->init_speed = 0;
166
167         if (ide_tune_dma(drive))
168                 return 0;
169
170         if (ide_use_fast_pio(drive))
171                 slc90e66_tune_drive(drive, 255);
172
173         return -1;
174 }
175
176 static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
177 {
178         u8 reg47 = 0;
179         u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */
180
181         hwif->autodma = 0;
182
183         if (!hwif->irq)
184                 hwif->irq = hwif->channel ? 15 : 14;
185
186         hwif->speedproc = &slc90e66_tune_chipset;
187         hwif->tuneproc  = &slc90e66_tune_drive;
188
189         pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
190
191         if (!hwif->dma_base) {
192                 hwif->drives[0].autotune = 1;
193                 hwif->drives[1].autotune = 1;
194                 return;
195         }
196
197         hwif->atapi_dma = 1;
198         hwif->ultra_mask = 0x1f;
199         hwif->mwdma_mask = 0x06;
200         hwif->swdma_mask = 0x04;
201
202         if (hwif->cbl != ATA_CBL_PATA40_SHORT)
203                 /* bit[0(1)]: 0:80, 1:40 */
204                 hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
205
206         hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
207
208         if (!noautodma)
209                 hwif->autodma = 1;
210         hwif->drives[0].autodma = hwif->autodma;
211         hwif->drives[1].autodma = hwif->autodma;
212 }
213
214 static ide_pci_device_t slc90e66_chipset __devinitdata = {
215         .name           = "SLC90E66",
216         .init_hwif      = init_hwif_slc90e66,
217         .autodma        = AUTODMA,
218         .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
219         .bootable       = ON_BOARD,
220         .pio_mask       = ATA_PIO4,
221 };
222
223 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
224 {
225         return ide_setup_pci_device(dev, &slc90e66_chipset);
226 }
227
228 static struct pci_device_id slc90e66_pci_tbl[] = {
229         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
230         { 0, },
231 };
232 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
233
234 static struct pci_driver driver = {
235         .name           = "SLC90e66_IDE",
236         .id_table       = slc90e66_pci_tbl,
237         .probe          = slc90e66_init_one,
238 };
239
240 static int __init slc90e66_ide_init(void)
241 {
242         return ide_pci_register_driver(&driver);
243 }
244
245 module_init(slc90e66_ide_init);
246
247 MODULE_AUTHOR("Andre Hedrick");
248 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
249 MODULE_LICENSE("GPL");