2 * IBM eServer eHCA Infiniband device driver for Linux on POWER
6 * Authors: Joachim Fenkes <fenkes@de.ibm.com>
7 * Stefan Roscher <stefan.roscher@de.ibm.com>
8 * Waleri Fomin <fomin@de.ibm.com>
9 * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
10 * Reinhard Ernst <rernst@de.ibm.com>
11 * Heiko J Schick <schickhj@de.ibm.com>
13 * Copyright (c) 2005 IBM Corporation
15 * All rights reserved.
17 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
25 * Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following disclaimer.
28 * Redistributions in binary form must reproduce the above copyright notice,
29 * this list of conditions and the following disclaimer in the documentation
30 * and/or other materials
31 * provided with the distribution.
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
40 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
41 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 * POSSIBILITY OF SUCH DAMAGE.
46 #include "ehca_classes.h"
47 #include "ehca_tools.h"
49 #include "ehca_iverbs.h"
53 static struct kmem_cache *qp_cache;
56 * attributes not supported by query qp
58 #define QP_ATTR_QUERY_NOT_SUPPORTED (IB_QP_MAX_DEST_RD_ATOMIC | \
59 IB_QP_MAX_QP_RD_ATOMIC | \
60 IB_QP_ACCESS_FLAGS | \
61 IB_QP_EN_SQD_ASYNC_NOTIFY)
64 * ehca (internal) qp state values
77 * qp state transitions as defined by IB Arch Rel 1.1 page 431
79 enum ib_qp_statetrans {
91 IB_QPST_MAX /* nr of transitions, this must be last!!! */
95 * ib2ehca_qp_state maps IB to ehca qp_state
96 * returns ehca qp state corresponding to given ib qp state
98 static inline enum ehca_qp_state ib2ehca_qp_state(enum ib_qp_state ib_qp_state)
100 switch (ib_qp_state) {
102 return EHCA_QPS_RESET;
104 return EHCA_QPS_INIT;
116 ehca_gen_err("invalid ib_qp_state=%x", ib_qp_state);
122 * ehca2ib_qp_state maps ehca to IB qp_state
123 * returns ib qp state corresponding to given ehca qp state
125 static inline enum ib_qp_state ehca2ib_qp_state(enum ehca_qp_state
128 switch (ehca_qp_state) {
144 ehca_gen_err("invalid ehca_qp_state=%x", ehca_qp_state);
150 * ehca_qp_type used as index for req_attr and opt_attr of
151 * struct ehca_modqp_statetrans
162 * ib2ehcaqptype maps Ib to ehca qp_type
163 * returns ehca qp type corresponding to ib qp type
165 static inline enum ehca_qp_type ib2ehcaqptype(enum ib_qp_type ibqptype)
178 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
183 static inline enum ib_qp_statetrans get_modqp_statetrans(int ib_fromstate,
187 switch (ib_tostate) {
189 index = IB_QPST_ANY2RESET;
192 switch (ib_fromstate) {
194 index = IB_QPST_RESET2INIT;
197 index = IB_QPST_INIT2INIT;
202 if (ib_fromstate == IB_QPS_INIT)
203 index = IB_QPST_INIT2RTR;
206 switch (ib_fromstate) {
208 index = IB_QPST_RTR2RTS;
211 index = IB_QPST_RTS2RTS;
214 index = IB_QPST_SQD2RTS;
217 index = IB_QPST_SQE2RTS;
222 if (ib_fromstate == IB_QPS_RTS)
223 index = IB_QPST_RTS2SQD;
228 index = IB_QPST_ANY2ERR;
237 * ibqptype2servicetype returns hcp service type corresponding to given
238 * ib qp type used by create_qp()
240 static inline int ibqptype2servicetype(enum ib_qp_type ibqptype)
252 case IB_QPT_RAW_IPV6:
257 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
263 * init userspace queue info from ipz_queue data
265 static inline void queue2resp(struct ipzu_queue_resp *resp,
266 struct ipz_queue *queue)
268 resp->qe_size = queue->qe_size;
269 resp->act_nr_of_sg = queue->act_nr_of_sg;
270 resp->queue_length = queue->queue_length;
271 resp->pagesize = queue->pagesize;
272 resp->toggle_state = queue->toggle_state;
273 resp->offset = queue->offset;
277 * init_qp_queue initializes/constructs r/squeue and registers queue pages.
279 static inline int init_qp_queue(struct ehca_shca *shca,
281 struct ehca_qp *my_qp,
282 struct ipz_queue *queue,
285 struct ehca_alloc_queue_parms *parms,
288 int ret, cnt, ipz_rc, nr_q_pages;
291 struct ib_device *ib_dev = &shca->ib_device;
292 struct ipz_adapter_handle ipz_hca_handle = shca->ipz_hca_handle;
294 if (!parms->queue_size)
297 if (parms->is_small) {
299 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
300 128 << parms->page_size,
301 wqe_size, parms->act_nr_sges, 1);
303 nr_q_pages = parms->queue_size;
304 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
305 EHCA_PAGESIZE, wqe_size,
306 parms->act_nr_sges, 0);
310 ehca_err(ib_dev, "Cannot allocate page for queue. ipz_rc=%i",
315 /* register queue pages */
316 for (cnt = 0; cnt < nr_q_pages; cnt++) {
317 vpage = ipz_qpageit_get_inc(queue);
319 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
320 "failed p_vpage= %p", vpage);
324 rpage = virt_to_abs(vpage);
326 h_ret = hipz_h_register_rpage_qp(ipz_hca_handle,
327 my_qp->ipz_qp_handle,
329 rpage, parms->is_small ? 0 : 1,
330 my_qp->galpas.kernel);
331 if (cnt == (nr_q_pages - 1)) { /* last page! */
332 if (h_ret != expected_hret) {
333 ehca_err(ib_dev, "hipz_qp_register_rpage() "
335 ret = ehca2ib_return_code(h_ret);
338 vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue);
340 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
341 "should not succeed vpage=%p", vpage);
346 if (h_ret != H_PAGE_REGISTERED) {
347 ehca_err(ib_dev, "hipz_qp_register_rpage() "
349 ret = ehca2ib_return_code(h_ret);
355 ipz_qeit_reset(queue);
360 ipz_queue_dtor(pd, queue);
364 static inline int ehca_calc_wqe_size(int act_nr_sge, int is_llqp)
367 return 128 << act_nr_sge;
369 return offsetof(struct ehca_wqe,
370 u.nud.sg_list[act_nr_sge]);
373 static void ehca_determine_small_queue(struct ehca_alloc_queue_parms *queue,
374 int req_nr_sge, int is_llqp)
376 u32 wqe_size, q_size;
377 int act_nr_sge = req_nr_sge;
380 /* round up #SGEs so WQE size is a power of 2 */
381 for (act_nr_sge = 4; act_nr_sge <= 252;
382 act_nr_sge = 4 + 2 * act_nr_sge)
383 if (act_nr_sge >= req_nr_sge)
386 wqe_size = ehca_calc_wqe_size(act_nr_sge, is_llqp);
387 q_size = wqe_size * (queue->max_wr + 1);
390 queue->page_size = 2;
391 else if (q_size <= 1024)
392 queue->page_size = 3;
394 queue->page_size = 0;
396 queue->is_small = (queue->page_size != 0);
400 * Create an ib_qp struct that is either a QP or an SRQ, depending on
401 * the value of the is_srq parameter. If init_attr and srq_init_attr share
402 * fields, the field out of init_attr is used.
404 static struct ehca_qp *internal_create_qp(
406 struct ib_qp_init_attr *init_attr,
407 struct ib_srq_init_attr *srq_init_attr,
408 struct ib_udata *udata, int is_srq)
410 struct ehca_qp *my_qp;
411 struct ehca_pd *my_pd = container_of(pd, struct ehca_pd, ib_pd);
412 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
414 struct ib_ucontext *context = NULL;
417 int is_llqp = 0, has_srq = 0;
418 int qp_type, max_send_sge, max_recv_sge, ret;
420 /* h_call's out parameters */
421 struct ehca_alloc_qp_parms parms;
422 u32 swqe_size = 0, rwqe_size = 0, ib_qp_num;
425 if (!atomic_add_unless(&shca->num_qps, 1, ehca_max_qp)) {
426 ehca_err(pd->device, "Unable to create QP, max number of %i "
427 "QPs reached.", ehca_max_qp);
428 ehca_err(pd->device, "To increase the maximum number of QPs "
429 "use the number_of_qps module parameter.\n");
430 return ERR_PTR(-ENOSPC);
433 if (init_attr->create_flags) {
434 atomic_dec(&shca->num_qps);
435 return ERR_PTR(-EINVAL);
438 memset(&parms, 0, sizeof(parms));
439 qp_type = init_attr->qp_type;
441 if (init_attr->sq_sig_type != IB_SIGNAL_REQ_WR &&
442 init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) {
443 ehca_err(pd->device, "init_attr->sg_sig_type=%x not allowed",
444 init_attr->sq_sig_type);
445 atomic_dec(&shca->num_qps);
446 return ERR_PTR(-EINVAL);
450 if (qp_type & 0x80) {
452 parms.ext_type = EQPT_LLQP;
453 parms.ll_comp_flags = qp_type & LLQP_COMP_MASK;
456 init_attr->qp_type &= 0x1F;
458 /* handle SRQ base QPs */
459 if (init_attr->srq) {
460 struct ehca_qp *my_srq =
461 container_of(init_attr->srq, struct ehca_qp, ib_srq);
464 parms.ext_type = EQPT_SRQBASE;
465 parms.srq_qpn = my_srq->real_qp_num;
468 if (is_llqp && has_srq) {
469 ehca_err(pd->device, "LLQPs can't have an SRQ");
470 atomic_dec(&shca->num_qps);
471 return ERR_PTR(-EINVAL);
476 parms.ext_type = EQPT_SRQ;
477 parms.srq_limit = srq_init_attr->attr.srq_limit;
478 if (init_attr->cap.max_recv_sge > 3) {
479 ehca_err(pd->device, "no more than three SGEs "
480 "supported for SRQ pd=%p max_sge=%x",
481 pd, init_attr->cap.max_recv_sge);
482 atomic_dec(&shca->num_qps);
483 return ERR_PTR(-EINVAL);
488 if (qp_type != IB_QPT_UD &&
489 qp_type != IB_QPT_UC &&
490 qp_type != IB_QPT_RC &&
491 qp_type != IB_QPT_SMI &&
492 qp_type != IB_QPT_GSI) {
493 ehca_err(pd->device, "wrong QP Type=%x", qp_type);
494 atomic_dec(&shca->num_qps);
495 return ERR_PTR(-EINVAL);
501 if ((init_attr->cap.max_send_wr > 255) ||
502 (init_attr->cap.max_recv_wr > 255)) {
504 "Invalid Number of max_sq_wr=%x "
505 "or max_rq_wr=%x for RC LLQP",
506 init_attr->cap.max_send_wr,
507 init_attr->cap.max_recv_wr);
508 atomic_dec(&shca->num_qps);
509 return ERR_PTR(-EINVAL);
513 if (!EHCA_BMASK_GET(HCA_CAP_UD_LL_QP, shca->hca_cap)) {
514 ehca_err(pd->device, "UD LLQP not supported "
516 atomic_dec(&shca->num_qps);
517 return ERR_PTR(-ENOSYS);
519 if (!(init_attr->cap.max_send_sge <= 5
520 && init_attr->cap.max_send_sge >= 1
521 && init_attr->cap.max_recv_sge <= 5
522 && init_attr->cap.max_recv_sge >= 1)) {
524 "Invalid Number of max_send_sge=%x "
525 "or max_recv_sge=%x for UD LLQP",
526 init_attr->cap.max_send_sge,
527 init_attr->cap.max_recv_sge);
528 atomic_dec(&shca->num_qps);
529 return ERR_PTR(-EINVAL);
530 } else if (init_attr->cap.max_send_wr > 255) {
533 "max_send_wr=%x for UD QP_TYPE=%x",
534 init_attr->cap.max_send_wr, qp_type);
535 atomic_dec(&shca->num_qps);
536 return ERR_PTR(-EINVAL);
540 ehca_err(pd->device, "unsupported LL QP Type=%x",
542 atomic_dec(&shca->num_qps);
543 return ERR_PTR(-EINVAL);
546 int max_sge = (qp_type == IB_QPT_UD || qp_type == IB_QPT_SMI
547 || qp_type == IB_QPT_GSI) ? 250 : 252;
549 if (init_attr->cap.max_send_sge > max_sge
550 || init_attr->cap.max_recv_sge > max_sge) {
551 ehca_err(pd->device, "Invalid number of SGEs requested "
552 "send_sge=%x recv_sge=%x max_sge=%x",
553 init_attr->cap.max_send_sge,
554 init_attr->cap.max_recv_sge, max_sge);
555 atomic_dec(&shca->num_qps);
556 return ERR_PTR(-EINVAL);
560 if (pd->uobject && udata)
561 context = pd->uobject->context;
563 my_qp = kmem_cache_zalloc(qp_cache, GFP_KERNEL);
565 ehca_err(pd->device, "pd=%p not enough memory to alloc qp", pd);
566 atomic_dec(&shca->num_qps);
567 return ERR_PTR(-ENOMEM);
570 atomic_set(&my_qp->nr_events, 0);
571 init_waitqueue_head(&my_qp->wait_completion);
572 spin_lock_init(&my_qp->spinlock_s);
573 spin_lock_init(&my_qp->spinlock_r);
574 my_qp->qp_type = qp_type;
575 my_qp->ext_type = parms.ext_type;
576 my_qp->state = IB_QPS_RESET;
578 if (init_attr->recv_cq)
580 container_of(init_attr->recv_cq, struct ehca_cq, ib_cq);
581 if (init_attr->send_cq)
583 container_of(init_attr->send_cq, struct ehca_cq, ib_cq);
586 if (!idr_pre_get(&ehca_qp_idr, GFP_KERNEL)) {
588 ehca_err(pd->device, "Can't reserve idr resources.");
589 goto create_qp_exit0;
592 write_lock_irqsave(&ehca_qp_idr_lock, flags);
593 ret = idr_get_new(&ehca_qp_idr, my_qp, &my_qp->token);
594 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
595 } while (ret == -EAGAIN);
599 ehca_err(pd->device, "Can't allocate new idr entry.");
600 goto create_qp_exit0;
603 if (my_qp->token > 0x1FFFFFF) {
605 ehca_err(pd->device, "Invalid number of qp");
606 goto create_qp_exit1;
610 parms.srq_token = my_qp->token;
612 parms.servicetype = ibqptype2servicetype(qp_type);
613 if (parms.servicetype < 0) {
615 ehca_err(pd->device, "Invalid qp_type=%x", qp_type);
616 goto create_qp_exit1;
619 /* Always signal by WQE so we can hide circ. WQEs */
620 parms.sigtype = HCALL_SIGT_BY_WQE;
622 /* UD_AV CIRCUMVENTION */
623 max_send_sge = init_attr->cap.max_send_sge;
624 max_recv_sge = init_attr->cap.max_recv_sge;
625 if (parms.servicetype == ST_UD && !is_llqp) {
630 parms.token = my_qp->token;
631 parms.eq_handle = shca->eq.ipz_eq_handle;
632 parms.pd = my_pd->fw_pd;
634 parms.send_cq_handle = my_qp->send_cq->ipz_cq_handle;
636 parms.recv_cq_handle = my_qp->recv_cq->ipz_cq_handle;
638 parms.squeue.max_wr = init_attr->cap.max_send_wr;
639 parms.rqueue.max_wr = init_attr->cap.max_recv_wr;
640 parms.squeue.max_sge = max_send_sge;
641 parms.rqueue.max_sge = max_recv_sge;
643 /* RC QPs need one more SWQE for unsolicited ack circumvention */
644 if (qp_type == IB_QPT_RC)
645 parms.squeue.max_wr++;
647 if (EHCA_BMASK_GET(HCA_CAP_MINI_QP, shca->hca_cap)) {
649 ehca_determine_small_queue(
650 &parms.squeue, max_send_sge, is_llqp);
652 ehca_determine_small_queue(
653 &parms.rqueue, max_recv_sge, is_llqp);
655 (parms.squeue.is_small || parms.rqueue.is_small);
658 h_ret = hipz_h_alloc_resource_qp(shca->ipz_hca_handle, &parms);
659 if (h_ret != H_SUCCESS) {
660 ehca_err(pd->device, "h_alloc_resource_qp() failed h_ret=%li",
662 ret = ehca2ib_return_code(h_ret);
663 goto create_qp_exit1;
666 ib_qp_num = my_qp->real_qp_num = parms.real_qp_num;
667 my_qp->ipz_qp_handle = parms.qp_handle;
668 my_qp->galpas = parms.galpas;
670 swqe_size = ehca_calc_wqe_size(parms.squeue.act_nr_sges, is_llqp);
671 rwqe_size = ehca_calc_wqe_size(parms.rqueue.act_nr_sges, is_llqp);
676 parms.squeue.act_nr_sges = 1;
677 parms.rqueue.act_nr_sges = 1;
679 /* hide the extra WQE */
680 parms.squeue.act_nr_wqes--;
685 /* UD circumvention */
687 parms.squeue.act_nr_sges = 1;
688 parms.rqueue.act_nr_sges = 1;
690 parms.squeue.act_nr_sges -= 2;
691 parms.rqueue.act_nr_sges -= 2;
694 if (IB_QPT_GSI == qp_type || IB_QPT_SMI == qp_type) {
695 parms.squeue.act_nr_wqes = init_attr->cap.max_send_wr;
696 parms.rqueue.act_nr_wqes = init_attr->cap.max_recv_wr;
697 parms.squeue.act_nr_sges = init_attr->cap.max_send_sge;
698 parms.rqueue.act_nr_sges = init_attr->cap.max_recv_sge;
699 ib_qp_num = (qp_type == IB_QPT_SMI) ? 0 : 1;
708 /* initialize r/squeue and register queue pages */
711 shca, my_pd, my_qp, &my_qp->ipz_squeue, 0,
712 HAS_RQ(my_qp) ? H_PAGE_REGISTERED : H_SUCCESS,
713 &parms.squeue, swqe_size);
715 ehca_err(pd->device, "Couldn't initialize squeue "
716 "and pages ret=%i", ret);
717 goto create_qp_exit2;
719 nr_qes = my_qp->ipz_squeue.queue_length /
720 my_qp->ipz_squeue.qe_size;
721 my_qp->sq_map = vmalloc(nr_qes *
722 sizeof(struct ehca_qmap_entry));
723 if (!my_qp->sq_map) {
724 ehca_err(pd->device, "Couldn't allocate squeue "
726 goto create_qp_exit3;
732 shca, my_pd, my_qp, &my_qp->ipz_rqueue, 1,
733 H_SUCCESS, &parms.rqueue, rwqe_size);
735 ehca_err(pd->device, "Couldn't initialize rqueue "
736 "and pages ret=%i", ret);
737 goto create_qp_exit4;
742 my_qp->ib_srq.pd = &my_pd->ib_pd;
743 my_qp->ib_srq.device = my_pd->ib_pd.device;
745 my_qp->ib_srq.srq_context = init_attr->qp_context;
746 my_qp->ib_srq.event_handler = init_attr->event_handler;
748 my_qp->ib_qp.qp_num = ib_qp_num;
749 my_qp->ib_qp.pd = &my_pd->ib_pd;
750 my_qp->ib_qp.device = my_pd->ib_pd.device;
752 my_qp->ib_qp.recv_cq = init_attr->recv_cq;
753 my_qp->ib_qp.send_cq = init_attr->send_cq;
755 my_qp->ib_qp.qp_type = qp_type;
756 my_qp->ib_qp.srq = init_attr->srq;
758 my_qp->ib_qp.qp_context = init_attr->qp_context;
759 my_qp->ib_qp.event_handler = init_attr->event_handler;
762 init_attr->cap.max_inline_data = 0; /* not supported yet */
763 init_attr->cap.max_recv_sge = parms.rqueue.act_nr_sges;
764 init_attr->cap.max_recv_wr = parms.rqueue.act_nr_wqes;
765 init_attr->cap.max_send_sge = parms.squeue.act_nr_sges;
766 init_attr->cap.max_send_wr = parms.squeue.act_nr_wqes;
767 my_qp->init_attr = *init_attr;
769 if (qp_type == IB_QPT_SMI || qp_type == IB_QPT_GSI) {
770 shca->sport[init_attr->port_num - 1].ibqp_sqp[qp_type] =
772 if (ehca_nr_ports < 0) {
773 /* alloc array to cache subsequent modify qp parms
774 * for autodetect mode
777 kzalloc(EHCA_MOD_QP_PARM_MAX *
778 sizeof(*my_qp->mod_qp_parm),
780 if (!my_qp->mod_qp_parm) {
782 "Could not alloc mod_qp_parm");
783 goto create_qp_exit5;
788 /* NOTE: define_apq0() not supported yet */
789 if (qp_type == IB_QPT_GSI) {
790 h_ret = ehca_define_sqp(shca, my_qp, init_attr);
791 if (h_ret != H_SUCCESS) {
792 ret = ehca2ib_return_code(h_ret);
793 goto create_qp_exit6;
797 if (my_qp->send_cq) {
798 ret = ehca_cq_assign_qp(my_qp->send_cq, my_qp);
801 "Couldn't assign qp to send_cq ret=%i", ret);
802 goto create_qp_exit6;
806 /* copy queues, galpa data to user space */
807 if (context && udata) {
808 struct ehca_create_qp_resp resp;
809 memset(&resp, 0, sizeof(resp));
811 resp.qp_num = my_qp->real_qp_num;
812 resp.token = my_qp->token;
813 resp.qp_type = my_qp->qp_type;
814 resp.ext_type = my_qp->ext_type;
815 resp.qkey = my_qp->qkey;
816 resp.real_qp_num = my_qp->real_qp_num;
819 queue2resp(&resp.ipz_squeue, &my_qp->ipz_squeue);
821 queue2resp(&resp.ipz_rqueue, &my_qp->ipz_rqueue);
822 resp.fw_handle_ofs = (u32)
823 (my_qp->galpas.user.fw_handle & (PAGE_SIZE - 1));
825 if (ib_copy_to_udata(udata, &resp, sizeof resp)) {
826 ehca_err(pd->device, "Copy to udata failed");
828 goto create_qp_exit7;
835 ehca_cq_unassign_qp(my_qp->send_cq, my_qp->real_qp_num);
838 kfree(my_qp->mod_qp_parm);
842 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
846 vfree(my_qp->sq_map);
850 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
853 hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
856 write_lock_irqsave(&ehca_qp_idr_lock, flags);
857 idr_remove(&ehca_qp_idr, my_qp->token);
858 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
861 kmem_cache_free(qp_cache, my_qp);
862 atomic_dec(&shca->num_qps);
866 struct ib_qp *ehca_create_qp(struct ib_pd *pd,
867 struct ib_qp_init_attr *qp_init_attr,
868 struct ib_udata *udata)
872 ret = internal_create_qp(pd, qp_init_attr, NULL, udata, 0);
873 return IS_ERR(ret) ? (struct ib_qp *)ret : &ret->ib_qp;
876 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
877 struct ib_uobject *uobject);
879 struct ib_srq *ehca_create_srq(struct ib_pd *pd,
880 struct ib_srq_init_attr *srq_init_attr,
881 struct ib_udata *udata)
883 struct ib_qp_init_attr qp_init_attr;
884 struct ehca_qp *my_qp;
886 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
888 struct hcp_modify_qp_control_block *mqpcb;
889 u64 hret, update_mask;
891 /* For common attributes, internal_create_qp() takes its info
892 * out of qp_init_attr, so copy all common attrs there.
894 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
895 qp_init_attr.event_handler = srq_init_attr->event_handler;
896 qp_init_attr.qp_context = srq_init_attr->srq_context;
897 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
898 qp_init_attr.qp_type = IB_QPT_RC;
899 qp_init_attr.cap.max_recv_wr = srq_init_attr->attr.max_wr;
900 qp_init_attr.cap.max_recv_sge = srq_init_attr->attr.max_sge;
902 my_qp = internal_create_qp(pd, &qp_init_attr, srq_init_attr, udata, 1);
904 return (struct ib_srq *)my_qp;
906 /* copy back return values */
907 srq_init_attr->attr.max_wr = qp_init_attr.cap.max_recv_wr;
908 srq_init_attr->attr.max_sge = 3;
910 /* drive SRQ into RTR state */
911 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
913 ehca_err(pd->device, "Could not get zeroed page for mqpcb "
914 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
915 ret = ERR_PTR(-ENOMEM);
919 mqpcb->qp_state = EHCA_QPS_INIT;
920 mqpcb->prim_phys_port = 1;
921 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
922 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
923 my_qp->ipz_qp_handle,
926 mqpcb, my_qp->galpas.kernel);
927 if (hret != H_SUCCESS) {
928 ehca_err(pd->device, "Could not modify SRQ to INIT "
929 "ehca_qp=%p qp_num=%x h_ret=%li",
930 my_qp, my_qp->real_qp_num, hret);
934 mqpcb->qp_enable = 1;
935 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
936 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
937 my_qp->ipz_qp_handle,
940 mqpcb, my_qp->galpas.kernel);
941 if (hret != H_SUCCESS) {
942 ehca_err(pd->device, "Could not enable SRQ "
943 "ehca_qp=%p qp_num=%x h_ret=%li",
944 my_qp, my_qp->real_qp_num, hret);
948 mqpcb->qp_state = EHCA_QPS_RTR;
949 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
950 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
951 my_qp->ipz_qp_handle,
954 mqpcb, my_qp->galpas.kernel);
955 if (hret != H_SUCCESS) {
956 ehca_err(pd->device, "Could not modify SRQ to RTR "
957 "ehca_qp=%p qp_num=%x h_ret=%li",
958 my_qp, my_qp->real_qp_num, hret);
962 ehca_free_fw_ctrlblock(mqpcb);
964 return &my_qp->ib_srq;
967 ret = ERR_PTR(ehca2ib_return_code(hret));
968 ehca_free_fw_ctrlblock(mqpcb);
971 internal_destroy_qp(pd->device, my_qp, my_qp->ib_srq.uobject);
977 * prepare_sqe_rts called by internal_modify_qp() at trans sqe -> rts
978 * set purge bit of bad wqe and subsequent wqes to avoid reentering sqe
979 * returns total number of bad wqes in bad_wqe_cnt
981 static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca,
985 struct ipz_queue *squeue;
986 void *bad_send_wqe_p, *bad_send_wqe_v;
988 struct ehca_wqe *wqe;
989 int qp_num = my_qp->ib_qp.qp_num;
991 /* get send wqe pointer */
992 h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle,
993 my_qp->ipz_qp_handle, &my_qp->pf,
994 &bad_send_wqe_p, NULL, 2);
995 if (h_ret != H_SUCCESS) {
996 ehca_err(&shca->ib_device, "hipz_h_disable_and_get_wqe() failed"
997 " ehca_qp=%p qp_num=%x h_ret=%li",
998 my_qp, qp_num, h_ret);
999 return ehca2ib_return_code(h_ret);
1001 bad_send_wqe_p = (void *)((u64)bad_send_wqe_p & (~(1L << 63)));
1002 ehca_dbg(&shca->ib_device, "qp_num=%x bad_send_wqe_p=%p",
1003 qp_num, bad_send_wqe_p);
1004 /* convert wqe pointer to vadr */
1005 bad_send_wqe_v = abs_to_virt((u64)bad_send_wqe_p);
1006 if (ehca_debug_level >= 2)
1007 ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num);
1008 squeue = &my_qp->ipz_squeue;
1009 if (ipz_queue_abs_to_offset(squeue, (u64)bad_send_wqe_p, &q_ofs)) {
1010 ehca_err(&shca->ib_device, "failed to get wqe offset qp_num=%x"
1011 " bad_send_wqe_p=%p", qp_num, bad_send_wqe_p);
1015 /* loop sets wqe's purge bit */
1016 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
1018 while (wqe->optype != 0xff && wqe->wqef != 0xff) {
1019 if (ehca_debug_level >= 2)
1020 ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num);
1021 wqe->nr_of_data_seg = 0; /* suppress data access */
1022 wqe->wqef = WQEF_PURGE; /* WQE to be purged */
1023 q_ofs = ipz_queue_advance_offset(squeue, q_ofs);
1024 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
1025 *bad_wqe_cnt = (*bad_wqe_cnt)+1;
1028 * bad wqe will be reprocessed and ignored when pol_cq() is called,
1029 * i.e. nr of wqes with flush error status is one less
1031 ehca_dbg(&shca->ib_device, "qp_num=%x flusherr_wqe_cnt=%x",
1032 qp_num, (*bad_wqe_cnt)-1);
1039 * internal_modify_qp with circumvention to handle aqp0 properly
1040 * smi_reset2init indicates if this is an internal reset-to-init-call for
1041 * smi. This flag must always be zero if called from ehca_modify_qp()!
1042 * This internal func was intorduced to avoid recursion of ehca_modify_qp()!
1044 static int internal_modify_qp(struct ib_qp *ibqp,
1045 struct ib_qp_attr *attr,
1046 int attr_mask, int smi_reset2init)
1048 enum ib_qp_state qp_cur_state, qp_new_state;
1049 int cnt, qp_attr_idx, ret = 0;
1050 enum ib_qp_statetrans statetrans;
1051 struct hcp_modify_qp_control_block *mqpcb;
1052 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1053 struct ehca_shca *shca =
1054 container_of(ibqp->pd->device, struct ehca_shca, ib_device);
1057 int bad_wqe_cnt = 0;
1058 int squeue_locked = 0;
1059 unsigned long flags = 0;
1061 /* do query_qp to obtain current attr values */
1062 mqpcb = ehca_alloc_fw_ctrlblock(GFP_ATOMIC);
1064 ehca_err(ibqp->device, "Could not get zeroed page for mqpcb "
1065 "ehca_qp=%p qp_num=%x ", my_qp, ibqp->qp_num);
1069 h_ret = hipz_h_query_qp(shca->ipz_hca_handle,
1070 my_qp->ipz_qp_handle,
1072 mqpcb, my_qp->galpas.kernel);
1073 if (h_ret != H_SUCCESS) {
1074 ehca_err(ibqp->device, "hipz_h_query_qp() failed "
1075 "ehca_qp=%p qp_num=%x h_ret=%li",
1076 my_qp, ibqp->qp_num, h_ret);
1077 ret = ehca2ib_return_code(h_ret);
1078 goto modify_qp_exit1;
1081 qp_cur_state = ehca2ib_qp_state(mqpcb->qp_state);
1083 if (qp_cur_state == -EINVAL) { /* invalid qp state */
1085 ehca_err(ibqp->device, "Invalid current ehca_qp_state=%x "
1086 "ehca_qp=%p qp_num=%x",
1087 mqpcb->qp_state, my_qp, ibqp->qp_num);
1088 goto modify_qp_exit1;
1091 * circumvention to set aqp0 initial state to init
1092 * as expected by IB spec
1094 if (smi_reset2init == 0 &&
1095 ibqp->qp_type == IB_QPT_SMI &&
1096 qp_cur_state == IB_QPS_RESET &&
1097 (attr_mask & IB_QP_STATE) &&
1098 attr->qp_state == IB_QPS_INIT) { /* RESET -> INIT */
1099 struct ib_qp_attr smiqp_attr = {
1100 .qp_state = IB_QPS_INIT,
1101 .port_num = my_qp->init_attr.port_num,
1105 int smiqp_attr_mask = IB_QP_STATE | IB_QP_PORT |
1106 IB_QP_PKEY_INDEX | IB_QP_QKEY;
1107 int smirc = internal_modify_qp(
1108 ibqp, &smiqp_attr, smiqp_attr_mask, 1);
1110 ehca_err(ibqp->device, "SMI RESET -> INIT failed. "
1111 "ehca_modify_qp() rc=%i", smirc);
1113 goto modify_qp_exit1;
1115 qp_cur_state = IB_QPS_INIT;
1116 ehca_dbg(ibqp->device, "SMI RESET -> INIT succeeded");
1118 /* is transmitted current state equal to "real" current state */
1119 if ((attr_mask & IB_QP_CUR_STATE) &&
1120 qp_cur_state != attr->cur_qp_state) {
1122 ehca_err(ibqp->device,
1123 "Invalid IB_QP_CUR_STATE attr->curr_qp_state=%x <>"
1124 " actual cur_qp_state=%x. ehca_qp=%p qp_num=%x",
1125 attr->cur_qp_state, qp_cur_state, my_qp, ibqp->qp_num);
1126 goto modify_qp_exit1;
1129 ehca_dbg(ibqp->device, "ehca_qp=%p qp_num=%x current qp_state=%x "
1130 "new qp_state=%x attribute_mask=%x",
1131 my_qp, ibqp->qp_num, qp_cur_state, attr->qp_state, attr_mask);
1133 qp_new_state = attr_mask & IB_QP_STATE ? attr->qp_state : qp_cur_state;
1134 if (!smi_reset2init &&
1135 !ib_modify_qp_is_ok(qp_cur_state, qp_new_state, ibqp->qp_type,
1138 ehca_err(ibqp->device,
1139 "Invalid qp transition new_state=%x cur_state=%x "
1140 "ehca_qp=%p qp_num=%x attr_mask=%x", qp_new_state,
1141 qp_cur_state, my_qp, ibqp->qp_num, attr_mask);
1142 goto modify_qp_exit1;
1145 mqpcb->qp_state = ib2ehca_qp_state(qp_new_state);
1146 if (mqpcb->qp_state)
1147 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
1150 ehca_err(ibqp->device, "Invalid new qp state=%x "
1151 "ehca_qp=%p qp_num=%x",
1152 qp_new_state, my_qp, ibqp->qp_num);
1153 goto modify_qp_exit1;
1156 /* retrieve state transition struct to get req and opt attrs */
1157 statetrans = get_modqp_statetrans(qp_cur_state, qp_new_state);
1158 if (statetrans < 0) {
1160 ehca_err(ibqp->device, "<INVALID STATE CHANGE> qp_cur_state=%x "
1161 "new_qp_state=%x State_xsition=%x ehca_qp=%p "
1162 "qp_num=%x", qp_cur_state, qp_new_state,
1163 statetrans, my_qp, ibqp->qp_num);
1164 goto modify_qp_exit1;
1167 qp_attr_idx = ib2ehcaqptype(ibqp->qp_type);
1169 if (qp_attr_idx < 0) {
1171 ehca_err(ibqp->device,
1172 "Invalid QP type=%x ehca_qp=%p qp_num=%x",
1173 ibqp->qp_type, my_qp, ibqp->qp_num);
1174 goto modify_qp_exit1;
1177 ehca_dbg(ibqp->device,
1178 "ehca_qp=%p qp_num=%x <VALID STATE CHANGE> qp_state_xsit=%x",
1179 my_qp, ibqp->qp_num, statetrans);
1181 /* eHCA2 rev2 and higher require the SEND_GRH_FLAG to be set
1184 if ((my_qp->qp_type == IB_QPT_UD) &&
1185 (my_qp->ext_type != EQPT_LLQP) &&
1186 (statetrans == IB_QPST_INIT2RTR) &&
1187 (shca->hw_level >= 0x22)) {
1188 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1189 mqpcb->send_grh_flag = 1;
1192 /* sqe -> rts: set purge bit of bad wqe before actual trans */
1193 if ((my_qp->qp_type == IB_QPT_UD ||
1194 my_qp->qp_type == IB_QPT_GSI ||
1195 my_qp->qp_type == IB_QPT_SMI) &&
1196 statetrans == IB_QPST_SQE2RTS) {
1197 /* mark next free wqe if kernel */
1198 if (!ibqp->uobject) {
1199 struct ehca_wqe *wqe;
1200 /* lock send queue */
1201 spin_lock_irqsave(&my_qp->spinlock_s, flags);
1203 /* mark next free wqe */
1204 wqe = (struct ehca_wqe *)
1205 ipz_qeit_get(&my_qp->ipz_squeue);
1206 wqe->optype = wqe->wqef = 0xff;
1207 ehca_dbg(ibqp->device, "qp_num=%x next_free_wqe=%p",
1210 ret = prepare_sqe_rts(my_qp, shca, &bad_wqe_cnt);
1212 ehca_err(ibqp->device, "prepare_sqe_rts() failed "
1213 "ehca_qp=%p qp_num=%x ret=%i",
1214 my_qp, ibqp->qp_num, ret);
1215 goto modify_qp_exit2;
1220 * enable RDMA_Atomic_Control if reset->init und reliable con
1221 * this is necessary since gen2 does not provide that flag,
1222 * but pHyp requires it
1224 if (statetrans == IB_QPST_RESET2INIT &&
1225 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_UC)) {
1226 mqpcb->rdma_atomic_ctrl = 3;
1227 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RDMA_ATOMIC_CTRL, 1);
1229 /* circ. pHyp requires #RDMA/Atomic Resp Res for UC INIT -> RTR */
1230 if (statetrans == IB_QPST_INIT2RTR &&
1231 (ibqp->qp_type == IB_QPT_UC) &&
1232 !(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)) {
1233 mqpcb->rdma_nr_atomic_resp_res = 1; /* default to 1 */
1235 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1238 if (attr_mask & IB_QP_PKEY_INDEX) {
1239 if (attr->pkey_index >= 16) {
1241 ehca_err(ibqp->device, "Invalid pkey_index=%x. "
1242 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1243 attr->pkey_index, my_qp, ibqp->qp_num);
1244 goto modify_qp_exit2;
1246 mqpcb->prim_p_key_idx = attr->pkey_index;
1247 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_P_KEY_IDX, 1);
1249 if (attr_mask & IB_QP_PORT) {
1250 struct ehca_sport *sport;
1251 struct ehca_qp *aqp1;
1252 if (attr->port_num < 1 || attr->port_num > shca->num_ports) {
1254 ehca_err(ibqp->device, "Invalid port=%x. "
1255 "ehca_qp=%p qp_num=%x num_ports=%x",
1256 attr->port_num, my_qp, ibqp->qp_num,
1258 goto modify_qp_exit2;
1260 sport = &shca->sport[attr->port_num - 1];
1261 if (!sport->ibqp_sqp[IB_QPT_GSI]) {
1262 /* should not occur */
1264 ehca_err(ibqp->device, "AQP1 was not created for "
1265 "port=%x", attr->port_num);
1266 goto modify_qp_exit2;
1268 aqp1 = container_of(sport->ibqp_sqp[IB_QPT_GSI],
1269 struct ehca_qp, ib_qp);
1270 if (ibqp->qp_type != IB_QPT_GSI &&
1271 ibqp->qp_type != IB_QPT_SMI &&
1272 aqp1->mod_qp_parm) {
1274 * firmware will reject this modify_qp() because
1275 * port is not activated/initialized fully
1278 ehca_warn(ibqp->device, "Couldn't modify qp port=%x: "
1279 "either port is being activated (try again) "
1280 "or cabling issue", attr->port_num);
1281 goto modify_qp_exit2;
1283 mqpcb->prim_phys_port = attr->port_num;
1284 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_PHYS_PORT, 1);
1286 if (attr_mask & IB_QP_QKEY) {
1287 mqpcb->qkey = attr->qkey;
1288 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_QKEY, 1);
1290 if (attr_mask & IB_QP_AV) {
1291 mqpcb->dlid = attr->ah_attr.dlid;
1292 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID, 1);
1293 mqpcb->source_path_bits = attr->ah_attr.src_path_bits;
1294 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS, 1);
1295 mqpcb->service_level = attr->ah_attr.sl;
1296 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL, 1);
1298 if (ehca_calc_ipd(shca, mqpcb->prim_phys_port,
1299 attr->ah_attr.static_rate,
1300 &mqpcb->max_static_rate)) {
1302 goto modify_qp_exit2;
1304 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE, 1);
1307 * Always supply the GRH flag, even if it's zero, to give the
1308 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1310 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1313 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1314 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1316 if (attr->ah_attr.ah_flags == IB_AH_GRH) {
1317 mqpcb->send_grh_flag = 1;
1319 mqpcb->source_gid_idx = attr->ah_attr.grh.sgid_index;
1321 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX, 1);
1323 for (cnt = 0; cnt < 16; cnt++)
1324 mqpcb->dest_gid.byte[cnt] =
1325 attr->ah_attr.grh.dgid.raw[cnt];
1327 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_GID, 1);
1328 mqpcb->flow_label = attr->ah_attr.grh.flow_label;
1329 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL, 1);
1330 mqpcb->hop_limit = attr->ah_attr.grh.hop_limit;
1331 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT, 1);
1332 mqpcb->traffic_class = attr->ah_attr.grh.traffic_class;
1334 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS, 1);
1338 if (attr_mask & IB_QP_PATH_MTU) {
1340 my_qp->mtu_shift = attr->path_mtu + 7;
1341 mqpcb->path_mtu = attr->path_mtu;
1342 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PATH_MTU, 1);
1344 if (attr_mask & IB_QP_TIMEOUT) {
1345 mqpcb->timeout = attr->timeout;
1346 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT, 1);
1348 if (attr_mask & IB_QP_RETRY_CNT) {
1349 mqpcb->retry_count = attr->retry_cnt;
1350 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT, 1);
1352 if (attr_mask & IB_QP_RNR_RETRY) {
1353 mqpcb->rnr_retry_count = attr->rnr_retry;
1354 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT, 1);
1356 if (attr_mask & IB_QP_RQ_PSN) {
1357 mqpcb->receive_psn = attr->rq_psn;
1358 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RECEIVE_PSN, 1);
1360 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1361 mqpcb->rdma_nr_atomic_resp_res = attr->max_dest_rd_atomic < 3 ?
1362 attr->max_dest_rd_atomic : 2;
1364 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1366 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1367 mqpcb->rdma_atomic_outst_dest_qp = attr->max_rd_atomic < 3 ?
1368 attr->max_rd_atomic : 2;
1371 (MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP, 1);
1373 if (attr_mask & IB_QP_ALT_PATH) {
1374 if (attr->alt_port_num < 1
1375 || attr->alt_port_num > shca->num_ports) {
1377 ehca_err(ibqp->device, "Invalid alt_port=%x. "
1378 "ehca_qp=%p qp_num=%x num_ports=%x",
1379 attr->alt_port_num, my_qp, ibqp->qp_num,
1381 goto modify_qp_exit2;
1383 mqpcb->alt_phys_port = attr->alt_port_num;
1385 if (attr->alt_pkey_index >= 16) {
1387 ehca_err(ibqp->device, "Invalid alt_pkey_index=%x. "
1388 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1389 attr->pkey_index, my_qp, ibqp->qp_num);
1390 goto modify_qp_exit2;
1392 mqpcb->alt_p_key_idx = attr->alt_pkey_index;
1394 mqpcb->timeout_al = attr->alt_timeout;
1395 mqpcb->dlid_al = attr->alt_ah_attr.dlid;
1396 mqpcb->source_path_bits_al = attr->alt_ah_attr.src_path_bits;
1397 mqpcb->service_level_al = attr->alt_ah_attr.sl;
1399 if (ehca_calc_ipd(shca, mqpcb->alt_phys_port,
1400 attr->alt_ah_attr.static_rate,
1401 &mqpcb->max_static_rate_al)) {
1403 goto modify_qp_exit2;
1406 /* OpenIB doesn't support alternate retry counts - copy them */
1407 mqpcb->retry_count_al = mqpcb->retry_count;
1408 mqpcb->rnr_retry_count_al = mqpcb->rnr_retry_count;
1410 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_ALT_PHYS_PORT, 1)
1411 | EHCA_BMASK_SET(MQPCB_MASK_ALT_P_KEY_IDX, 1)
1412 | EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT_AL, 1)
1413 | EHCA_BMASK_SET(MQPCB_MASK_DLID_AL, 1)
1414 | EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS_AL, 1)
1415 | EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL_AL, 1)
1416 | EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE_AL, 1)
1417 | EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT_AL, 1)
1418 | EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT_AL, 1);
1421 * Always supply the GRH flag, even if it's zero, to give the
1422 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1424 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG_AL, 1);
1427 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1428 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1430 if (attr->alt_ah_attr.ah_flags == IB_AH_GRH) {
1431 mqpcb->send_grh_flag_al = 1;
1433 for (cnt = 0; cnt < 16; cnt++)
1434 mqpcb->dest_gid_al.byte[cnt] =
1435 attr->alt_ah_attr.grh.dgid.raw[cnt];
1436 mqpcb->source_gid_idx_al =
1437 attr->alt_ah_attr.grh.sgid_index;
1438 mqpcb->flow_label_al = attr->alt_ah_attr.grh.flow_label;
1439 mqpcb->hop_limit_al = attr->alt_ah_attr.grh.hop_limit;
1440 mqpcb->traffic_class_al =
1441 attr->alt_ah_attr.grh.traffic_class;
1444 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX_AL, 1)
1445 | EHCA_BMASK_SET(MQPCB_MASK_DEST_GID_AL, 1)
1446 | EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL_AL, 1)
1447 | EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT_AL, 1) |
1448 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS_AL, 1);
1452 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1453 mqpcb->min_rnr_nak_timer_field = attr->min_rnr_timer;
1455 EHCA_BMASK_SET(MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD, 1);
1458 if (attr_mask & IB_QP_SQ_PSN) {
1459 mqpcb->send_psn = attr->sq_psn;
1460 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_PSN, 1);
1463 if (attr_mask & IB_QP_DEST_QPN) {
1464 mqpcb->dest_qp_nr = attr->dest_qp_num;
1465 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_QP_NR, 1);
1468 if (attr_mask & IB_QP_PATH_MIG_STATE) {
1469 if (attr->path_mig_state != IB_MIG_REARM
1470 && attr->path_mig_state != IB_MIG_MIGRATED) {
1472 ehca_err(ibqp->device, "Invalid mig_state=%x",
1473 attr->path_mig_state);
1474 goto modify_qp_exit2;
1476 mqpcb->path_migration_state = attr->path_mig_state + 1;
1477 if (attr->path_mig_state == IB_MIG_REARM)
1478 my_qp->mig_armed = 1;
1480 EHCA_BMASK_SET(MQPCB_MASK_PATH_MIGRATION_STATE, 1);
1483 if (attr_mask & IB_QP_CAP) {
1484 mqpcb->max_nr_outst_send_wr = attr->cap.max_send_wr+1;
1486 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_SEND_WR, 1);
1487 mqpcb->max_nr_outst_recv_wr = attr->cap.max_recv_wr+1;
1489 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_RECV_WR, 1);
1490 /* no support for max_send/recv_sge yet */
1493 if (ehca_debug_level >= 2)
1494 ehca_dmp(mqpcb, 4*70, "qp_num=%x", ibqp->qp_num);
1496 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1497 my_qp->ipz_qp_handle,
1500 mqpcb, my_qp->galpas.kernel);
1502 if (h_ret != H_SUCCESS) {
1503 ret = ehca2ib_return_code(h_ret);
1504 ehca_err(ibqp->device, "hipz_h_modify_qp() failed h_ret=%li "
1505 "ehca_qp=%p qp_num=%x", h_ret, my_qp, ibqp->qp_num);
1506 goto modify_qp_exit2;
1509 if ((my_qp->qp_type == IB_QPT_UD ||
1510 my_qp->qp_type == IB_QPT_GSI ||
1511 my_qp->qp_type == IB_QPT_SMI) &&
1512 statetrans == IB_QPST_SQE2RTS) {
1513 /* doorbell to reprocessing wqes */
1514 iosync(); /* serialize GAL register access */
1515 hipz_update_sqa(my_qp, bad_wqe_cnt-1);
1516 ehca_gen_dbg("doorbell for %x wqes", bad_wqe_cnt);
1519 if (statetrans == IB_QPST_RESET2INIT ||
1520 statetrans == IB_QPST_INIT2INIT) {
1521 mqpcb->qp_enable = 1;
1522 mqpcb->qp_state = EHCA_QPS_INIT;
1524 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
1526 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1527 my_qp->ipz_qp_handle,
1531 my_qp->galpas.kernel);
1533 if (h_ret != H_SUCCESS) {
1534 ret = ehca2ib_return_code(h_ret);
1535 ehca_err(ibqp->device, "ENABLE in context of "
1536 "RESET_2_INIT failed! Maybe you didn't get "
1537 "a LID h_ret=%li ehca_qp=%p qp_num=%x",
1538 h_ret, my_qp, ibqp->qp_num);
1539 goto modify_qp_exit2;
1543 if (statetrans == IB_QPST_ANY2RESET) {
1544 ipz_qeit_reset(&my_qp->ipz_rqueue);
1545 ipz_qeit_reset(&my_qp->ipz_squeue);
1548 if (attr_mask & IB_QP_QKEY)
1549 my_qp->qkey = attr->qkey;
1552 if (squeue_locked) { /* this means: sqe -> rts */
1553 spin_unlock_irqrestore(&my_qp->spinlock_s, flags);
1554 my_qp->sqerr_purgeflag = 1;
1558 ehca_free_fw_ctrlblock(mqpcb);
1563 int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
1564 struct ib_udata *udata)
1568 struct ehca_shca *shca = container_of(ibqp->device, struct ehca_shca,
1570 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1572 /* The if-block below caches qp_attr to be modified for GSI and SMI
1573 * qps during the initialization by ib_mad. When the respective port
1574 * is activated, ie we got an event PORT_ACTIVE, we'll replay the
1575 * cached modify calls sequence, see ehca_recover_sqs() below.
1576 * Why that is required:
1577 * 1) If one port is connected, older code requires that port one
1578 * to be connected and module option nr_ports=1 to be given by
1579 * user, which is very inconvenient for end user.
1580 * 2) Firmware accepts modify_qp() only if respective port has become
1581 * active. Older code had a wait loop of 30sec create_qp()/
1582 * define_aqp1(), which is not appropriate in practice. This
1583 * code now removes that wait loop, see define_aqp1(), and always
1584 * reports all ports to ib_mad resp. users. Only activated ports
1585 * will then usable for the users.
1587 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1588 int port = my_qp->init_attr.port_num;
1589 struct ehca_sport *sport = &shca->sport[port - 1];
1590 unsigned long flags;
1591 spin_lock_irqsave(&sport->mod_sqp_lock, flags);
1592 /* cache qp_attr only during init */
1593 if (my_qp->mod_qp_parm) {
1594 struct ehca_mod_qp_parm *p;
1595 if (my_qp->mod_qp_parm_idx >= EHCA_MOD_QP_PARM_MAX) {
1596 ehca_err(&shca->ib_device,
1597 "mod_qp_parm overflow state=%x port=%x"
1598 " type=%x", attr->qp_state,
1599 my_qp->init_attr.port_num,
1601 spin_unlock_irqrestore(&sport->mod_sqp_lock,
1605 p = &my_qp->mod_qp_parm[my_qp->mod_qp_parm_idx];
1606 p->mask = attr_mask;
1608 my_qp->mod_qp_parm_idx++;
1609 ehca_dbg(&shca->ib_device,
1610 "Saved qp_attr for state=%x port=%x type=%x",
1611 attr->qp_state, my_qp->init_attr.port_num,
1613 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1616 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1619 ret = internal_modify_qp(ibqp, attr, attr_mask, 0);
1622 if ((ret == 0) && (attr_mask & IB_QP_STATE))
1623 my_qp->state = attr->qp_state;
1628 void ehca_recover_sqp(struct ib_qp *sqp)
1630 struct ehca_qp *my_sqp = container_of(sqp, struct ehca_qp, ib_qp);
1631 int port = my_sqp->init_attr.port_num;
1632 struct ib_qp_attr attr;
1633 struct ehca_mod_qp_parm *qp_parm;
1634 int i, qp_parm_idx, ret;
1635 unsigned long flags, wr_cnt;
1637 if (!my_sqp->mod_qp_parm)
1639 ehca_dbg(sqp->device, "SQP port=%x qp_num=%x", port, sqp->qp_num);
1641 qp_parm = my_sqp->mod_qp_parm;
1642 qp_parm_idx = my_sqp->mod_qp_parm_idx;
1643 for (i = 0; i < qp_parm_idx; i++) {
1644 attr = qp_parm[i].attr;
1645 ret = internal_modify_qp(sqp, &attr, qp_parm[i].mask, 0);
1647 ehca_err(sqp->device, "Could not modify SQP port=%x "
1648 "qp_num=%x ret=%x", port, sqp->qp_num, ret);
1651 ehca_dbg(sqp->device, "SQP port=%x qp_num=%x in state=%x",
1652 port, sqp->qp_num, attr.qp_state);
1655 /* re-trigger posted recv wrs */
1656 wr_cnt = my_sqp->ipz_rqueue.current_q_offset /
1657 my_sqp->ipz_rqueue.qe_size;
1659 spin_lock_irqsave(&my_sqp->spinlock_r, flags);
1660 hipz_update_rqa(my_sqp, wr_cnt);
1661 spin_unlock_irqrestore(&my_sqp->spinlock_r, flags);
1662 ehca_dbg(sqp->device, "doorbell port=%x qp_num=%x wr_cnt=%lx",
1663 port, sqp->qp_num, wr_cnt);
1668 /* this prevents subsequent calls to modify_qp() to cache qp_attr */
1669 my_sqp->mod_qp_parm = NULL;
1672 int ehca_query_qp(struct ib_qp *qp,
1673 struct ib_qp_attr *qp_attr,
1674 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1676 struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp);
1677 struct ehca_shca *shca = container_of(qp->device, struct ehca_shca,
1679 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1680 struct hcp_modify_qp_control_block *qpcb;
1684 if (qp_attr_mask & QP_ATTR_QUERY_NOT_SUPPORTED) {
1685 ehca_err(qp->device, "Invalid attribute mask "
1686 "ehca_qp=%p qp_num=%x qp_attr_mask=%x ",
1687 my_qp, qp->qp_num, qp_attr_mask);
1691 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1693 ehca_err(qp->device, "Out of memory for qpcb "
1694 "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num);
1698 h_ret = hipz_h_query_qp(adapter_handle,
1699 my_qp->ipz_qp_handle,
1701 qpcb, my_qp->galpas.kernel);
1703 if (h_ret != H_SUCCESS) {
1704 ret = ehca2ib_return_code(h_ret);
1705 ehca_err(qp->device, "hipz_h_query_qp() failed "
1706 "ehca_qp=%p qp_num=%x h_ret=%li",
1707 my_qp, qp->qp_num, h_ret);
1708 goto query_qp_exit1;
1711 qp_attr->cur_qp_state = ehca2ib_qp_state(qpcb->qp_state);
1712 qp_attr->qp_state = qp_attr->cur_qp_state;
1714 if (qp_attr->cur_qp_state == -EINVAL) {
1716 ehca_err(qp->device, "Got invalid ehca_qp_state=%x "
1717 "ehca_qp=%p qp_num=%x",
1718 qpcb->qp_state, my_qp, qp->qp_num);
1719 goto query_qp_exit1;
1722 if (qp_attr->qp_state == IB_QPS_SQD)
1723 qp_attr->sq_draining = 1;
1725 qp_attr->qkey = qpcb->qkey;
1726 qp_attr->path_mtu = qpcb->path_mtu;
1727 qp_attr->path_mig_state = qpcb->path_migration_state - 1;
1728 qp_attr->rq_psn = qpcb->receive_psn;
1729 qp_attr->sq_psn = qpcb->send_psn;
1730 qp_attr->min_rnr_timer = qpcb->min_rnr_nak_timer_field;
1731 qp_attr->cap.max_send_wr = qpcb->max_nr_outst_send_wr-1;
1732 qp_attr->cap.max_recv_wr = qpcb->max_nr_outst_recv_wr-1;
1733 /* UD_AV CIRCUMVENTION */
1734 if (my_qp->qp_type == IB_QPT_UD) {
1735 qp_attr->cap.max_send_sge =
1736 qpcb->actual_nr_sges_in_sq_wqe - 2;
1737 qp_attr->cap.max_recv_sge =
1738 qpcb->actual_nr_sges_in_rq_wqe - 2;
1740 qp_attr->cap.max_send_sge =
1741 qpcb->actual_nr_sges_in_sq_wqe;
1742 qp_attr->cap.max_recv_sge =
1743 qpcb->actual_nr_sges_in_rq_wqe;
1746 qp_attr->cap.max_inline_data = my_qp->sq_max_inline_data_size;
1747 qp_attr->dest_qp_num = qpcb->dest_qp_nr;
1749 qp_attr->pkey_index =
1750 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->prim_p_key_idx);
1753 EHCA_BMASK_GET(MQPCB_PRIM_PHYS_PORT, qpcb->prim_phys_port);
1755 qp_attr->timeout = qpcb->timeout;
1756 qp_attr->retry_cnt = qpcb->retry_count;
1757 qp_attr->rnr_retry = qpcb->rnr_retry_count;
1759 qp_attr->alt_pkey_index =
1760 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->alt_p_key_idx);
1762 qp_attr->alt_port_num = qpcb->alt_phys_port;
1763 qp_attr->alt_timeout = qpcb->timeout_al;
1765 qp_attr->max_dest_rd_atomic = qpcb->rdma_nr_atomic_resp_res;
1766 qp_attr->max_rd_atomic = qpcb->rdma_atomic_outst_dest_qp;
1769 qp_attr->ah_attr.sl = qpcb->service_level;
1771 if (qpcb->send_grh_flag) {
1772 qp_attr->ah_attr.ah_flags = IB_AH_GRH;
1775 qp_attr->ah_attr.static_rate = qpcb->max_static_rate;
1776 qp_attr->ah_attr.dlid = qpcb->dlid;
1777 qp_attr->ah_attr.src_path_bits = qpcb->source_path_bits;
1778 qp_attr->ah_attr.port_num = qp_attr->port_num;
1781 qp_attr->ah_attr.grh.traffic_class = qpcb->traffic_class;
1782 qp_attr->ah_attr.grh.hop_limit = qpcb->hop_limit;
1783 qp_attr->ah_attr.grh.sgid_index = qpcb->source_gid_idx;
1784 qp_attr->ah_attr.grh.flow_label = qpcb->flow_label;
1786 for (cnt = 0; cnt < 16; cnt++)
1787 qp_attr->ah_attr.grh.dgid.raw[cnt] =
1788 qpcb->dest_gid.byte[cnt];
1791 qp_attr->alt_ah_attr.sl = qpcb->service_level_al;
1792 if (qpcb->send_grh_flag_al) {
1793 qp_attr->alt_ah_attr.ah_flags = IB_AH_GRH;
1796 qp_attr->alt_ah_attr.static_rate = qpcb->max_static_rate_al;
1797 qp_attr->alt_ah_attr.dlid = qpcb->dlid_al;
1798 qp_attr->alt_ah_attr.src_path_bits = qpcb->source_path_bits_al;
1801 qp_attr->alt_ah_attr.grh.traffic_class = qpcb->traffic_class_al;
1802 qp_attr->alt_ah_attr.grh.hop_limit = qpcb->hop_limit_al;
1803 qp_attr->alt_ah_attr.grh.sgid_index = qpcb->source_gid_idx_al;
1804 qp_attr->alt_ah_attr.grh.flow_label = qpcb->flow_label_al;
1806 for (cnt = 0; cnt < 16; cnt++)
1807 qp_attr->alt_ah_attr.grh.dgid.raw[cnt] =
1808 qpcb->dest_gid_al.byte[cnt];
1810 /* return init attributes given in ehca_create_qp */
1812 *qp_init_attr = my_qp->init_attr;
1814 if (ehca_debug_level >= 2)
1815 ehca_dmp(qpcb, 4*70, "qp_num=%x", qp->qp_num);
1818 ehca_free_fw_ctrlblock(qpcb);
1823 int ehca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1824 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
1826 struct ehca_qp *my_qp =
1827 container_of(ibsrq, struct ehca_qp, ib_srq);
1828 struct ehca_shca *shca =
1829 container_of(ibsrq->pd->device, struct ehca_shca, ib_device);
1830 struct hcp_modify_qp_control_block *mqpcb;
1835 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1837 ehca_err(ibsrq->device, "Could not get zeroed page for mqpcb "
1838 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
1843 if (attr_mask & IB_SRQ_LIMIT) {
1844 attr_mask &= ~IB_SRQ_LIMIT;
1846 EHCA_BMASK_SET(MQPCB_MASK_CURR_SRQ_LIMIT, 1)
1847 | EHCA_BMASK_SET(MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG, 1);
1848 mqpcb->curr_srq_limit =
1849 EHCA_BMASK_SET(MQPCB_CURR_SRQ_LIMIT, attr->srq_limit);
1850 mqpcb->qp_aff_asyn_ev_log_reg =
1851 EHCA_BMASK_SET(QPX_AAELOG_RESET_SRQ_LIMIT, 1);
1854 /* by now, all bits in attr_mask should have been cleared */
1856 ehca_err(ibsrq->device, "invalid attribute mask bits set "
1857 "attr_mask=%x", attr_mask);
1859 goto modify_srq_exit0;
1862 if (ehca_debug_level >= 2)
1863 ehca_dmp(mqpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1865 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, my_qp->ipz_qp_handle,
1866 NULL, update_mask, mqpcb,
1867 my_qp->galpas.kernel);
1869 if (h_ret != H_SUCCESS) {
1870 ret = ehca2ib_return_code(h_ret);
1871 ehca_err(ibsrq->device, "hipz_h_modify_qp() failed h_ret=%li "
1872 "ehca_qp=%p qp_num=%x",
1873 h_ret, my_qp, my_qp->real_qp_num);
1877 ehca_free_fw_ctrlblock(mqpcb);
1882 int ehca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr)
1884 struct ehca_qp *my_qp = container_of(srq, struct ehca_qp, ib_srq);
1885 struct ehca_shca *shca = container_of(srq->device, struct ehca_shca,
1887 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1888 struct hcp_modify_qp_control_block *qpcb;
1892 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1894 ehca_err(srq->device, "Out of memory for qpcb "
1895 "ehca_qp=%p qp_num=%x", my_qp, my_qp->real_qp_num);
1899 h_ret = hipz_h_query_qp(adapter_handle, my_qp->ipz_qp_handle,
1900 NULL, qpcb, my_qp->galpas.kernel);
1902 if (h_ret != H_SUCCESS) {
1903 ret = ehca2ib_return_code(h_ret);
1904 ehca_err(srq->device, "hipz_h_query_qp() failed "
1905 "ehca_qp=%p qp_num=%x h_ret=%li",
1906 my_qp, my_qp->real_qp_num, h_ret);
1907 goto query_srq_exit1;
1910 srq_attr->max_wr = qpcb->max_nr_outst_recv_wr - 1;
1911 srq_attr->max_sge = 3;
1912 srq_attr->srq_limit = EHCA_BMASK_GET(
1913 MQPCB_CURR_SRQ_LIMIT, qpcb->curr_srq_limit);
1915 if (ehca_debug_level >= 2)
1916 ehca_dmp(qpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1919 ehca_free_fw_ctrlblock(qpcb);
1924 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
1925 struct ib_uobject *uobject)
1927 struct ehca_shca *shca = container_of(dev, struct ehca_shca, ib_device);
1928 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1930 struct ehca_sport *sport = &shca->sport[my_qp->init_attr.port_num - 1];
1931 u32 qp_num = my_qp->real_qp_num;
1935 enum ib_qp_type qp_type;
1936 unsigned long flags;
1939 if (my_qp->mm_count_galpa ||
1940 my_qp->mm_count_rqueue || my_qp->mm_count_squeue) {
1941 ehca_err(dev, "Resources still referenced in "
1942 "user space qp_num=%x", qp_num);
1947 if (my_qp->send_cq) {
1948 ret = ehca_cq_unassign_qp(my_qp->send_cq, qp_num);
1950 ehca_err(dev, "Couldn't unassign qp from "
1951 "send_cq ret=%i qp_num=%x cq_num=%x", ret,
1952 qp_num, my_qp->send_cq->cq_number);
1957 write_lock_irqsave(&ehca_qp_idr_lock, flags);
1958 idr_remove(&ehca_qp_idr, my_qp->token);
1959 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
1961 /* now wait until all pending events have completed */
1962 wait_event(my_qp->wait_completion, !atomic_read(&my_qp->nr_events));
1964 h_ret = hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
1965 if (h_ret != H_SUCCESS) {
1966 ehca_err(dev, "hipz_h_destroy_qp() failed h_ret=%li "
1967 "ehca_qp=%p qp_num=%x", h_ret, my_qp, qp_num);
1968 return ehca2ib_return_code(h_ret);
1971 port_num = my_qp->init_attr.port_num;
1972 qp_type = my_qp->init_attr.qp_type;
1974 if (qp_type == IB_QPT_SMI || qp_type == IB_QPT_GSI) {
1975 spin_lock_irqsave(&sport->mod_sqp_lock, flags);
1976 kfree(my_qp->mod_qp_parm);
1977 my_qp->mod_qp_parm = NULL;
1978 shca->sport[port_num - 1].ibqp_sqp[qp_type] = NULL;
1979 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1982 /* no support for IB_QPT_SMI yet */
1983 if (qp_type == IB_QPT_GSI) {
1984 struct ib_event event;
1985 ehca_info(dev, "device %s: port %x is inactive.",
1986 shca->ib_device.name, port_num);
1987 event.device = &shca->ib_device;
1988 event.event = IB_EVENT_PORT_ERR;
1989 event.element.port_num = port_num;
1990 shca->sport[port_num - 1].port_state = IB_PORT_DOWN;
1991 ib_dispatch_event(&event);
1995 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
1996 if (HAS_SQ(my_qp)) {
1997 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
1998 vfree(my_qp->sq_map);
2000 kmem_cache_free(qp_cache, my_qp);
2001 atomic_dec(&shca->num_qps);
2005 int ehca_destroy_qp(struct ib_qp *qp)
2007 return internal_destroy_qp(qp->device,
2008 container_of(qp, struct ehca_qp, ib_qp),
2012 int ehca_destroy_srq(struct ib_srq *srq)
2014 return internal_destroy_qp(srq->device,
2015 container_of(srq, struct ehca_qp, ib_srq),
2019 int ehca_init_qp_cache(void)
2021 qp_cache = kmem_cache_create("ehca_cache_qp",
2022 sizeof(struct ehca_qp), 0,
2030 void ehca_cleanup_qp_cache(void)
2033 kmem_cache_destroy(qp_cache);